Abstract
An effective method is proposed to reduce dynamic power for synchronous 2-read/write (2RW) 8T dual-port (DP) SRAM. Adjusting the wordline (WL) pulse timing control circuit is newly introduced for both reading and writing operations. Row addresses of port-A and port-B are compared. The same row access is detected or not in each cycle, which is an inherent access mode of 2RW 8T DP SRAM. In different row access, the WL pulse width is shortened to reduce excessive bitline (BL) discharging power. A well balanced 8T DP SRAM bitcell layout is demonstrated using 40-nm technology. A test chip including 512 w × 73 b 36 kbit and 2 kw × 19 b (38 kbit) 2RW DP SRAM macros was designed and fabricated using 40-nm technology. The measured data show that reading and writing powers are reduced, respectively, by ∼7% and ∼18% using the proposed scheme.
Published Version
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