A Test Screening Method for 28 nm HK/MG Single-Port and Dual-Port SRAMs Considering with Dynamic Stability and Read/Write Disturb Issues

Abstract

We first discuss the dynamic stability of embedded SRAMs in 28-nm high-k/metal-gate (HK/MG) bulk CMOS technology. The good correlation between simulation result and measured data of the SRAM operation voltage Vmin is shown. Second, we introduce the test screening circuitries considering with dynamic stability for not only 6T single-port (SP) SRAM but also 8T dual-port (DP) SRAM. We designed and fabricated test chips, which include 1-Mb SP-SRAM and 512-kb DP-SRAM macros, using 28-nm technology. We obtain the appropriate screening results from the evaluation results of the test-chip thanks to the additional test screening circuitries. It is also confirmed assured screening of failures in the write/read disturb operations for DP-SRAM.