Jitter Testing Research Articles

Study on the design of single-seat control valve with stable flow regulation and its fluid flow characteristics and thermal stress

Aiming at technical problems such as unstable flow at small openings and uneven force on the valve core, the single-seat control valve with stable flow regulation is researched and designed. The tapered surface of the outer edge of the valve core can cooperate with the valve seat when the valve core is running stably, resulting in higher flow regulation accuracy and more stable regulation. The mechanical characteristics and flow characteristics are analyzed. The fluid flow simulation analyzes the pressure, velocity, density, mass flow rate and volume flow rate of the fluid under small and large openings of the single-seat control valve. The relationship between the maximum pressure, maximum velocity, maximum density, mass flow rate and volume flow rate of the inlet and outlet with the opening are analyzed from small opening to large opening and smaller opening. The spool motion simulation analyzes the relationship between actuator driving force, unbalanced force, linear displacement, velocity and acceleration with time. The thermal stress simulation analyzes the thermal temperature, resultant heat flow, thermal stress, thermal strain and safety factor, and the material strength meets the requirements. The valve body pressure test, valve seat sealing test, full stroke and switching time test, drift and jitter test, starting deviation test, basic error and return difference test and dead zone test are carried out on the single-seat control valve. The test results all meet the requirements. The simulation results are compared and analyzed with the test results, and the simulation results are consistent with the test result.

PERBANDINGAN KUALITAS LAYANAN KINERJA PERANGKAT JARINGAN TP-LINK WIRELESS N ROUTER DAN GL- INET WIRELESS ROUTER BERBASIS FIRMWARE OPENWRT

The development of the internet network and network equipment is currently very rapid, to meet the needs of internet usage, network devices are used as supporting tools in service access and network deployment. According to research conducted in a performance comparison analysis between the default firmware and the openwrt firmware [1], the performance of the network device is not only determined by the hardware specifications contained in the network device, but is also determined by the firmware in the network device. according to a literature review from various sources that the openwrt firmware can be used as a firmware solution to improve the performance of network devices that have limited service features and as firmware updates for network devices that do not get development support from vendors.The research will be conducted by analyzing the comparison of the performance of the Gl iNet Wireless Router network device which was created for the openwrt firmware and already using the openwrt firmware from the manufacturer, with the Tp Link Wireless Router network device, which is a network device that will implement the openwrt firmware. The design is carried out using the PPDIOO Life-Cycle Approach network development method, and a comparative analysis of network quality using QoS (Quality of Service) parameters.The final result of this research is how to implement and how the openwrt firmware runs on network devices that are not actually using the original firmware based on the results of network parameters jitter, delay, packet loss, throughput and signal strength testing in internet service access.
 Keywords : OpenWrt, Quality of Service, PPDIOO, Life-Cycle Approach.

A Scanner Jitter Test Method of CR System Based on Improved Hough Transform Algorithm

Computed radiology system (CR) test technology has been applied in the testing of industrial welding defect after the promulgation and implementation of digital radiographic imaging test standards. The performance of CR system directly affects the testing rate of welding defects. Therefore, testing and evaluating the performance of CR system becomes the premise and guarantee for the application of CR system. In this paper, based on the testing image of CR phantom and the simulation of scanner dither results, an algorithm combining fault-tolerant voting and improved point-based hoof transform is proposed to test the performance index of scanner dither in CR system. Experimental results show that the proposed algorithm can test not only the row and column dithering, but also the subtle arc dithering. Compared with standard Hough transform algorithm, this algorithm has higher accuracy and can avoid the influence of other image indicators around the T-shaped image quality indicator used in CR phantom.

DESAIN JARINGAN WIRELESS MENGGUNAKAN DISTRIBUTION SYSTEM (WDS) DAN PENGUJIAN BERDASARKAN QUALITY OF SERVICE (QOS)

Tujuan dari penelitian ini adalah merancang jaringan wireless yang memanfaatkan jalur wireless sebagai backbone pada semua access point kecuali basestation point yang tetap mempergunakan kabel UTP sebagai backbone-nya dan memperluas area jangkauan jaringan wireless yang mampu mencakup seluruh bagian di Universitas Widyatama. Hasil desain jaringan wireless dengan WDS akan diuji dengan melakukan simulasi. Kemudian pengujian akan difokuskan pada parameter delay, packet loss, throughput, dan jitter dengan menggunakan metode Quality of Service (QoS) menggunakan aplikasi Axence netTools. Desain jaringan wireless dengan Wireless Distribution System (WDS) memiliki tingkat fleksibilitas yang lebih baik daripada backbone yang menggunakan kabel Unshielded Twisted Pair (UTP). Hasil pengujian menunjukkan bahwa throughput, delay, packet loss, dan jitter menunjukkan hasil yang bagus. Hasil pengujian throughput didapatkan nilai rata-rata throughput dengan presentase sebesar 90%, dapat dikategorikan BAGUS dengan indeks 3, sedangkan hasil pengujian delay didapatkan nilai rata-rata sebesar107,8 dapat dikategorikan SANGAT BAGUS dengan indeks 4, kemudian nilai rata-rata packet loss dengan presentase 2%, dapat dikategorikan BAGUS dengan indeks 3, dan hasil pengujian jitter diperoleh nilai yang bervariasi dengan nilai rata-rata jitter sebesar 1,71 ms, dapat dikategorikan BAGUS dengan indeks 3.

Manajemen Alokasi Bandwidth Layanan Internet Menggunakan Fractional Knapsack Problem

The technical problems faced in e-government implemented by the Ministry of Religion of Indonesia since 2015 are minimal bandwidth requirements to provide information services and behavior of users who access entertainment sites. When peak hours occur, the congested network often occurs which becomes a significant bottleneck. This study aims to implement bandwidth management using the fractional knapsack problem method by limiting access to entertainment services. The QoS parameters used in this management are throughput, delay, and jitter. The method was tested using a paired t-test using throughput, jitter, and delay test parameters by comparing test parameters before and after bandwidth management applied. The significance value produced is between 75-85%. The method used can control the amount of traffic for each service, but on the other, hand the delay and jitter are still high. It is necessary to add additional free space to each service that can be used when needed to reduce the delay and jitter.

The research micro-vibration detecting optical imaging system verification

In order to reduce the influence of vibration on the imaging quality of space cameras, the ground simulation micro-vibration imaging detection optics is carried out, which is convenient for the off-line image recovery technology of measurement information. In this paper, the collimator system is selected as the optical system to simulate the characteristic target from infinity. The LIGHTTOOLS software is used to simulate the optical path. The system is studied through four experiments, namely camera excitation jitter test, target motion simulation optical axis jitter test, The wave-front distortion measurement test and the defocus measurement test analyze and compensate the optical error of the space camera through off-line image restoration. The test results show that when the camera is not excited, the camera outputs a clear image through the collimator system, which meets the requirements of the micro-vibration imaging test. In the micro-vibration imaging test, when the wave-front aberration reaches 0.21λ and 0.23λ, the imaging of the collimator system can meet the processing requirements of the recovery software. The result proves that the collimator system can be effectively applied to micro-vibration imaging. The detection system has the ability to successfully verify micro-vibration imaging detection tests.

Accurate and cost‐effective technique for jitter and noise separation based on single‐frequency measurement

A simple and cost-effective technique is proposed for jitter and noise separation in ADC test. On the basis of the property that clock jitter is modulated by the slope of input signal, few simple mathematical manipulations are performed on a single data record of ADC output to separate jitter and noise. The proposed method requires only one high-frequency signal test and eliminates the need for a second low-frequency test in conventional dual-frequency jitter tests. Compared with existing single-frequency test, the new method is accurate and robust to non-harmonic distortion, without requiring any additional data acquisition time. Therefore, both hardware overhead and data acquisition time are saved significantly. Experimental results show that both jitter and signal-to-noise ratio are estimated accurately, and the accuracy of jitter estimation is comparable with that of conventional dual-frequency test.

基于脉宽收缩和累积寄存器的片上时钟抖动测试电路

An on-chip clock jitter testing circuit based on pulse-shrinkage TDC and accumulation register is introduced in this paper, which can be used to monitor the jitter of internal clock signal with sub-gate delay resolution. The whole testing circuit is consisted of pulse-shrinkage loop, accumulation register, XOR array, counter and control circuit. All the pulse-shrinkage units are connected in a loop to reduce the required number, so that the area can be saved and the effects of process variations can be reduced. Multi-cycle clock pulse measurement results are accumulated simultaneously and output in the form of serial code in monitor-mode, the clock jitter can be read directly from the serial code. The whole circuit is designed in a 65-nm CMOS process, simulation results show that the circuit can measure several GHz clock signal, with a resolution of 1 ps.

Development of multi-degree-of-freedom microvibration emulator for efficient jitter test of spacecraft

A number of components and payload systems installed in satellites are found to be exposed to various disturbance sources, such as the reaction wheel assembly, the control moment gyro, coolers, and others. Low damping in space causes continuous microvibration that degrades the performance of various payload systems; this is customarily called jitter problem in spacecraft community. Various isolation systems have been developed to improve the performance of the optical payloads under the microvibration environments. During the spacecraft development process, an experimental validation of jitter effects (either controlled or not) on the performance of optical payloads using all the flight model components is not often conducted due to the scheduling issue or the product assurance activities. The disturbance characteristics of a prototype or an engineering model of the disturbance source such as reaction wheel assembly are significantly different from their flight model counterparts. Therefore, in order to facilitate jitter test as well as the performance evaluations of an isolator during the satellite development process, this article proposes a microvibration emulator that generates the real disturbance spectrums of flight models. The development procedure for the reaction wheel assembly emulator is described. Prototype single-axis and three-axis microvibration emulators are demonstrated, and the performances are evaluated by means of disturbance characteristics similar to those of the reaction wheel assembly.

Oversampled multi-phase time-domain bit-error rate processing for transmitter testing

High speed serial interfaces (HSSI) are continually pushed toward operating at higher speed to meet the demand for higher bandwidth. As a result, the timing constraints for HSSI devices get tighter. Consequently, HSSI devices experience issues such as timing jitter and bit-errors. This paper investigates techniques to speed up HSSI bit-error rate and jitter testing. The proposed oversampling-based transmitter test scheme accelerates transmitter jitter and eye diagram testing by means of a multi-phase bit-error rate test circuit (BERT). The proposed scheme creates parallel BERT elements working in conjunction that are able to digitize the input signal jitter behavior in a multi-phase manner. The more phases we deploy the faster the test is completed. We accurately extract the transmitter jitter in time domain and finish the whole transmitter test within tens of milliseconds, exceeding the current norm of 100 ms.

The Instrument Bandwidth Effect in Jitter and BER Test for High-Speed Serial Interconnection

Different from other electronics measurement, the bandwidth of the instrument can affect the test results more seriously in jitter and bit-error rate (BER) test. This paper analyzes the effect on the jitter and BER test results caused by instrument bandwidth in high-speed serial interconnection. An algorithm is presented to measure and estimate the equivalent frequency response of instruments. Computed data-dependent jitter (DDJ) results are produced based on the <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">S</i> -parameter of the serial interconnected channels and the equivalent frequency response of instruments, which are perfectly consistent with actual DDJ measure results. These methods can be used to measure and calibrate the instrument bandwidth effect precisely in jitter and BER test. At last, the paper gives the results of the instrument bandwidth effect for three channels and a set of instruments according to simulation, and presents a new concept “equivalent bandwidth” to roughly estimate the test error of DDJ caused by instrument bandwidth.

An Accurate and Cost-Effective Jitter Measurement Technique Using a Single Test Frequency

An accurate and cost-effective jitter measurement technique is proposed. The new technique uses only a single test with a high frequency input sine wave. Eliminating the need for a 2nd low frequency test, which is required in the conventional dual-frequency jitter test, provides significantly savings in both hardware and data acquisition time. The new technique is computationally efficient since it requires only one FFT together with some simple time domain computation. Furthermore, there are no nonlinear operations involved, hence avoiding errors inherently associated with such operations. Theoretical analysis, extensive simulation results and experimental results show that the proposed technique is cost-effective and achieves comparable test accuracy to that achieved by the conventional dual-frequency test. The new technique is reliable and robust to both harmonic and non-harmonic distortions. The algorithmic simplicity and the relaxed hardware requirement make the new technique potentially suited for built-in self test.

Fast Jitter Test Solutions of High-Speed IO Based on Timing and Frequency Domain

To quantify the transmission quality of HSIO with high-level confidence is the big challenge in front of SOC ATE test engineers. The mainstream approaches can be separated into 3 types: BIST loopback, golden device and fast eye-mask test. All these 3 approaches cannot meet the strict specifications of the leading-edge high-speed device which need random jitter and deterministic jitter separation. This paper introduces one fast jitter test solution which can get accurate RJ/DJ value from either timing domain or frequency domain. This solution has been implemented in production of real devices and the result shows its high accuracy.

An Equivalent Model of Pattern Generator in Jitter Testing

Pattern generator is used to provide the stimulus in jitter testing. An equivalent model is proposed in order to determine the impact of non-ideal pattern generator on data jitter. Our model consists of an ideal square wave generator and a shaping filter. The algorithm of extracting the impulse response of the shaping filter is introduced. Analytical expressions of probability distribution function (PDF) of data jitter and bit error rate (BER) are given based on impulse response of the system. This model is verified in a set of experiments. It is shown the non-ideal pattern generator greatly changes the PDF of data jitter and exacerbates link BER. The estimated jitter with the impact of non-ideal pattern generator accords well with measured one, and the equivalent model has high accuracy.

Jitter Test of Multiphase DTTL

Speed and precision are always two critical factors to tradeoff in SDH jitter measurement. According to existing jitter test of single-phase data transition tracking loop(DTTL), a multi-phase DTTL jitter testing circuit is presented in this paper based on Xilinx chips. Xilinx chips have a feature of delay programmable configuration. This method makes use of it,and divides the square wave signal with the input jitter in a jitter measurement part into N copies. The copies are respectively configurated suitable delay, and with the local reference signal for phase comparison, the sum of all comparison outputs as a jitter error. Under the same sampling period, because the sampling points that take part in phase comparison are increased, so the sampling frequency and measurement accuracy indirectly improves. Theoretical analysis and simulation results show that the measurement accuracy for multi-phase jitter error has corresponding times than for single phase jitter error. The method eases limitation of the Xilinx chip clock and increases SDH jitter measurement accuracy.

Qualifying Serial Interface Jitter Rapidly and Cost-effectively

High-Speed Serial Interface (HSSI) devices have witnessed an increased use in communications. As a measure of how often bit errors happen in a communication interface, Bit Error Rate (BER) performance is of paramount importance. The bit errors in HSSIs are in large part due to jitter. This paper investigates the topic of accelerating the jitter and BER testing. We first present an under-sampling based transmitter test scheme. The scheme can accurately extract the transmitter jitter and finish the whole transmitter test within 100 ms while the test usually takes seconds. Then we propose a jitter tolerance extrapolation algorithm that enables us to perform the receiver jitter tolerance characterization and production test more than 1,000 times faster. The transmitter and receiver testing schemes have been successfully used on Automatic Test Equipment (ATE) to qualify millions of HSSIs with data rates up to 6 Gigabits per second (Gbps). The paper also presents a low cost external loopback-based testing scheme, where a novel jitter injection technique is proposed using the state-of-the-art phase delay line. With the novel jitter injection scheme and an FPGA-based Bit Error Rate Tester (BERT), we can validate and test HSSIs with higher data rates, but without the need of high-speed ATE instruments. Using high-speed relays, we can also utilize ATE to provide a more versatile scheme for HSSI validation, characterization and testing.

IEEE 1057 Jitter Test of Waveform Recorders

<para xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> The jitter test of waveform recorders and analog-to-digital converters (ADCs) is traditionally carried out using one of the methods recommended in the IEEE standard for digitizing waveform recorders, i.e., IEEE Standard 1057. Here, we study the uncertainty of one of those methods, point out the bias inherent to the estimator recommended for measuring the ADC jitter, and suggest an alternate estimator. Expressions are also presented for the determination of the precision of a given estimate from the number of samples used, the standard deviation of the additive noise present in the test setup, the jitter standard deviation, and the stimulus signal parameters. In addition, an expression for the computation of the minimum number of samples required to guarantee a given bound on the estimation uncertainty is presented, which is useful in optimizing the duration of the test. </para>

Runtime and Jitter on a Laser-Triggered Spark-Gap Switch

The University of Missouri has completed a new facility, named Tiger, for pulsed-power experimentation. Tiger consists of a 2.8-MV 450-kJ Marx bank that charges up to four 7-nF intermediate storage capacitors (I-stores) in parallel. When charged, the storage capacitors are switched into a resistive load through an SF6-filled laser-triggered gas switch. This switch has been designed to study the factors affecting runtime and jitter of spark-gap switches. All experiments presented in this paper were performed with a single I-store. The test switch was operated from about 500 kV up to 1.25 MV, at switch pressures from 10 to 50 psig. A 30-mJ 266-nm Nd:YAG laser was focused between the switch electrodes to initiate breakdown in the switch. The University of Missouri has examined laser energy, percentage of self-break, and focal length to determine their relation to runtime and jitter. A short discussion of the Tiger facility is presented with experimental results of jitter and runtime tests. The end goal of this paper is to understand the factors contributing to increased jitter and runtime and, thereby, provide paths to improved switch performance.

On-Chip Random Jitter Testing Using Low Tap-Count Coarse Delay Lines

An on-chip RMS jitter testing technique for design-for-test (DfT) applications is presented in this paper. In addition to utilizing a less complicated low tap-count variable delay line to sample the jitter's cumulative density function (CDF), a sophisticated post-processing algorithm is developed to enhance process variation tolerance. Our simulation results show that using an eight-tap delay line, the probability of making correct pass/fail decisions is higher than 99% in the presence of up to 30% delay line value deviations.

Novel On-Chip Circuit for Jitter Testing in High-Speed PLLs

We propose a novel on-chip circuit to measure the jitter present at the output of phase-locked loops (PLLs) used for generating phase-synchronous, frequency-multiplied clocks. This measure is performed at every period of the PLL reference clock, and a digital output encoded by means of a thermometer code is obtained. Such a digital output is then analyzed in order to confirm on-chip whether or not the jitter is within specifications. Our proposed circuit is able to test PLLs providing an output frequency in the gigahertz range. Compared to alternate techniques, that proposed here requires lower costs in terms of area overhead (requiring an area <12% of the PLLs' area) and circuit complexity, while featuring higher or comparable accuracy and lower or comparable test time.