基于脉宽收缩和累积寄存器的片上时钟抖动测试电路

Abstract

An on-chip clock jitter testing circuit based on pulse-shrinkage TDC and accumulation register is introduced in this paper, which can be used to monitor the jitter of internal clock signal with sub-gate delay resolution. The whole testing circuit is consisted of pulse-shrinkage loop, accumulation register, XOR array, counter and control circuit. All the pulse-shrinkage units are connected in a loop to reduce the required number, so that the area can be saved and the effects of process variations can be reduced. Multi-cycle clock pulse measurement results are accumulated simultaneously and output in the form of serial code in monitor-mode, the clock jitter can be read directly from the serial code. The whole circuit is designed in a 65-nm CMOS process, simulation results show that the circuit can measure several GHz clock signal, with a resolution of 1 ps.