Jitter Test of Multiphase DTTL

Abstract

Speed and precision are always two critical factors to tradeoff in SDH jitter measurement. According to existing jitter test of single-phase data transition tracking loop(DTTL), a multi-phase DTTL jitter testing circuit is presented in this paper based on Xilinx chips. Xilinx chips have a feature of delay programmable configuration. This method makes use of it,and divides the square wave signal with the input jitter in a jitter measurement part into N copies. The copies are respectively configurated suitable delay, and with the local reference signal for phase comparison, the sum of all comparison outputs as a jitter error. Under the same sampling period, because the sampling points that take part in phase comparison are increased, so the sampling frequency and measurement accuracy indirectly improves. Theoretical analysis and simulation results show that the measurement accuracy for multi-phase jitter error has corresponding times than for single phase jitter error. The method eases limitation of the Xilinx chip clock and increases SDH jitter measurement accuracy.