Irreducible Trinomials Research Articles

On Indices of Septic Number Fields Defined by Trinomials x7 + ax + b

Let K be a septic number field generated by a root, α, of an irreducible trinomial, x7+ax+b∈Z[x]. In this paper, for every prime integer, p, we calculate νp(i(K)); the highest power of p dividing the index, i(K), of the number field, K. In particular, we calculate the index, i(K). In application, when the index of K is not trivial, then K is not monogenic.

A note on indices of quartic number fields defined by trinomials x 4+ax+b

The main goal of this paper is to calculate the index of any number field K generated by a root of an irreducible trinomial x 4 + a x + b ∈ Z [ x ] . Our approach is based on Engstrom’s results and the factorization of 2 Z K and 3 Z K . In particular, we reformulate the Davis and Spearman’s results. Namely, for every prime integer p, we evaluate ν p ( i ( K ) ) . The existence of a common index divisor of K guaranties the non monogenity of K.

History and development of algebraic number theory

We briefly describe the origin and development of classical Algebraic Number Theory. We state some latest results regarding discriminants and integral bases of pure number fields as well as sextic number fields defined by irreducible trinomials with integer coefficients. A few open problems regarding class number of algebraic number fields are also mentioned.

On index divisors and monogenity of certain septic number fields defined by x 7 + ax 3 + b

In this paper, for any septic number field K generated by a root α of a monic irreducible trinomial , we describe all prime power divisors of the index of K answering Problem 22 of Narkiewicz [26]. In particular, if , then K is not mongenic. We illustrate our results by some computational examples.

Cyclic cubic extensions of ℚ

We determine the irreducible trinomials [Formula: see text] for integers [Formula: see text] which generate precisely all possible Galois extensions of degree [Formula: see text] over [Formula: see text]. The proof, although involved, is elementary and one can parametrize all these polynomials explicitly. As an accidental by-product of the results, we prove that infinitely many primes congruent to [Formula: see text] or [Formula: see text] mod [Formula: see text] are sums of two rational cubes - thereby, giving the first unconditional result on a classical open problem.

An area-efficient architecture for finite field inversion over GF(2m) using polynomial basis

Elliptic curve cryptography (ECC) is a powerful approach to cryptography, and its implementation in cryptography necessitates a smaller chip size, lower power consumption, and faster processing. Finite-field inversion is one of the most computational operations involved in Elliptic curve cryptography(ECC). Extended-Euclidean algorithm and Itoh–Tsujii’s algorithm (ITA) are the two commonly used algorithms for implementing the FF-inversion operation. In this paper, we present the Finite-field inversion architecture developed for the modified Itoh–Tsujii’s algorithm. The reduction in computational delay for the FF-inversion is achieved by using 4k exponentiation in the realization of modified ITA. The hardware complexity of 4k exponentiation module depends on k value and k value depends on the order of the field. In this work the best value of k for a specific irreducible trinomial is computed analytically to achieve reduction in area×time product of the proposed FF-inversion architecture. The area and time complexities of the proposed architecture over National Institute of Standard and Technology(NIST) irreducible trinomials GF(2193), GF(2233), and GF(2409) targeting virtex-4 FPGA are computed and compared with similar works in the literature.

The Chebotarev density theorem for function fields — Incomplete intervals

We prove a Pólya-Vinogradov type variation of the Chebotarev density theorem for function fields over finite fields valid for “incomplete intervals” I⊂Fp, provided (p1/2log⁡p)/|I|=o(1). Applications include density results for irreducible trinomials in Fp[x], i.e. the number of irreducible polynomials in the set {f(x)=xd+a1x+a0∈Fp[x]}a0∈I0,a1∈I1 is ∼|I0|⋅|I1|/d provided |I0|>p1/2+ϵ, |I1|>pϵ, or |I1|>p1/2+ϵ, |I0|>pϵ, and similarly when xd is replaced by any monic degree d polynomial in Fp[x]. Under the above assumptions we can also determine the distribution of factorization types, and find it to be consistent with the distribution of cycle types of permutations in the symmetric group Sd.

Low-Delay FPGA-Based Implementation of Finite Field Multipliers

Arithmetic operations over binary extension fields GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) have many important applications in domains such as cryptography, code theory and digital signal processing. These applications must be fast, so low-delay implementations of arithmetic circuits are required. Among GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) arithmetic operations, field multiplication is considered the most important one. For hardware implementation of multiplication over binary finite fields, irreducible trinomials and pentanomials are normally used. In this brief, low-delay FPGA-based implementations of bit-parallel GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) polynomial basis multipliers are presented, where a new multiplier based on irreducible trinomials is given. Several post-place and route implementation results in Xilinx Artix-7 FPGA for different GF(2 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> ) finite fields are reported. Experimental results show that the proposed multiplier exhibits the best delay, with a delay improvement of up to 4.7%, and the second best Area×Time complexities when compared with similar multipliers found in the literature.

Construction of isodual codes from polycirculant matrices

Double polycirculant codes are introduced here as a generalization of double circulant codes. When the matrix of the polyshift is a companion matrix of a trinomial, we show that such a code is isodual, hence formally self-dual. Numerical examples show that the codes constructed have optimal or quasi-optimal parameters amongst formally self-dual codes. Self-duality, the trivial case of isoduality, can only occur over $$ {\mathbb {F}}_2$$ in the double circulant case. Building on an explicit infinite sequence of irreducible trinomials over $${\mathbb {F}}_2,$$ we show that binary double polycirculant codes are asymptotically good.

A three-term Karatsuba multiplier for a special class of trinomials

In this paper, we continue the study of bit-parallel multiplier using three-term Karatsuba algorithm (KA), recently introduced by Li et al. (VLSI Design 2018). The three-term KA is the simplest variation of the classic Karatsuba algorithm, which multiplies two 3-term polynomials using six scalar multiplications. Based on this observation, Li et al. developed an efficient bit-parallel multiplier scheme for a new special class of irreducible trinomial, namely, xm + xk + 1, m = 3k. The scheme can save about 1/3 logic gates compared with the fastest multiplier so far. However, such a special type of trinomials is quite rare. We consider two more general type of trinomials, where m = 3k + 1 or m = 3k + 2. The corresponding Mastrovito matrices are constructed for different computing parts. It is demonstrated that the space complexity of our proposal matches Li et al. scheme, while its time complexity increases a little. In the end, some comments are derived.

Implementation of High Speed Low Power Systolic Multiplier Based on Irreducible Trinomials

This paper presents a high speed low power systolic multiplier based on irreducible trinomials which is implemented using GF (2M). To calculate a set of d partial products in each Handling Element (HE) during every cycle we suggest multiplication algorithm of digit level. By using the systolic channels independently, operands in the proposed structure will be reduced and accumulated by partial products. Functional verification (Simulation) of the multiplier is done by using Xilinx ISE and synthesis is done by using Xilinx XST. The synthesized design is implemented on Zynq7000 FPGA. After completion of the synthesis, it is found that the proposed multiplier achieved power consumption of 2.9mW. Area and the performance of the multiplier is optimized in the proposed structures.

LFSR-based Bit-Serial $GF(2^m)$ Multipliers using Irreducible Trinomials

In this article, a new architecture of bit-serial polynomial basis (PB) multipliers over the binary extension field $GF(2^m)$ G F ( 2 m ) generated by irreducible trinomials is presented. Bit-serial $GF(2^m)$ G F ( 2 m ) PB multiplication offers a performance/area trade-off that is very useful in resource constrained applications. The architecture here proposed is based on LFSR ( Linear-Feedback Shift Register ) and can perform a multiplication in $m$ m clock cycles with a constant propagation delay of $T_{A} + T_{X}$ T A + T X . These values match the best time results found in the literature for bit-serial PB multipliers with a slight reduction of the space complexity. Furthermore, the proposed architecture can perform the multiplication of two operands for $t$ t different finite fields $GF(2^m)$ G F ( 2 m ) generated by $t$ t irreducible trinomials simultaneously in $m$ m clock cycles with the inclusion of $t(m-1)$ t ( m - 1 ) flipflops and $tm$ t m XOR gates.

Efficient Bit-Parallel Multiplier for All Trinomials Based on n-Term Karatsuba Algorithm

Recently, hybrid multiplication schemes over the binary extension field GF(2m) based on nterm Karatsuba algorithm (KA) have been proposed for irreducible trinomials. Their complexities depend on a decomposition of m and the choice of a generation polynomial. However, these multipliers have some limitations on a decomposition of m or generation polynomial x <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> + x <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> + 1 such that m ≥ 2k. In this paper, we loosen such limited conditions. We present a new hybrid bit-parallel multiplier based on n-term KA for any irreducible trinomial x <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">m</sup> + x <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> + 1 (0 k m), where m is decomposed as m = nm <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> + r with 0 r m0 and 1 n. (Here, various values for n, m <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> and r may be chosen.) To this end, we generalize the previously proposed multiplication scheme for x <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nm0+1</sup> +x <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> +1 into x <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">nm0+r</sup> +x <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">k</sup> +1. We evaluate the explicit complexity of the proposed multiplier. Specific comparisons show that the proposed multiplier achieves the lowest space complexity with the same or lower time complexity among hybrid multipliers. Compared to the fastest multipliers, the time complexity of the proposed multiplier costs only TX higher while its space complexity is much lower (it has roughly 40% reduced space complexity), where TX is the delay of one 2-input XOR gate.

Space Efficient $GF(2^m)$ Multiplier for Special Pentanomials Based on $n$ -Term Karatsuba Algorithm

Recently, new multiplication schemes over the binary extension field $GF(2^{m})$ based on an $n$ -term Karatsuba algorithm have been proposed for irreducible trinomials. In this paper, we extend these schemes for trinomials to any irreducible polynomials. We introduce some new types of pentanomials and propose multipliers for those pentanomials utilizing the extended schemes. We evaluate the rigorous space and time complexities of the proposed multipliers, and compare those with similar bit-parallel multipliers for pentanomials. As a main contribution, the best space complexities of our multipliers are $\frac {1}2m^{2}+O\left({m^{\frac {3}2}}\right)$ AND gates and $\frac {1}2m^{2}+O\left({m^{\frac {3}2}}\right)$ XOR gates, which nearly correspond to the best results for trinomials. Also, specific comparisons for three fields $GF(2^{163})$ , $GF(2^{283})$ , and $GF(2^{571})$ recommended by NIST show that the proposed multiplier has roughly 40% reduced space complexity compared to the fastest multipliers, while it costs a few more XOR gate delay. It is noticed that our space complexity gain is much greater than the time complexity loss. Moreover, the proposed multiplier has about 21% reduced space complexity than the best-known space efficient multipliers, while having the same time complexity. The results show that the proposed multipliers are the best space optimized multipliers.

Low Space Complexity &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$GF(2^m)$ &lt;/tex-math&gt; &lt;/inline-formula&gt; Multiplier for Trinomials Using &lt;inline-formula&gt; &lt;tex-math notation="LaTeX"&gt;$n$ &lt;/tex-math&gt; &lt;/inline-formula&gt;-Term Karatsuba Algorithm

We propose bit-parallel GF(2 m ) multipliers for irreducible trinomials using an n-term Karatsuba algorithm and Mastrovito approach, which are generalizations of the newly proposed multiplication scheme for a specific trinomial. The complexities of the proposed multipliers for GF(2 m ) depend on the choice of an irreducible trinomial x m + x k + 1 defining GF(2 m ) and values n, m 0 such that m = nm 0 or m = nm 0 + 1. It is possible to achieve a space-time tradeoff by choosing proper values for k, n, and m 0 . For the purpose of a specific comparison, we compare the proposed multipliers with the best-known multipliers for an odd m ∈ [399, 450] for which there exists an irreducible trinomial of degree m. As a result, the proposed multipliers achieve the lowest space complexities among similar bit-parallel multipliers (they have roughly 40% reduced space complexities compared with the fastest multiplier). On the other hand, their time complexities match or are at most 2T X higher than the fastest multipliers, where T X is the delay of one 2-input XOR gate.

Prime ideal factorization and p-integral basis of quintic number fields defined by x^5+ax+b

Based on Newton polygon techniques, for every prime integer p, a p-integral basis of ℤK, and the factorization of the principal ideal pℤK into prime ideals of ℤK are given, where K is a quintic number field defined by an irreducible trinomial X5 + aX + b ∈ ℤ[X].

Koblitz Curves over Quadratic Fields

In this work, we retake an old idea that Koblitz presented in his landmark paper (Koblitz, in: Proceedings of CRYPTO 1991. LNCS, vol 576, Springer, Berlin, pp 279–287, 1991), where he suggested the possibility of defining anomalous elliptic curves over the base field $${\mathbb {F}}_4$$ . We present a careful implementation of the base and quadratic field arithmetic required for computing the scalar multiplication operation in such curves. We also introduce two ordinary Koblitz-like elliptic curves defined over $${\mathbb {F}}_4$$ that are equipped with efficient endomorphisms. To the best of our knowledge, these endomorphisms have not been reported before. In order to achieve a fast reduction procedure, we adopted a redundant trinomial strategy that embeds elements of the field $${\mathbb {F}}_{4^{m}},$$ with m a prime number, into a ring of higher order defined by an almost irreducible trinomial. We also suggest a number of techniques that allow us to take full advantage of the native vector instructions of high-end microprocessors. Our software library achieves the fastest timings reported for the computation of the timing-protected scalar multiplication on Koblitz curves, and competitive timings with respect to the speed records established recently in the computation of the scalar multiplication over binary and prime fields.

On a hypothese concerning irreducible trinomials over GF(2)

W pracy zostaly znalezione wszystkie najmlodsze leksykograficznie wielomiany nierozkladalne nad cialem binarnym GF(2) o stopniach od 10000 do 20000. Kazdy ze znalezionych wielomianow posiada szczegolną strukture: moze byc przedstawiony w postaci X^n + g(X), gdzie g(X) jest wielomianem bardzo niskiego stopnia w stosunku do n, zaleznym od n. Hipoteza, o ktorej mowa w tytule dotyczy oszacowania maksymalnej szybkości wzrostu stopnia wielomianu g(X) w zalezności od n. Przy okazji odnosimy sie do innych przypuszczen mowiących o zalezności stopnia wielomianu g(X) od n. Badania przeprowadzono z wykorzystaniem techniki obliczen rozproszonych w niewielkiej sieci komputerowej skladającej sie z komputerow IBM PC.

Bit‐parallel systolic multiplier over for irreducible trinomials with ASIC and FPGA implementations

Cryptography in digital world must offer integrity and confidentiality using cryptographic algorithms which mainly involve multiplication operation in finite fields. Various algorithms and architectures are proposed in the literature to obtain efficient finite field multiplications in both hardware and software. Here, a modified interleaved multiplication algorithm with reduced computational complexity is proposed based on a novel pre-computation (PC) technique to perform multiplication over for trinomials. Consequently, an m-bit systolic multiplier for trinomials (SMT) is designed by employing the proposed algorithm. Hardware and delay complexity analysis is performed and comparison of the proposed SMT structure with similar multipliers available in the literature is presented. The SMT structure achieves ∼28 and 17% improvement in hardware and area-delay product, respectively, for m = 233 when compared with the best multiplier available in the literature. The functionality of the proposed SMT structure is also verified by implementing on field-programmable gate array (FPGA) and application-specific integrated circuit (ASIC) technologies. It can be observed from FPGA and ASIC implementation results that the proposed SMT structure shows improvement in area, power consumption, area-delay, and power-delay products when compared with similar multipliers available in the literature.

Efficient Nonrecursive Bit-Parallel Karatsuba Multiplier for a Special Class of Trinomials

Recently, we present a novel Mastrovito form of nonrecursive Karatsuba multiplier for all trinomials. Specifically, we found that related Mastrovito matrix is very simple for equally spaced trinomial (EST) combined with classic Karatsuba algorithm (KA), which leads to a highly efficient Karatsuba multiplier. In this paper, we consider a new special class of irreducible trinomial, namely, xm+xm/3+1. Based on a three-term KA and shifted polynomial basis (SPB), a novel bit-parallel multiplier is derived with better space and time complexity. As a main contribution, the proposed multiplier costs about 2/3 circuit gates of the fastest multipliers, while its time delay matches our former result. To the best of our knowledge, this is the first time that the space complexity bound is reached without increasing the gate delay.