Ion-cut Process Research Articles

Current transport mechanism of lateral Schottky barrier diodes on β-Ga2O3/SiC structure with atomic level interface

Heterogeneous integration of β-Ga2O3 on highly thermal conductive SiC substrate by the ion-cutting technique is an effective solution to break the heat-dissipation bottleneck of β-Ga2O3 power electronics. In order to acquire high-quality β-Ga2O3 materials on SiC substrates, it is essential to understand the influence of the ion-cutting process on the current transport in β-Ga2O3 devices and to further optimize the electrical characteristics of the exfoliated β-Ga2O3 materials. In this work, the high quality of β-Ga2O3/SiC structure was constructed by the ion-cutting process, in which an amorphous layer of only 1.2 nm was formed between β-Ga2O3 and SiC. The current transport characteristics of Au/Pt/Ni/β-Ga2O3 Schottky barrier diodes (SBDs) on SiC were systematically investigated. β-Ga2O3 SBDs with a high rectification ratio of 108 were realized on a heterogeneous β-Ga2O3 on-SiC (GaOSiC) substrate. The net carrier concentration of the β-Ga2O3 thin film for GaOSiC substrate was down to about 8% leading to a significantly higher resistivity, compared to the β-Ga2O3 donor wafer, which is attributed to the increase in acceptor-type implantation defects during the ion-cutting process. Furthermore, temperature-dependent current–voltage characteristics suggested that the reverse leakage current was limited by the thermionic emission at a low electric field, while at a high electric field, it was dominated by the Poole–Frenkel emission from E3 deep donors caused by the implantation-induced GaO antisite defects. These results would advance the development of β-Ga2O3 power devices on high thermal conductivity substrate fabricated by ion-cutting technique.

Fabrication technology of void embedded silicon-on-insulator substrate

Void embedded silicon-on-insulator (VESOI) substrate is a newly developed silicon-on-insulator (SOI) substrate for advanced complementary metal oxide semiconductor (CMOS) devices and integration technology. However, in the ion-cutting process for preparing the substrate, numerous hydrogen bubbles aggregate at the cut interface, which compresses the cavity structure and might cause the thin film above the cavity to be damaged and delaminated. Therefore, it is necessary to conduct in-depth research on the stress mechanism and process stability in the preparation of VESOI substrates. This study focuses on a single rectangular cavity structure and uses the fixed-supported beam theory to analyze its mechanical behavior during fabrication, and a three-dimensional model of cavity structure is constructed by using the finite element analysis tool. Through stress simulation, the failure mechanism of the cavity structure is identified, and the weak points are confirmed. The results show that the short side length (<i>w</i>), top silicon film thickness (<i>t</i>), and hydrogen bubble pressure are the main factors affecting the stress state of the top silicon film. When the <i>w</i>/<i>t</i> ratio exceeds 4–5, the silicon film will fracture owing to excessive tensile stress, and the fracture site is along the long side of the rectangular cavity. By increasing the thickness of the top silicon film slightly and adding support structures inside the cavity (to reduce <i>w</i>), this work successfully prepares high-quality 8-inch VESOI substrates that meet the requirements for the CMOS production line. The present study is expected to provide valuable idea for the development of integrated technologies relying on VESOI substrates.

Heterogeneous integration of lithium tantalate thin film on quartz for high performance surface acoustic wave resonator

Surface acoustic wave (SAW) resonator based on the piezo film on a foreign substrate is promising to enhance the performance of radio frequency filters. In this work, the 4 inch wafer-scale lithium tantalate thin film on quartz (LTOQ) heterogenous substrate was fabricated by ion-cut process. The cut angle of quartz was optimized to achieve high-quality factor (Q) based on finite element analysis. The average film thickness and the film nonuniformity for the whole wafer are 602 nm and ±2.2%, respectively. The lithium tantalate film exhibits single-crystalline quality where the full width at half-maximum of high-resolution X-ray diffraction rocking curve is 47.4 arcsec. The shear horizonal surface acoustic wave resonator based on the LTOQ structure exhibits a maximum Bode-Q exceeding 3000 and the electromechanical coupling coefficient of 10.26%. The temperature coefficient of frequency at resonant frequency and anti-resonant frequency are −25.21 ppm °C−1 and −35.22 ppm °C−1, respectively.

Wafer-Scale Fabrication of Silicon Film on Lithium Niobate on Insulator (LNOI)

Hybrid integration of silicon photonics with lithium niobate (LN) devices provides a promising route to enable an excellent modulation performance in silicon photonic integrated circuits. To realize this purpose, a substrate containing a Si film on an LNOI substrate, called Si on the LNOI structure, was analyzed and fabricated. The mode propagation properties in the Si-on-LNOI structure were simulated in detail and a vertical adiabatic coupler (VAC) between the Si waveguide and LN waveguide was simulated to help in the determination of the dimension of this structure. A 4-inch wafer-scale Si on an LNOI hybrid structure was fabricated through the ion-cut process. This structure has a single-crystalline quality, high thickness uniformity, smooth surface, and sharp bonding interface, which are practical for realizing low loss and high coupling efficiency.

Wafer-scale single-crystalline β-Ga2O3 thin film on SiC substrate by ion-cutting technique with hydrophilic wafer bonding at elevated temperatures

Heterogeneous integration of β-Ga2O3 on a highly thermal conductive SiC substrate is an efficient solution to solve its bottleneck of thermal dissipation for high-power electronics. In this work, a 2-inch high-quality \(\left( {\bar 201} \right)\) β-Ga2O3 single-crystalline film was transferred to the 4H-SiC substrate via the ion-cutting technique with hydrophilic bonding at elevated temperatures. The evolution process of the surface blistering on the hydrogen-implanted β-Ga2O3 together with the internal pressure in blisters were investigated systematically to understand the physical mechanisms of the ion-cutting of β-Ga2O3 thin film. As suggested by the finite element simulation, the hydrophilic bonding was carried out at an elevated bonding temperature of 96°C to prevent the debonding of β-Ga2O3/4H-SiC during the ion-cutting process via reducing the thermal stress. The as-transferred β-Ga2O3 thin film exhibited a narrow full width at half maximum of the X-ray diffraction of 79.2 arcsec, and an extremely smooth surface with a root-mean-square roughness of 0.1 nm was achieved after chemical mechanical polishing. It is expected that the β-Ga2O3/4H-SiC heterogeneous integration material obtained by the ion-cutting technique with hydrophilic bonding at elevated temperatures will serve as a practical platform for high-performance β-Ga2O3 power devices.

A New Class of High-Overtone Bulk Acoustic Resonators Using Lithium Niobate on Conductive Silicon Carbide

This letter presents a new class of High-overtone Bulk Acoustic Resonators (HBARs) with only top electrodes but excellent performance using lithium niobate (LN) thin films on conductive silicon carbide (SiC). The 4-inch single-crystalline lithium niobate thin film on conductive SiC (LNCSiC) substrate was prepared by ion-cutting process. Since the conductive SiC serves as both the resonant cavity and the floating electrode, the HBARs based on LNCSiC with only top electrodes were designed and fabricated. The devices show a wide frequency response span exceeding 2.0 GHz, a frequency spacing of 10 MHz, an excellent f $\cdot $ Q $_{\textit {LAKIN}}$ product of ${9.6}\times {10} ^{{13}}$ Hz ( f $\cdot $ Bode-Q of ${1.1}\times {10} ^{{14}}$ Hz), and a low temperature coefficient of frequency (TCF) of −18.9 ppm/°C. The frequency response shift of the proposed HBAR can be achieved by just adjusting the in-plane orientation of the top electrodes. Additionally, a multi-band filter was numerically synthesized based on the proposed HBARs, showing a spectral spacing of 10 MHz and a passband span of more than 2.0 GHz. Upon further optimizations, the proposed HBARs with a wide frequency response, a high- f $\cdot $ Q , and a low-TCF will be very promising for radio-frequency applications.

Channel Properties of Ga₂O₃-on-SiC MOSFETs

We report the characterization of the channel mobility properties of metal-oxide-semiconductor field-effect transistors (MOSFETs) on the heterogeneous $\beta $ -Ga2O3-on-SiC (GaOSiC) substrate fabricated by an ion-cutting process. The mobility of GaOSiC MOSFETs is significantly improved as the postannealing temperature of Ga2O3 channel increases from 900 °C to 1200 °C. The GaOSiC transistor annealed at 1200 °C exhibits mobility consistent with the $\beta $ -Ga2O3 donor wafer, which suggests that the defects in Ga2O3 channel induced by the H+ implantation for the ion-cutting step can be eliminated by the high-temperature annealing. As the ambient temperature ( ${T} _{{\mathrm {amb}}}$ ) increases from 0 °C to 150 °C, the mobility within the accumulation regime of GaOSiC MOSFETs decreases with the temperature following a ${T}_{{\mathrm {amb}}}^{-1}$ law, which is limited by the phonon scattering. The results of this work will be critically important for designing the transport properties of the GaOSiC channel, significantly advancing the development of Ga2O3 power devices on high thermal conductivity substrate.

Solar-Blind Photodetector Based on Single Crystal Ga2O3 Film Prepared by a Unique Ion-Cutting Process

A solar-blind photodetector based on single crystal β-Ga2O3 thin film transferred on a SiC substrate with an Al2O3 buffer layer was prepared by a unique ion-cutting process. The structure and micro...

β-Ga2O3 MOSFETs on the Si substrate fabricated by the ion-cutting process

β-Ga2O3 MOSFETs are demonstrated on heterogeneous Ga2O3-Al2O3-Si (GaOISi) substrate fabricated by ion-cutting process. Enhancement (E)- and depletion (D)-mode β-Ga2O3 transistors are realized on by varying the channel thickness ( T ch). E-mode GaOISi transistor with a T ch of 15 nm achieves a high threshold voltage V TH of ~ 8 V. With the same T increase, GaOISi transistors demonstrate more stable ON-current I ON and OFF-current I OFF performance compared to the reported devices on bulk Ga2O3 wafer. Transistors on GaOISi achieve the breakdown voltage of 522 and 391 V at 25°C and 200°C, respectively.

Large area stress free Si layer transfer onto Corning glass substrate using ion-cut

We report on the large area stress free single crystal silicon (Si) layer transfer onto glass substrate using hydrogen ion (H+) implantation and heterogeneous direct wafer bonding (DWB) (ion-cut process). Si wafers were implanted with H+ ions at room temperature followed by the DWB between the Si wafer and glass substrate. Post-implantation annealing studies were performed at different temperatures. The root mean square surface roughness of the H-implanted Si wafer and glass substrate was measured to be 0.3 nm and 0.5 nm, respectively. At an annealing temperature of 330 °C, a thin layer of the Si wafer was transferred onto the glass substrate. The average thickness of the transferred layer was found to be ∼605 nm with surface roughness of 4 nm. Raman spectroscopy confirmed that the transferred Si layer was stress free and retained its crystallinity. Large area transfer of high quality stress free Si-on-glass substrate is demonstrated using heterogeneous DWB and ion-cut process.

Rapid Fabrication of 100 nm or Thinner Fully Depleted Silicon-on-Insulator Materials for Ultralow Energy Consumption

The fully depleted silicon-on-insulator (FD-SOI) wafer is the core material of the FD-SOI technology used for manufacturing the applications with ultralow energy consumption for internet of things, artificial intelligence, automotive, and wearable devices. Ion-cut process is the main technology to fabricate FD-SOI wafers. After ion cutting, the silicon layer transferred on the insulator includes a spongelike damaged layer. Therefore, it must contain a thinning buffer layer with a thickness more than 150 nm to remove the damaged layer by a polishing step. The requirement of the additional buffer layer makes the direct fabrication of a less than 100 nm thick SOI layer from the as-split status impossible. Here, we develop a process based on solid-phase epitaxial growth (SPEG) technique, abandoning the polishing step, and thus achieve a one-step fabrication of FD-SOI substrate. First, inducing amorphization of an SOI layer via blistering supersaturated hydrogen ions through microwaving fully consumes the poss...

Investigation of low-fluence hydrogen implantation-induced cracking in B doped Si0.70Ge0.30

The splitting kinetics of B doped Si0.70Ge0.30 layers with low-fluence hydrogen implantation (3 × 1016/cm2) was investigated. For H-implanted Si/Si0.70Ge0.30/Si structures without B doping, no cracking was observed in the Si0.70Ge0.30 layer. Upon increasing the B concentration in the buried Si0.70Ge0.30 layer to 3 × 1019/cm3, a continuous cracking was observed parallel to the surface. A series of analyses indicate that B doping can greatly promote the evolution of hydrogen related defects, which in turn enhances H diffusion to form cracks. Since the hydrogen fluence (3 × 1016/cm2) is only half of the typical fluence required for a conventional ion-cut process, our research may bring an alternative path for SiGe on insulator (SGOI) fabrication technique in manufacturing and enable the subsequent application in postsilicon era.

Defect formation in MeV H+ implanted GaN and 4H-SiC investigated by cross-sectional Raman spectroscopy

Cross-sectional Raman spectroscopy is used to characterize the defect formation and the defect recovery in MeV H+ implanted bulk GaN and 4H-SiC in the high energy MeV ion-cut process. The Raman intensity decreases but the forbidden modes are activated at the damage region, and the intensity decrease is proportional to the damage level. The Raman spectrum is quite sensitive to detect the damage recovery after annealing. The main peak intensity increases and the forbidden mode disappears in both annealed GaN and 4H-SiC samples. The Raman spectra of GaN samples annealed at different temperatures suggest that higher annealing temperature is more efficient for damage recovery. While, the Raman spectra of SiC indicate that higher implantation temperature results in heavier lattice damage and other polytype clusters might be generated by high annealing temperature in the annealed SiC samples. The cross-sectional Raman spectroscopy is a straightforward method to characterize lattice damage and damage recovery in high energy ion-cut process. It can serve as a fast supplementary measurement technique to Rutherford backscattering spectrometry (RBS), nuclear reaction analysis (NRA) and transmission electron microscope (TEM) for the defect characterizations.

High quality extremely thin SOI fabricated by facilitated ion-cut with H-trapping effect

High-quality strain-relaxed extremely thin silicon-on-insulator (ETSOI) has been fabricated by using H-trapping and etch-stop process in the H-implanted Si/Si0.70Ge0.30/Si/B-doped Si0.70Ge0.30/Si heterostructure. Compared to conventional ion-cut process, the combination of ultrathin SiGe interlayer with boron doping can significantly decrease the critical hydrogen implantation dosage needed for layer transfer by improving H-trapping efficiency. During subsequent annealing process, implanted H preferentially agglomerates at the trapping centers and induces long microcracks at the B-doped Si0.70Ge0.30/Si interface as well as in the near-interface region. The selective etch-stop process was used to remove residual Si/SiGe layers to expose a strain-relaxed Si device layer with a smooth surface morphology. These results demonstrate facilitated ion-cut as a promising approach for fabricating high crystalline quality ETSOI substrate and further offer a potential solution for scaling planar complementary metal–oxide–semiconductor to 22 nm node and beyond.

Invited: Heterointegration of Semiconductors: Challenges and Opportunities

Nowadays, semiconductor industry faces major challenges as the current materials and designs can hardly respond to the relentless course towards device miniaturization, higher performances, energy efficiency, cost-effectiveness, and multifunctionality, which have been the driving forces for the development of semiconductor technologies. New materials and integration processes are urgently needed to overcome these multi-faceted challenges. The heterointegration of dissimilar materials on the same platform has recently emerged as a powerful strategy to address some of these challenges. Particularly, tremendous efforts have been put to develop fabrication processes that allow the integration of III-V compound semiconductors on foreign substrates. For instance, III-V heterointegration on silicon substrates will enable the combination, within a single platform, III-V high-performance technologies with low cost and wafer size advantages besides its compatibility with standard semiconductor processing. In addition to electronic and optoelectronic applications, the realization of these hybrid substrates is also highly relevant for high-efficiency, low-cost photovoltaic cells, spintronics, bio-integrated technologies, to name a few. It is, however, noteworthy that this heterointegration needs to be achieved on the wafer level in order to be technologically and economically viable. In this presentation, we provide a description of important approaches to achieve this heterogeneous integration, with an emphasis on wafer bonding processes and thin layer splitting using the ion-cut process. A variety of bulk-quality heterostructures, frequently unattainable by direct epitaxial growth, can be produced provided that a list of technical criteria is fulfilled, thus offering an additional degree of freedom in the design and fabrication of heterogeneous, multifunctional, and flexible devices. Ion cutting is a generic process that can be employed to split and transfer fine monocrystalline layers from various crystals. Materials and engineering issues as well as our current understanding of the underlying physics involved in its application to cleaving thin layers from freestanding GaN, InP, and GaAs wafers will be presented and discussed.

Sharp crack formation in low fluence hydrogen implanted Si0.75Ge0.25/B doped Si0.70Ge0.30/Si heterostructure

An approach to transfer a high-quality SiGe layer for the fabrication of SiGe-on-insulator wafers has been proposed based on the investigation of crack formation in H-implanted Si0.75Ge0.25/B-doped Si0.70Ge0.30/Si structures. The crack formation is found to be closely correlated to the concentration of B atoms doped in the buried Si0.70Ge0.30 layer. For H-implanted Si0.75Ge0.25/Si0.70Ge0.30/Si structures without B doping, no platelets or cracking is observed in the Si0.70Ge0.30 layer. Upon increasing the concentration of B doping in the buried Si0.70Ge0.30 layer to 2 × 1019/cm3, cracking occurs at the interfaces on both sides of Si0.70Ge0.30 interlayer, thus, resulting in the formation of continuous sharp crack confined in the ultrathin Si0.70Ge0.30 interlayer. With B doped ultrathin Si0.70Ge0.30 interlayer, the Si0.75Ge0.25 layer can be transferred to fabricate SiGe-on-insulator by H implantation with a fluence as low as 3 × 1016/cm2, which is only half of the typical fluence required for a conventional ion-cut process. Since cracking is confined in the ultrathin Si0.70Ge0.30 interlayer, the as-cut SiGe-on-insulator possesses a rather smooth surface with a roughness of 1.55 nm.

Multi-Scale Thickness and Roughness Characterization of Thin Silicon-On-Insulator Films

Thickness uniformity of the silicon top layer is extremely important for the next generation of CMOS electronics based on Fully-Depleted Silicon-On-Insulator (FD-SOI) wafers. It requires accurate thickness characterization over a wide spatial bandwidth, from transistor to wafer scales [10 nm-300 mm]. We propose a data processing method using one-dimensional Power Spectral Density functions to describe both roughness and thickness variations of thin layers over the bandwidth of interest. The study of the correlation between thickness and roughness of the silicon top layer of SOI wafers leads to the distinction of three spectral domains: high-frequencies, where thickness variations are larger than roughness variations, mid-frequencies, where thickness and roughness variations are comparable, and low-frequencies, where the top layer conformably follows the buried oxide roughness. Furthermore, the spectral analysis of thickness variations, points out fractal behaviors over three regions (scaling exponent 0.3, 1.2 and 0.2 respectively). These regions provide the spectral foot-prints of fracture propagation [1.10−5−2.10−3 μm−1], surface self-diffusion [0.3−1 μm−1] and sacrificial oxidation [1−10 μm−1] respectively, all phenomena involved in fabrication of SOI wafers by the ion-cut process. Additionally, over the mid-frequencies region [0.03−1 μm−1], we observe a “bump” which results from the depth and size-distribution of micro-cracks generated during the ion-implantation step.

Investigation of Germanium Implanted with Hydrogen for Layer Transfer Applications

The technology for thin Ge layer transfer by hydrogen ion-cut process is characterised in this work. Experiments were carried out to determine suitable hydrogen ion implantation doses in germanium for the low temperature ion cut process by examining the formation of blisters on implanted samples. Raman and Spreading Resistance Profiling (SRP) have been used to analyse defects in germanium caused by hydrogen implants. Bevelling has been used to facilitate probing beyond the laser penetration depth. Results of Raman mapping along the projection area reveal that after post implant annealing at 400 °C, some crystal damage remains, while at 600 °C, the crystal damage has been repaired. SRP shows that some amount of hydrogen acceptor states (~1Î1016 acceptors/cm2) remain after 600 °C. These are thought to be vacancy-related point defect clusters.

High electron mobility transistors on plastic flexible substrates

The double-flip transfer of indium phosphide (InP) based transistors onto plastic flexible substrates was demonstrated. Modulation doped field effect transistor layers, epitaxially grown on InP bulk substrates, were transferred onto sapphire using a masked ion-cutting process. Following layer transfer, transistors were fabricated at low temperatures (≤150 °C). The device structure was then bonded to flexible substrate, and laser ablation was used to separate the initial bond. The transferred transistors were characterized and exhibited high field-effect mobility (μaverage∼2800 cm2 V−1 s−1).

Heterointegration of Compound Semiconductors by Ultrathin Layer Splitting

Compound semiconductors are very attractive for a wide spectrum of applications in electronics, optoelectronics, photonics, and photovoltaics. From materials standpoint, the exploitation of the full potential of these technologies requires processes that can satisfy the two major conditions: (1) Integrability with the traditional technology of Si; and (2) Cost-effective. In this perspective, this paper presents the ion-cut process by which fine monocrystalline layers can be transferred onto foreign substrates. Bulk quality heterostructures frequently unattainable by direct epitaxial growth can be produced, which offers an additional degree of freedom in design and fabrication of hybrid devices. Ion-cut process can also be exploited to reduce the material cost by splitting several ultrathin layers from the same wafer. Materials and engineering issues as well as our current understanding of the underlying physics involved in the application of ion-cut process to cleave thin layers from III-V and III-nitride semiconductors are briefly discussed.