Abstract
Nowadays, semiconductor industry faces major challenges as the current materials and designs can hardly respond to the relentless course towards device miniaturization, higher performances, energy efficiency, cost-effectiveness, and multifunctionality, which have been the driving forces for the development of semiconductor technologies. New materials and integration processes are urgently needed to overcome these multi-faceted challenges. The heterointegration of dissimilar materials on the same platform has recently emerged as a powerful strategy to address some of these challenges. Particularly, tremendous efforts have been put to develop fabrication processes that allow the integration of III-V compound semiconductors on foreign substrates. For instance, III-V heterointegration on silicon substrates will enable the combination, within a single platform, III-V high-performance technologies with low cost and wafer size advantages besides its compatibility with standard semiconductor processing. In addition to electronic and optoelectronic applications, the realization of these hybrid substrates is also highly relevant for high-efficiency, low-cost photovoltaic cells, spintronics, bio-integrated technologies, to name a few. It is, however, noteworthy that this heterointegration needs to be achieved on the wafer level in order to be technologically and economically viable. In this presentation, we provide a description of important approaches to achieve this heterogeneous integration, with an emphasis on wafer bonding processes and thin layer splitting using the ion-cut process. A variety of bulk-quality heterostructures, frequently unattainable by direct epitaxial growth, can be produced provided that a list of technical criteria is fulfilled, thus offering an additional degree of freedom in the design and fabrication of heterogeneous, multifunctional, and flexible devices. Ion cutting is a generic process that can be employed to split and transfer fine monocrystalline layers from various crystals. Materials and engineering issues as well as our current understanding of the underlying physics involved in its application to cleaving thin layers from freestanding GaN, InP, and GaAs wafers will be presented and discussed.
Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Disclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.