IO Power Research Articles

Scaling of Output Load in Energy Efficient FIR Filter for Green Communication on Ultra-Scale FPGA

FIR Filter always remains in linear phase with the help of symmetric coefficient. This feature makes it ideal for phase-sensitive applications like data communications. Design of FIR filter with energy efficiency makes excellent sense to achieve energy efficiency in digital selected frequency module of communication. We are using scaling of output load from 5000 to 0 pF to show an effect of output load on both on-chip and off-chip power consumption of FIR filter design. 20 nm technology based FVA1156 package and Kintex-7 family ultra-scale FPGA is taken under reconsideration for implementation of our model. With the use of HSTL_II IO standards, there is 84.39 and 92.83% reduction in IOs power when we scale down capacitance from 5000 to 500 and 0 pF respectively. With the use of HSTL_I_18 IO standards, there is 72.48 and 80.13% reduction in total on-chip power when we scale down capacitance from 5000 to 500 and 0 pF respectively. Along with IOs power and total on-chip power, we have also analyzed Off-chip device power, junction temperature, thermal margin, and different dynamic power likes Signal power, logic power, and DSP power.

Core i7 Specific Energy Efficient Ram Design for IoT Application

Fundamental memory has turned out to be one of largest contributors to overall energy consumption and offer many opportunities for power reduction. Power dissipation plays important role in portable products that can store, receive and transmit data because in each operation cycle the power is consumed by the operator. The goal of this paper is to use Frequency scaling approach in Random Access Memory to minimize power dissipation by the help of High Speed Transceiver Logic (HSTL) input output standard. These techniques cover RTL coding. This research suggest that there is 75% reduction clock power 66.66% reduction in Signal power, (35.20% to 47.77%) reduction in IOs power when the frequency are minimize. This design is implemented on Artex-7.

Comparative Power Analysis of an Adaptive Bus Encoding Method on the MBUS Structure

This paper proposes a novel bus encoding method on MBUS in order to reduce the power consumption of system-on-chips (SoCs). The main contribution is to lower the bus activity by an average 64.55% and thus decrease the IO power consumption through reconfiguring the MBUS transmission. This method is effective because field-programmable gate array (FPGA) IOs are most likely to have very large capacitance associated with them and consequently dissipate a lot of dynamic power. Experimental result shows an average 70.96% total power reduction compared with the original MBUS implementation.

Note: A 10 Gbps real-time post-processing free physical random number generator chip

A random number generator with high data rate, small size, and low power consumption is essential for a certain quantum key distribution (QKD) system. We designed a 10 Gbps random number generator ASIC, TRNG2016, for the QKD system. With a 6 mm × 6 mm QFN48 package, TRNG2016 has 10 independent physical random number generation channels, and each channel can work at a fixed frequency up to 1 Gbps. The random number generated by TRNG2016 can pass the NIST statistical tests without any post-processing. With 3.3 V IO power supply and 1.2 V core power supply, the typical power consumption of TRNG2016 is 773 mW with 10 channels on and running at 1 Gbps data rate.

Measuring the Empowerment of International Organizations: The Evolution of Financial and Staff Capabilities.

International organizations’ (IOs) power in shaping global governance outcomes is not only determined by the formal delegation of tasks and issue areas but also by the necessary capabilities to fulfill these tasks. Yet, extant research on the delegation of power to IOs gives few insights into the financial and staff capabilities of IOs and focuses mainly on the formal rules that specify IOs’ tasks and issue scope. To address these limitations, this paper makes three contributions. First, we propose a more encompassing concept of IO power which incorporates three principal components: tasks, issue scope, and capabilities. Second, we introduce a new concept – IO empowerment (IOE) – which encapsulates formal and informal changes in IO power over time. Third, we introduce a novel dataset on IO capabilities, which measures the formal rules governing IO staff and financial resources as well as the actual capabilities available to six well‐known IOs over 65 years. These original data show that capabilities vary not only across IOs but also over time.

FPGA based Green Digital Clock Design for Network Synchronization using LVCMOS I/O Standard

The idea is to develop a green digital clock design that consumes least amount of power for its network specific operation. Low Voltage complementary metal oxide semiconductor i.e. LVCMOS IO standard is used at fixed temperature and changing output load at various frequencies. FPGA family used is Virtex-6 and software used of simulation of proposed algorithm for digital clock is Xilinx. Coding is done using Verilog. The results are taken for LVCMOS at frequency of 0.1GHz, 1GHz, 10GHz and 100 GHz and data is collected to prove it green digital clock. For making any device green means the amount of power consumed by it should be small with desirable output. There is 89.60%, 98.56%, 99.46% and 99.56% saving in IOs power when we reduce output load from 5000pF to 500pF, 50pF, 5pF and 0.5pF respectively.

LVCMOS IO Standard Based High Performance RAM Design on 28nm FPGA

In the work the energy efficient and thermal aware single-port RAM has been designed to make it more energy efficient using 28 nm Kintex-7 at ambient temperature of 25 ◦C design tool used is Xilinx 14.2 ISE. Frequency scaling approach has been taken to design energy and power efficient RAM. It is done by scaling frequencies from 50GHz to 200 GHz and calculating the Leakage Power, Quiescent Power as well as the Junction Temperature of Single–Port RAM. Leakage Power has been reduced to the range of 9.411% to 3.52%by Frequency Scaling technique, Quiescent Power Consumption in the range 9.33% to 4.00% and Junction Temperature range from 9.39% to 3.33%, IO Power consumption in range of 45.75% to 15.266% for 50GHz frequency and so on, which makes RAM Design energy efficient and thermal aware.

FPGA Based Low Power DES Algorithm Design and Implementation using HTML Technology

In this particular work, we have done power analysis of DES algorithm implemented on 28nm FPGA using HTML (H-HSUL, T-TTL, M-MOBILE_DDR, L-LVCMOS) technology. In this research, we have used high performance software Xilinx ISE where we have selected four different IO Standards i.e. MOBILE_DDR, HSUL_12, LVTTL and LVCMOS (LVCMOS_15, LVCMOS_18, LVCMOS_25 and LVCMOS_33). We have done power analysis of on-chip power like clock power, signals power, IO power, leakage power and supply power. We notified our analysis at five different voltages like 0.5V, 0.8V, 1.0V, 1.2V and 1.5V.

Architecture of a Reusable BIST Engine for Detection and Autocorrection of Memory Failures and for IO Debug, Validation, Link Training, and Power Optimization on 14-nm SoC

This paper presents the hardware and software architecture of a reusable BIST engine for 3D stacked 14-nm SoC, which also includes softwareassisted autorepair of memory defects. Silicon results presented demonstrate the features of such engine such as easy silicon debug, validation time reduction by 3x, detection and repair of memory cell defects, etc. This solution has been successfully designed and used for seven Intel SoCs successfully debugged, tested, and launched into the market place.

English

Stub-Series Terminated Logic (SSTL) IO standards and theory of Vedic Mathematics are used in design of Vedic multiplier. This vedic multiplier is a part of Vedic arithmetic circuits design project for Vedic Processor Design. This Vedic multiplier design is based on the formula “Urdhva-Tiryagbhyam” means Vertical and cross wise. SSTL135_R is minimum I/O power consumer. SSTL135_DCI is maximum power consumer. There is 8.27% reduction in Total power when we use SSTL12_DCI in place of SSTL135_DCI at 56.7C. There is 14.19% reduction in IO power when we use SSTL12_DCI in place of SSTL135_DCI at 56.7C. There is 50% reduction in Total power when we use SSTL135_R in place of SSTL135_DCI at 56.7C. There is 85.16% reduction in IO power when we use SSTL135_R in place of SSTL135_DCI at 56.7C. This design is implemented on 28nm FPGA using Verilog and Xilinx Integrated System Environment 14.1. There is no change in Leakage power with change in IO standards. Leakage power depends on ambient temperature. In the other words, leakage power is directly proportional to ambient temperature. Keywords–SSTL, Low Power, Vedic Multiplier, IO Standard, FPGA

English

In the domain of High Performance Energy Efficient Computing (HPEEC), the focus of research is shifting toward energy efficient computing or low power VLSI design or green computing. We are applying three different clock gating technique in target design of Gurmukhi Unicode Reader (GUR). These power saving techniques reduce the power dissipation of GUR in significant amount. It has been observed that if we switch to flip flop based clock gating instead of simple clock then we can save 89.6% of clock power and we can save 90.48% of clock power if we switch to latch free clock gating (LFCG) or latch based clock gating (LBCG) in case of all SSTL based logic families. It has been observed that if we switch to flip flop based clock gating instead of simple clock then we can save 23.88% of IO power and we can save 26.59% of IO power if we switch to either LFCG or LBCG in case of SSTL2_II_DCI. It has been observed that if we switch to FFBCG instead of simple clock then we can save 52.38% of total power and we can save 56.67% of total power if we switch to either LFCG or LBCG in case of SSTL2_II_DCI.

IO Standards based Energy Efficient Room Temperature Sensor Design

In this work energy efficient room temperature sensor is designed using various IO standards. This design is implemented on Kintex-7 FPGA, XC7K70T device and FBG676 package. The simulator used is Xilinx 14.6 and Verilog is used as the verification language. The power analysis is done using XPower estimator. The various IO standards implemented in the design are HSUL_12, Mobile_DDR, PCI33_3 and SSTL18_II. The temperature scaling is being done for analyzing the behavior of circuit at different temperature values. The temperature is scaled from 50 o C to 45 o C, 40 o C, 35 o C, 30 o C and 25 o C. There is reduction of 17.39%, 65.22% and 91.30% in IO power when we migrate our design from SSTL18_II to HSUL_12, Mobile_DDR and PCI33_3 IO standards respectively. The maximum reduction in total power is achieved when the design is migrated from SSTL18_II to PCI33_3 IO standard. The reduction in total power is 26.32%, 24.69%, 22.72%, 20.83%, 18.87% and 16.95% at 25 o C, 30 o C, 35 o C, 40 o C, 45 o C and 50 o C respectively when the IO standard is migrated from SSTL18_II to PCI33_3.

SSTL Based Power Efficient Implementation of DES Security Algorithm on 28nm FPGA

In this particular work, we have done power dissipation analysis of DES algorithm, implemented on 28nm FPGA. We have used Xilinx ISE software development kit for all the observation done in this particular research work. Here, we have taken SSTL (StubSeries Terminated Logic) as input-output standard. We have considered six subcategories of SSTL (i.e. SSTL135, SSTL135_R, SSTL15, SSTL15_R, SSTL18_I and SSTL18_II) for four different WLAN frequencies (i.e. 2.4GHz, 3.6GHz, 4.9GHz, and 5.9GHz). We have done analysis considering five basic powers i.e. clock power, logic power, signal power, IOs power, leakage power and total power. There is 50-60% reduction in power dissipation, which is possible with proper selection of the most energy efficient IO standards i.e. SSTL135_R among SSTL logic families.

CACTI-IO: CACTI With OFF-Chip Power-Area-Timing Models

In this paper, we describe CACTI-IO, an extension to CACTI that includes power, area, and timing models for the IO and PHY of the OFF-chip memory interface for various server and mobile configurations. CACTI-IO enables design space exploration of the OFF-chip IO along with the dynamic random access memory and cache parameters. We describe the models added and four case studies that use CACTI-IO to study the tradeoffs between memory capacity, bandwidth (BW), and power. The case studies show that CACTI-IO helps to: 1) provide IO power numbers that can be fed into a system simulator for accurate power calculations; 2) optimize OFF-chip configurations including the bus width, number of ranks, memory data width, and OFF-chip bus frequency, especially for novel buffer-based topologies; and 3) enable architects to quickly explore new interconnect technologies, including 3-D interconnect. We find that buffers on board and 3-D technologies offer an attractive design space involving power, BW, and capacity when appropriate interconnect parameters are deployed.

LVCMOS and BLVDS Based Energy Efficient Counter Design on 28nm FPGA

Counter play an important role in design of stopwatch, countdown of space craft, rocket, launcher and so on. In this work, we are going to design energy efficient counter. For that we are exploring 10 different configuration of counter and find the most energy efficient counter among them. For further reduction of power dissipation of the most efficient counter, we are using different Input/Output standards and select the most energy efficient IO standards for counter. 8 bit Up counter with Load has maximum reduction in total power among 10 different counters. When we use LVCMOS15, LVCMOS18, LVCMOS25, and LVCMOS33 in place of BLVDS_25 then there is 65-81% reduction in total power dissipation in 8 bit Up counter with Load. As we move down the column from LVCMOS15 to LVCMOS33 there is 94-77% reduction in IO power Dissipation and leakage power variation is very less. Keywords—Counter, LVCMOS, BLVDS, FPGA, Energy Efficient, clock, enable, up down counter, one hot counter, random LFSR counter, divide by 3 counter.

IoTs Enable Active Contour Modeling Based Energy Efficient and Thermal Aware Object Tracking on FPGA

Object tracking based on active contour modeling is an image processing related technology that uses snapshots of the object under consideration to track it via robot in the real world. Nowadays, the word is moving towards the internet of things (IoTs) and having significant effect on our daily life. In this work, we have designed IoTs enable power efficient and thermal aware frame buffer to store the frames and uses that frame to detect changes in object position. In order to make IoTs enable design, we are embedding a 128-bit IPv6 address into frame buffer. In order to test the compatibility of this design with wireless network, we are operating this design with different operating frequency of WLAN channel. The operating frequency of WLAN Channel 802.11ah, 802.11b/g/n, 802.11y, 802.11a/h/j/n/ac, 802.11p and 802.11d are 900 MHz, 2.4, 3.6, 5, 5.9 and 60 GHz respectively. There is no change in signal power, clock power, IO power, when we scale down ambient temperature from 70 to 30 °C. There are 98---89 % saving in signal power, 2---85 % reduction in clock power, 90---99 % saving in IO power with WLAN Channel 802.11ah, 802.11b/g/n, 802.11y, 802.11a/h/j/n/ac, 802.11p in compare to power dissipation with 802.11ad. There is 71.11, 72.60, 73.96, 74.28, and 74.42 % reduction in leakage power with WLAN Channel 802.11ah, 802.11b/g/n, 802.11y, 802.11a/h/j/n/ac, and 802.11p, when we scale down ambient temperature from 70 to 30 °C. IoTs enable frame buffer design can be controlled from any part of this globe. Another design characteristic of this frame buffer is that it is 3-D frame buffer which gives us an added advantage over 2-D frame buffer that store image only in X, Y orientation. Capability to analyze third dimension helps us to track object more efficiently.

I2C and HSTL IO Standard Based Low Power Thermal Aware Adder Design on 45nm FPGA

In this work, we are we are going to search the most thermal and energy efficient IO Standards among the HSTL family and I2C family on 45 nm technology based FPGA. Here we are also doing thermal analysis for 273.15K-343.15K temperature, while during comparing the different IO Standards, we are taking the improvement level at 283.15K. In leakage power analysis, we are getting 9.09% improvement in HSTL with respect to others and in IO power analysis I2C shows 57.89% improvement with respect to others. In thermal analysis for maximum ambient temperature, we observe 1.79% improvement in HSTL_II as compared to others and in Junction Temperature analysis HSTL_I and I2C are 3.6% efficient than others. HSTL_I has minimum Theta Junction to Ambient Temperature value. In this work, we are using 45nm Spartan-6 FPGA. . We are taking airflow of 250LFM where LFM is a unit of airflow. LFM is linear feet per minute. Adder is our target design.

An Energy Efficient Design Using CSAT Approach on Ultra Scale FPGA

In this paper an approach called Capacitance Scaling Ambient Temperature (CSAT) is used to design an energy efficient as well as thermal efficient GCD generator. Energy efficient means it dissipates less power either IO power or leakage power than their traditional counterpart. Thermal efficient means junction temperature of FPGA is lesser than their traditional counterpart. Where, Junction temperature is the highest temperature of an actual device or silicon die in FPGA. Our work shows the variance of I/O power and Junction temperature at different capacitance values under different frequencies. There is 15.22% reduction in I/O Power when we scale down capacitance from 100pF to 80pF. There is 29.31%, 44.83%, 58.62%, and 74.14% reduction when we further scale down capacitance to 60pF, 40pF, 20pF and 0pF. When we scale down capacitance from 100pF to 80pF, 60pF, 40pF, 20pF and 0pF, there is 3%, 6%, 9.14%, 12.14% and 15.19% reduction in junction temperature respectively at 100GHz device operating frequency. Virtex-6 is our target FPGA device for this design. Keywords—CSAT, Greatest Common Divisor (GCD), Capacitance, Energy Efficient Design, I/Os Power, Junction Temperature FPGA.

Thermal Mechanics Based Energy Efficient FIR Filter for Digital Signal Processing

Thermal mechanism cover the mechanics of Hit Sink, Airflow mechanics, and Ambient Temperature Mechanism to reduce junction temperature in design of Finite Duration Impulse Response (FIR) Filter. In this work, we are implementing FIR Filter on 28nm FPGA. After implementation of FIR Filter, we analyze the effect of in-built mechanism of Air Flow Controller and their produced Airflow on the junction temperature of FPGA. The mechanism of Ambient Temperature controller also play significant role in leakage power dissipation as well as junction temperature of FPGA. Finally, the mechanical structure of Hit Sink is considered for control of junction temperature of FPGA. There is 73.38% reduction in Leakage Power on 55 C ambient temperature when we increase airflow from 250 LFM to 500 LFM. Along with 500 LFM airflow, if we provide high profile hit sink then there is 78.31% reduction in leakage power. There is 37.68% reduction in junction temperature of FPGA when we increase airflow from 250LFM to 500LFM. Along with 500 LFM airflow, if we provide high profile hit sink then there is 41.76 % reduction in junction temperature on 45C ambient temperature. There is no effect of airflow on clock power. Whereas there is significant reduction in Logic Power, Signal Power, DSPs Power and IOs Power with change in Airflow.

Frequency Scaling Based Green Mobile Battery Charge Controller Sensor Design on FPGA

Frequency Scaling based energy efficient MBCCS is implemented in this paper. In this design, if battery's voltage or current is less than threshold then battery will continue charging. Whereas, if voltage or current is more than threshold then it will ring Overcharge Alarm. With Frequency Scaling, we reduce frequency from 1THz to 25GHz, where 125GHz, 625GHz are intermediate frequency value. There is 97.50%, 100%, 97.54%, 97.48%, 20%, 96.48 % reduction in clock power (CP), logic power (LP), signal power (SP), IOs power (IOP), leakage power and total power dissipation respectively when we scale down frequency from 1 THz to 25GHz.