Comparative Power Analysis of an Adaptive Bus Encoding Method on the MBUS Structure

X Yang,N Wu,J H Andrian

doi:10.1155/2017/4914301

Abstract

This paper proposes a novel bus encoding method on MBUS in order to reduce the power consumption of system-on-chips (SoCs). The main contribution is to lower the bus activity by an average 64.55% and thus decrease the IO power consumption through reconfiguring the MBUS transmission. This method is effective because field-programmable gate array (FPGA) IOs are most likely to have very large capacitance associated with them and consequently dissipate a lot of dynamic power. Experimental result shows an average 70.96% total power reduction compared with the original MBUS implementation.

Highlights

For the energy-limited IoT and wearable devices, low-power technologies to prolong the life of the battery become an important constraint for embedded chip design [1, 2]
Based on the master bus (MBUS) protocol, this paper presents a novel bus encoding technology on the existing address signal in order to reduce the dynamic power
The toggle rate and IO power decreasing can reach up to 18.9% in the best case of Mode#1, and in the same test the total power reduction is achieved by 29.1%

Summary

Introduction

For the energy-limited IoT and wearable devices, low-power technologies to prolong the life of the battery become an important constraint for embedded chip design [1, 2]. The existing on-chip buses, such as AHB [6] and AXI [7] from ARM Holdings, Wishbone from Silicore Corporation [8], and OCP from OCP-IP [9], cost much hardware resource in terms of slice/gate count and energy consumption, due to a large number of IO and signal definitions and complicated structures They are designed for a broad range of various applications and are characterized by high flexibility, scalability, and universality. Under this context, a cost-effective and power-efficient control bus named as master bus (MBUS) [10] has been proposed for specific IoT applications as our previous work, making a better balance between the limited energy on tiny-size embedded chips and high speed requirement of complex computations.

Related Work

Proposed Encoding MBUS

Implementation of the Encoding MBUS Structure

Results and Analysis

Conclusions