Power Consumption Management on FPGAs

Abstract

During the last years, the number of hardware implementations based on field programmable gate arrays (FPGA) is increasing because it satisfies the high speed of system and hardware cost constraints. FPGA implementation allows the building of rapid prototypes reducing development times and board area. However, since FPGA has been improved to satisfy speed and size constraints, it is not evident that these devices can satisfy the low power consumption constraint. Compared to ASIC, FPGA are generally perceived as non-low-power consumption devices, whose only advantage is programmability and more recently dynamic reconfigurability. In this work we present a study of dynamic and static power consumption of FPGA that allows the designer to acquire a better understanding of how power consumption is generated and distributed inside the FPGA. Based on these results, a genetic algorithm is used to minimize critical long paths and optimize the internal resources during the place and route process in order to optimize power consumption while keeping a high performance.