LVCMOS and BLVDS Based Energy Efficient Counter Design on 28nm FPGA

Abstract

Counter play an important role in design of stopwatch, countdown of space craft, rocket, launcher and so on. In this work, we are going to design energy efficient counter. For that we are exploring 10 different configuration of counter and find the most energy efficient counter among them. For further reduction of power dissipation of the most efficient counter, we are using different Input/Output standards and select the most energy efficient IO standards for counter. 8 bit Up counter with Load has maximum reduction in total power among 10 different counters. When we use LVCMOS15, LVCMOS18, LVCMOS25, and LVCMOS33 in place of BLVDS_25 then there is 65-81% reduction in total power dissipation in 8 bit Up counter with Load. As we move down the column from LVCMOS15 to LVCMOS33 there is 94-77% reduction in IO power Dissipation and leakage power variation is very less. Keywords—Counter, LVCMOS, BLVDS, FPGA, Energy Efficient, clock, enable, up down counter, one hot counter, random LFSR counter, divide by 3 counter.