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Stub-Series Terminated Logic (SSTL) IO standards and theory of Vedic Mathematics are used in design of Vedic multiplier. This vedic multiplier is a part of Vedic arithmetic circuits design project for Vedic Processor Design. This Vedic multiplier design is based on the formula “Urdhva-Tiryagbhyam” means Vertical and cross wise. SSTL135_R is minimum I/O power consumer. SSTL135_DCI is maximum power consumer. There is 8.27% reduction in Total power when we use SSTL12_DCI in place of SSTL135_DCI at 56.7C. There is 14.19% reduction in IO power when we use SSTL12_DCI in place of SSTL135_DCI at 56.7C. There is 50% reduction in Total power when we use SSTL135_R in place of SSTL135_DCI at 56.7C. There is 85.16% reduction in IO power when we use SSTL135_R in place of SSTL135_DCI at 56.7C. This design is implemented on 28nm FPGA using Verilog and Xilinx Integrated System Environment 14.1. There is no change in Leakage power with change in IO standards. Leakage power depends on ambient temperature. In the other words, leakage power is directly proportional to ambient temperature. Keywords–SSTL, Low Power, Vedic Multiplier, IO Standard, FPGA