Inverter Ring Oscillator Research Articles

A Novel Scheme for Full Bottom Dielectric Isolation in Stacked Si Nanosheet Gate-All-Around Transistors.

In this paper, a novel scheme for source/drain-first (S/D-first) full bottom dielectric isolation (BDI), i.e., Full BDI_Last, with integration of a sacrificial Si0.5Ge0.5 layer was proposed and demonstrated in a stacked Si nanosheet gate-all-around (NS-GAA) device structure using TCAD simulations. The proposed full BDI scheme flow is compatible with the main process flow of NS-GAA transistor fabrication and provides a large window for process fluctuations, such as the thickness of the S/D recess. It is an ingenious solution to insert the dielectric material under the source, drain and gate regions to remove the parasitic channel. Moreover, because the S/D-first scheme decreases the problem of high-quality S/D epitaxy, the innovative fabrication scheme introduces full BDI formation after S/D epitaxy to mitigate the difficulty of providing stress engineering in the full BDI formation before S/D epitaxy (Full BDI_First). The electrical performance of Full BDI_Last is demonstrated by a 4.78-fold increase in the drive current compared to Full BDI_First. Furthermore, compared to traditional punch through stoppers (PTSs), the proposed Full BDI_Last technology could potentially provide an improved short channel behavior and good immunity against parasitic gate capacitance in NS-GAA devices. For the assessed inverter ring oscillator (RO), applying the Full BDI_Last scheme allows the operating speed to be increased by 15.2% and 6.2% at the same power, or alternatively enables an 18.9% and 6.8% lower power consumption at the same speed compared with the PTS and Full BDI_First schemes, respectively. The observations confirm that the novel Full BDI_Last scheme incorporated into an NS-GAA device can be utilized to enable superior characteristics to benefit the performance of integrated circuits.

Hyper-FET's Phase-Transition-Materials Design Guidelines for Ultra-Low Power Applications at 3 nm Technology Node.

In this work, a hybrid-phase transition field-effects-transistor (hyper-FET) integrated with phase-transition materials (PTM) and a multi-nanosheet FET (mNS-FET) at the 3 nm technology node were analyzed at the device and circuit level. Through this, a benchmark was performed for presenting device design guidelines and for using ultra-low-power applications. We present an optimization flow considering hyper-FET characteristics at the device and circuit level, and analyze hyper-FET performance according to the phase transition time (TT) and baseline-FET off-leakage current (IOFF) variations of the PTM. As a result of inverter ring oscillator (INV RO) circuit analysis, the optimized hyper-FET increases speed by +8.74% and reduces power consumption by -16.55%, with IOFF = 5 nA of baseline-FET and PTM TT = 50 ps compared to the conventional mNS-FET in the ultra-low-power region. As a result of SRAM circuit analysis, the read static noise margin is improved by 43.9%, and static power is reduced by 58.6% in the near-threshold voltage region when the PTM is connected to the pull-down transistor source terminal of 6T SRAM for high density. This is achieved at 41% read current penalty.

DTCO flow for air spacer generation and its impact on power and performance at N7

A novel DTCO flow is described with the principal aim to study the impact of air spacer fabrication on the power and performance of a 5-stage inverter ring oscillator at the 7 nm node. The flow incorporates physical and analytical process models from the in-house ViennaPS simulation tool together with device and circuit simulations from GTS Framework’s Cell Designer. The air spacer is usually filled by sequential conformal and non-conformal deposition steps. The impact of the thickness of the conformal layer and the sticking probability during non-conformal deposition on the ring oscillator performance is studied here. The air gap, which forms the core of the air spacer, is generated during the non-conformal deposition step. We extract the relative effective permittivity of the air spacer as a function of these two fabrication parameters by solving the Poisson equation to obtain the spacer capacitance. Finally, SPICE model cards are extracted automatically from the TCAD transistor characteristics and the parasitic network is calculated from the full 3D ring oscillator logic cell using a field solver. We apply our framework on two fabrication flows, when the air gap is created before and after the deposition of the first metal contacts layer. We observe that introducing the air gap inside the spacer results in an at-least 15% improvement in the ring oscillator’s performance, when the power is kept constant. Further improvements can be achieved by reducing the conformal layer thickness and increasing the sticking probability by increasing the chamber partial pressure or increasing the process temperature.

Optimization of Gate-All-Around Device to Achieve High Performance and Low Power with Low Substrate Leakage.

In this study on multi-nanosheet field-effect transistor (mNS-FET)—one of the gate-all-around FETs (GAAFET) in the 3 nm technology node dimension—3D TCAD (technology computer-aided design) was used to attain optimally reduced substrate leakage from options including a punch-through-stopper (PTS) doping scheme and a bottom oxide (BO) scheme for bottom isolation, with the performance improvement being shown in the circuit-level dynamic operation using the mNS-FET. The PTS doping concentration requires a high value of >5 × 1018 cm−3 to reduce gate induced drain leakage (GIDL), regardless of the presence or absence of the bottom isolation layer. When the bottom isolation is applied together with the PTS doping scheme, the capacitance reduction is larger than the on-state current reduction, as compared to when only the PTS doping concentration is applied. The effects of such transistor characteristics on the performance and capabilities of various circuit types—such as an inverter ring oscillator (RO), a full adder (FA) circuit, and a static random-access memory (SRAM)—were assessed. For the RO, applying BO along with the PTS doping allows the operating speed to be increased by 11.3% at the same power, or alternatively enables 26.4% less power consumption at the same speed. For the FA, power can be reduced by 6.45%, energy delay product (EDP) by 21.4%, and delay by 16.8% at the same standby power when BO and PTS are both applied. Finally, for the SRAM, read current (IREAD) increased by 18.7% and bit-line write margin (BWRM) increased by 12.5% at the same standby power. Through the circuit simulations, the Case 5 model (PTS doping concentration: 5.1 × 1018 cm−3, with BO) is the optimum condition for the best device and circuit performance. These observations confirm that PTS and bottom isolation applications in mNS-FETs can be utilized to enable the superior characteristics of such transistors to translate into high performance integrated circuits.

Analysis of Swarm Intelligence Based ANN Algorithms for Attacking PUFs

Physical Unclonable Functions (PUFs) are used for authentication and generation of secure cryptographic keys. However, recent research work has shown that PUFs, in general, are vulnerable to machine learning modeling attacks. From a subset of Challenge-Response Pairs (CRPs), the remaining CRPs can be effectively predicted using different machine learning algorithms. In this work, Artificial Neural Networks (ANNs) using swarm intelligence-based modeling attacks are used against different silicon-based PUFs to test their resiliency to these attacks. Amongst the swarm intelligence algorithms, the Gravitational Search Algorithm (GSA), Cuckoo Search Algorithm (CS), Particle Swarm Optimizer (PSO) and the Grey Wolf Optimizer (GWO) are used. The attacks are extensively performed on six different types of PUFs; namely, Configurable Ring Oscillator, Inverter Ring Oscillator, XOR-Inverter Ring Oscillator, Arbiter, Modified XOR-Inverter Ring Oscillator, and Hybrid Delay Based PUF. From the results, it can be concluded that the first four PUFs under study are vulnerable to ANN swarm intelligence-based models, and their responses can be predicted with an average accuracy of 71.1% to 88.3% for the different models. However, for the Hybrid Delay Based PUF and the Modified XOR-Inverter Ring Oscillator PUF, which are especially designed to thwart machine learning attacks, the prediction accuracy is much lower and in the range of 9.8% to 14.5%.

A Sub-10 mV Power Converter With Fully Integrated Self-Start, MPPT, and ZCS Control for Thermoelectric Energy Harvesting

An inductive power converter for thermoelectric generator (TEG) is presented in this paper. A novel redundant inverter ring oscillator is proposed to self-oscillate in a very low supply voltage down to 45 mV. An additional self-start assist circuit with a differential clock booster and an exponential charge pump is implemented in the power converter to achieve lower self-start voltage. Boundary continuous-conduction mode, zero current switch (ZCS), and maximum power point tracking (MPPT) features have been incorporated into the power converter. Selective turn-ON dynamical-comparators have been used in ZCS and MPPT circuits to save power and achieve minimum operating supply voltage. Fabricated in 65-nm CMOS process, the chip can self-start at 210 mV. After self-start, only 7-mV input voltage is needed to sustain the power converter operation. With a TEG open circuit voltage of 80 mV and internal resistance of $5~\Omega $ , the chip can provide a maximum output power of $229~\mu \text{W}$ with end-to-end efficiency of 71.5%.

A gate sizing and transistor fingering strategy for subthreshold CMOS circuits

Parallel Transistor Stacks (PTS) has been shown to be an effective technique for improving the speed of digital circuits operating in the subthreshold region which comes at the cost of power consumption and area. However, our experience shows that using PTS is not beneficial in all cases. In this paper, we present a methodology to identify whether using PTS is beneficial (or not) in a particular CMOS technology and what transistor sizing can be employed to maximize the circuit speed. Our technique is based on analyzing the Current-Over-Capacitance (COC) ratio of PMOS and NMOS transistors. The results of incorporating the proposed methodology in a 4-bit comparator and a 19-stage inverter ring oscillator, using 90nm CMOS technology, illustrate 26% and 40% extra improvement compared to the blind use of PTS, respectively.

Effect of Regularity-Enhanced Layout on Variability and Circuit Performance of Standard Cells

As the minimum feature size shrinks down far below sub-wavelength, Design for Manufacturability or layout regularity plays an important role for maintaining pattern fidelity in photolithography. However, it also incurs overheads in circuit performances due to parasitic capacitance. In this paper, we examine the effect of layout regularity on printability and circuit performance by lithography simulation and transistor-level simulation. It is shown that regularity-enhanced cells provide better Critical Dimension (CD) stability under defocus and lead to delay increase. Then we evaluate the effect of layout regularity by a real chip measurement in 90nm, 65nm and 45nm processes. For example, in a 65nm process, inverter Ring Oscillators (ROs) that have the smallest poly pitch with dummy-poly insertion exhibits 19% reduction of WID and D2D variation with delay overhead of 2.5%, compared to the ROs without dummy-poly insertion. However, we have observed that the effect of layout regularity varies depending on fabrication processes and circuit structures. It is therefore important to obtain the best trade-off among performance overhead and variability reduction for each process technology.

Bulk-drain connected load for subthreshold MOS current-mode logic

Bulk-drain connected PMOS transistors are proposed as loads for subthreshold MOS current-mode logic gates. Such loads exhibit an approximately linear dependence of the subthreshold drain-source current on the drain-source voltage, guaranteeing robust gate operation. The design and performance of an inverter gate and ring oscillator in a 0.25 mum CMOS technology are presented

Linearity of bulk-controlled inverter ring VCO in weak and strong inversion

In this paper linearity of frequency modulation in voltage controlled inverter ring oscillators for non feedback sigma delta converter applications is studied. The linearity is studied through theoretical models of the oscillator operating at supply voltages above and below the threshold voltage of a transistor, bringing the transistors in respectively strong and weak inversion. The theoretical results are tested with more advanced models through spectreRF simulations. A soft rail approach implemented to improve linearity in weak inversion is proposed and demonstrated. The influence from voltage noise, process variations and temperature variations have also been simulated to indicate the advantages of having the soft rail bias transistor in the VCO.

Device enhancement using process-strained-Si for sub-100-nm nMOSFET

Process-induced strain using a high-tensile contact etch stop layer has demonstrated 18% transconductance and 18% driving current enhancement at a gate length/width of 80 nm/0.6 /spl mu/m for bulk nMOSFETs without degrading the device performance of pMOSFET. A superior current drive at 917 /spl mu/A//spl mu/m for nMOSFET is achieved with 1.7-nm gate oxide, 80-nm gate length, and 1.2-V operation voltage. The gate delay for an inverter ring oscillator is improved up to 13%.

A low-cost programmable clock generator for switched-capacitor circuit applications

This paper presents two improved circuit techniques that allow the design of a low-cost programmable clock generator using a ring oscillator for low-frequency switched-capacitor applications. The first technique aims at reducing the frequency of the oscillator with small capacitors by proposing a Miller current-starved inverter ring oscillator. For identical values of integrated components in implementation, the proposed ring oscillator reduces the oscillation frequency by 5 times over the conventional ring oscillator and 3 times over the conventional current-starved inverter ring oscillator. This benefits the relaxation of PSRR requirement and the reduction of substrate noise coupling in mixed-signal circuits. The second technique aims at enhancing the reliability of the programmed data by proposing orthogonal fusible link trimming circuit. The experimental results have verified that the programming range of 56 kHz to 1.042 MHz is achieved using discrete-step tuning on small capacitor values from 0.375 pF to 5.625 pF together with frequency division by four divider stages, whilst the jitter is less than 300 ps at ±10% variation in a 5 V supply in the entire tuning range.

Write pulse Generator for 16x DVD recording with symmetric CMOS inverter ring oscillator

This paper reports the design and measurement results of a write pulse generator IC for rewritable CD and DVD disk drives implemented in a standard digital 0.35 /spl mu/m CMOS technology. The chip is the interface between a processor and a laser driver. It provides accurate timing signals to the laser driver via a four-level differential current interface. Transitions between current levels are programmable with 149 ps resolution at a data rate of 420 Mb/s, corresponding to 16x DVD write speed. The chip includes a digital core managing the different write strategies, a CMOS serial interface to the processor for programming, a low power, low phase noise, 64-phase ring voltage-controlled oscillator (VCO) based on CMOS inverters, a phase-locked loop (PLL) locking the VCO to the system clock, and a current interface to the laser driver. The PLL phase noise is -144 dBc/Hz at 10 MHz offset from the 105 MHz carrier. At this frequency, the rms jitter is 1.1 ps with 0.8 mA VCO core supply current. The chip is fully ESD protected.

Manufacturability of single and double-gate ultrathin silicon film fully depleted SOI technologies

Of several possible devices that can be used for sub-70 nm node technologies, two are built on ultra thin SOI layers. Scaling of such thin silicon layer SOI devices is constrained by the severe short channel control problem. To alleviate this, double-gate structures have been proposed by Wong et al. (1999), Chang et al. (2000), and Ieong et al. (2000). In this paper, we assess the manufacturability of single-gate (SG) and symmetric double-gate (DG) devices for gate lengths between 15 and 70 nm. Our results show that SG devices are not only manufacturable but also have tighter distributions than DG devices; inverter ring oscillator (RO) stage delays and power consumption are also better for SG devices. Besides gate length we find two additional major sources of variation: silicon thickness and encapsulation width. We show that for an optimized double-gate device with minimized parasitic resistance, CD variations become a dominant factor at 20-nm gate lengths despite superior electrostatic integrity. Also, the work function of metal gates must be controlled to better than /spl plusmn/0.1 eV (3/spl sigma/) to avoid severe manufacturability problems.

Ultralow resistance W/poly-Si gate CMOS technology using amorphous-Si/TiN buffer layer

Advanced tungsten/pn-poly-Si gate CMOS devices with an ultralow sheet resistance of 1 /spl Omega//sq. have been demonstrated using an amorphous-Si/TiN buffer layer. A low-resistivity tungsten film is formed by large grain size tungsten on an amorphous-silicon (a-Si) film. This result can be explained by the Mayadas-Shatzkes theory. After a source/drain annealing process, W/a-Si/TiN/pn-poly-Si systems become W/WSi/sub x//TiN/pn-poly-Si systems without impurity interdiffusion between the pn-poly-Si gate electrodes. The propagation delay time of a CMOS inverter ring oscillator with this novel gate electrode is considerably smaller than that with a cobalt-salicide film in a wider channel width.

Single-gate 0.15 and 0.12 μm CMOS with Co salicide technology

A high-speed 0.15 μm single-gate Co salicide CMOS technology has been demonstrated, which suppresses short channel effects in 0.15 μm buried channel pMOSFETs by optimizing the fabrication conditions of their extension region. An unloaded CMOS inverter ring-oscillator delay of 19.8 ps has been obtained. At 0.12 μm gate length, 11.4 ps gate delay was observed.

Intra-field effects on device and circuit manufacturability: a statistical simulation approach

In spite of the numerous improvements in deep ultraviolet (DUV) lithography, minimizing lens aberrations remains critical to obtaining manufacturable logic technologies. In this paper, we investigate the effects of lens imperfections on the distributions of process, device, and circuit parameters. Lens imperfections, as manifested by intrafield gate critical dimension (CD) variations, can affect device and circuit parameters strongly. The latter is central to designing fast high-yielding logic products, especially microprocessors. Our approach employs process, device, and statistical simulations, coupled with extensive calibration, to predict manufacturing distributions for a new technology well before it is ramped to full-scale production. We study nominal channel length n- and p-channel devices, inverter ring oscillators, and four-input NAND standard cells, We compare different stepper conditions both for conventional and annular illumination. We consider the case of more than one die in a reticle field and investigate how lens imperfections affects different dice therein. We apply our approach to an experimental DUV stepper and demonstrate coma effects that potentially lower yields. Our results also include a paradox: the best annular illumination case, which betters the CD distributions of conventional illumination, ultimately yields worse circuit performance.

High-performance 0.07-μm CMOS with 9.5-ps gate delay and 150 GHz f/sub T/

We report room-temperature 0.07-/spl mu/m CMOS inverter delays of 13.6 ps at 1.5 V and 9.5 ps at 2.5 V for an SOI substrate; 16 ps at 1.5 V and 12 ps at 2.5 V for a bulk substrate. This is the first room-temperature sub-10 ps inverter ring oscillator delay ever reported. PFETs with very high drive current and reduction in parasitic resistances and capacitances for both NFETs and PFETs, realized by careful thermal budget optimization, contribute to the fast device speed. Moreover, the fast inverter delay was achieved without compromising the device short-channel characteristics. At V/sub dd/=1.5 V and I/sub off//spl sim/2.5 nA//spl mu/m, minimum L/sub eff/ is about 0.085 /spl mu/m for NFETs and 0.068 /spl mu/m for PFETs. PFET I/sub on/ is 360 /spl mu/A//spl mu/m, which is the highest value ever reported at comparable V/sub dd/ and I/sub off/. The SOI MOSFET has about one order of magnitude higher I/sub off/ than a bulk MOSFET due to the floating-body effect. At around 0.07 /spl mu/m L/sub eff/, the NFET cut-off frequencies are 150 GHz for SOI and 135 GHz for bulk. These performance figures suggest that subtenth-micron CMOS is ready for multi-gigahertz digital circuits, and has good potential for RF and microwave applications.

Evaluation of a copper metallization process and the electrical characteristics of copper-interconnected quarter-micron CMOS

Copper metallization was applied to quarter-micron CMOS circuits using copper chemical vapor deposition (CVD) and chemical mechanical polishing (CMP). Both the metallization process and the electrical characteristics of CMOS devices/circuits were evaluated. Process-induced metal contamination on both sides of the wafer were quantitatively evaluated and reduced to about of 10/sup 11/ atoms/cm/sup 2/ by using an optimized cleaning sequence. The ability of borophosphosilicate-glass (BPSG) to act as a copper diffusion barrier was discovered and the ability of TiN to do so was also confirmed. Electrical characteristics of n and p MOSFET's with copper interconnections were stable even after annealing at 550/spl deg/C. The leakage current of the pn junction, capacitance-voltage characteristics and time-dependent dielectric breakdown characteristics of the MOS diode indicate that the copper metallization process did not deteriorate the pn junction and the gate oxide. Normal operation of a 53-stage quarter-micron CMOS inverter ring oscillator with copper metallization was successfully achieved.

21-ps 0.1- mu m CMOS devices operating at room temperature

High-speed complementary metal-oxide semiconductor (CMOS)-inverter ring oscillators with the shortest gate length of 0.17 mu m were fabricated by a conventional large-scale integrated (LSI) technology. The propagation delays were 21 ps / stage (2.0 V) at room temperature and 17 ps / stage (2.0 V) at 80 K. These results are the fastest records reported for bulk CMOS devices as of today. The results were obtained by reducing effective drain junction capacitances with "double-finger gates," and devices will probably be faster if the areas are completely proportionally reduced to the feature size. Though it is important for CMOS devices to increase drain currents, a silicidation technique for source and drain was not necessary for the tested devices to reduce series resistance.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>