DTCO flow for air spacer generation and its impact on power and performance at N7

Abstract

A novel DTCO flow is described with the principal aim to study the impact of air spacer fabrication on the power and performance of a 5-stage inverter ring oscillator at the 7 nm node. The flow incorporates physical and analytical process models from the in-house ViennaPS simulation tool together with device and circuit simulations from GTS Framework’s Cell Designer. The air spacer is usually filled by sequential conformal and non-conformal deposition steps. The impact of the thickness of the conformal layer and the sticking probability during non-conformal deposition on the ring oscillator performance is studied here. The air gap, which forms the core of the air spacer, is generated during the non-conformal deposition step. We extract the relative effective permittivity of the air spacer as a function of these two fabrication parameters by solving the Poisson equation to obtain the spacer capacitance. Finally, SPICE model cards are extracted automatically from the TCAD transistor characteristics and the parasitic network is calculated from the full 3D ring oscillator logic cell using a field solver. We apply our framework on two fabrication flows, when the air gap is created before and after the deposition of the first metal contacts layer. We observe that introducing the air gap inside the spacer results in an at-least 15% improvement in the ring oscillator’s performance, when the power is kept constant. Further improvements can be achieved by reducing the conformal layer thickness and increasing the sticking probability by increasing the chamber partial pressure or increasing the process temperature.