Device enhancement using process-strained-Si for sub-100-nm nMOSFET

Abstract

Process-induced strain using a high-tensile contact etch stop layer has demonstrated 18% transconductance and 18% driving current enhancement at a gate length/width of 80 nm/0.6 /spl mu/m for bulk nMOSFETs without degrading the device performance of pMOSFET. A superior current drive at 917 /spl mu/A//spl mu/m for nMOSFET is achieved with 1.7-nm gate oxide, 80-nm gate length, and 1.2-V operation voltage. The gate delay for an inverter ring oscillator is improved up to 13%.