Inverter Prototype Research Articles

In Situ Diagnosis for IGBT Chip Failure in Multichip IGBT Modules Based on a Newly Defined Characteristic Parameter Low-Sensitive to Operation Conditions

To achieve the desired current capability, insulated gate bipolar transistor (IGBT) modules are normally composed of parallel chips. The bond wires fatigue on a certain chip will gradually cause the performance of the power module to degrade, and eventually lead to an unexpected catastrophic failure of the entire system. Therefore, this paper proposes an in-situ diagnosis method for bond wires fatigue in multichip IGBT modules based on a newly defined characteristic parameter. By sensitivity analysis, horizontal comparison and experimental test, the parameter was proven to have the advantages of being safe, low-sensitive to operation conditions and easy to extract. Correspondingly, the online monitoring circuit was designed on the basis of the voltage clamping technology, and further applied on an inverter prototype with 100 A peak current and 10 kHz switching frequency. The results showed that although with large change of junction temperature and load current, the proposed method can accurately diagnose IGBT chip failure by the sudden increase in the amplitude of the parameter. Moreover, the monitoring circuit can be both plug-and-play in the existing inverters and integrated in the gate drive circuit owing to the compact design, which is expected to avoid catastrophic failures of the inverter in field application.

A Quasi-Z-Source Four-Switch Three-Phase Inverter With Null Vector Capability

In this paper, a novel structure for a four-switch three-phase inverter with the ability of creating a null vector is proposed. This structure utilizes a symmetrical quasi-Z-source network and generates zero output voltage during the shoot-through state, which is similar to the null vector in the conventional six- switch inverter. This vector is used for the remaining time for each switching period. This means that the proposed structure has several advantages over the conventional four-switch inverter, in which two active vectors with opposite directions are necessary for synthesizing a null vector. These two vectors increase the switching losses due to the current circulation through these active states. Moreover, the number of switching states increases because of applying two opposite vectors. However, this problem does not exist in the proposed topology. To decrease the output current distortion and to minimize the number of switching events per each cycle, a new switching pattern is proposed, too. Also, fluctuations of the two split capacitors in the dc-link are considered in the closed-loop modulation method, which balances the output voltages and decreases current THD by 0.7%. To validate the proposed topology and the given pulse width modulation approach, its mathematical analyses are given here. Also, simulations and experimental verification have been performed on a 1 kW prototype inverter.

Output Power Computation and Adaptation Strategy of an Electrosurgery Inverter for Reduced Collateral Tissue Damage.

This paper investigates two ways of output-power computation, namely, sparse- and multi-sampling-based methods, to overcome sampling speed limitation and arcing nonlinearity for electrosurgery. Moreover, an impedance-based power adaptation strategy is explored for reduced collateral tissue damage. The efficacy of the proposed power computation and adaptation strategy are experimentally investigated on a gallium-nitride (GaN)-based high-frequency inverter prototype that allows electrosurgery with a 390 kHz output frequency. The sparse-sampling-based method samples output voltage once and current twice per cycle. The achieved power computing errors over 1000 cycles are 1.43 W, 2.54 W, 4.53 W, and 4.89 W when output power varies between 15 W and 45 W. The multi-sampling-based method requires 28 samples of both outputs, and the corresponding errors are 0.02 W, 0.86 W, 1.86 W, and 3.09 W. The collateral tissue damage gauged by average thermal spread is 0.86 mm, 0.43 mm, 1.11 mm, and 0.36 mm for the impedance-based power adaptation against 1.49 mm for conventional electrosurgery. Both power-computation approaches break sampling speed limitations and calculate output power with small errors. However, with arcing nonlinearity presence, the multi-sampling-based method yields better accuracy. The impedance-based power adaptation reduces thermal spreads and diminishes sensor count and cost. This paper exemplifies two novel power-computation ways using low-end industrial-scale processors for biomedical research involving high-frequency and nonlinearly distorted outputs. Additionally, this work is the first to present the original impedance-based power adaptation strategy for reduced collateral damage and it may motivate further interdisciplinary research towards collateral-damage-less electrosurgery.

Space Vector Pulsewidth Modulation Strategy for ANPC-5L Inverter Based on Model Predictive Control

SVPWM strategies for active neutral-point-clamped five-level (ANPC-5L) inverters have multiple control degrees of freedom and control objectives. However, traditional SVPWM strategies are hard to realize optimal control of multiple objectives due to the objectives are coupled with each other. To address this problem, an SVPWM strategy based on model predictive control (MPC) is proposed. In the pulse generation process of the proposed SVPWM, all control degrees of freedom are utilized to achieve optimal control of multiple objectives through MPC. Firstly, voltage vector sequences that meet the requirements of CMV are selected. Then, a cost function is constructed to realize optimal control of the neutral point potential (NPP) and three floating capacitors (FCs) voltage. The proposed strategy has advantages such as high control accuracy and producing low CMV. Finally, the effectiveness of the proposed strategy is validated by a 150kW three-phase ANPC-5L inverter prototype.

Power hardware-in-the-loop testing for multiple inverters with virtual inertia controls

Virtual inertia (VI) control schemes implemented in inverter-based resources (IBRs) present a promising solution for mitigating the absence of inertial response in power systems after the decommissioning of synchronous generators (SGs). The interaction of multiple grid-following (GFL) and grid-forming (GFM) inverters with the power grid demands a thorough understanding, as different control mechanisms can lead to undesired interference that could severely impact the grid’s stability. Power hardware-in-the-loop (PHIL) simulation is a verification technique that effectively bridges the gap between pure simulation and field demonstration. However, the topic of PHIL testing frameworks for multiple inverters equipped with VI control schemes has not been extensively addressed. To address this gap, this study presents a PHIL test framework that enables the verification of the performance and possible interference of multiple hardware inverters. The proposed framework enables the testing of inverters with different rated capacities and control mechanisms under equivalent capacity and control parameter conditions. This framework allows for the testing of various combinations of two inverters, from different manufacturers, to assess their performance and possible interference. The inverter prototypes from different manufacturers will be combined and tested with the proposed PHIL test framework to examine performance and potential interference for all combinations of the two inverters.

Characterization and Mitigation of Conducted Emissions in a SiC Based Three-Level T-Type Motor Drive for Aircraft Propulsion

This paper presents the full-scale high power inverter design considerations that are needed for minimum conducted noise propagation throughout the system. Specifically, system design issues pertaining to high current and high altitude, high switching transients during commutation process, ribbon cables for high-speed signal transmission, strict conducted emissions requirements and motor side bearing/leakage currents are discussed. Based on the underlying deficits for high power motor drives, layout and circuit design methodologies are proposed to tackle such problems, while keeping costs at a bare minimum. Subsequently, modeling and prediction of common-mode (CM) and differential-mode (DM) noise is made possible using accurate lumped inverter and filter models, allowing for a better understanding of the sensitive components contributing to peak CM-DM noise. A high power (211 kW) rated three level T-type inverter prototype is used to demonstrate the viability of the proposed design techniques for reliable system operation and conducted electromagnetic interference (EMI) emissions mitigation.

A regular sampling method based on the immediate mode for improving the stability of inverters

The shadow mode-based regular sampling methods are usually used in the digital control of power inverters, which introduce a control delay of one and a half sampling periods. The control delay affects the closed loop bandwidth and the stability of dc–ac inverters. Recently, regular sampling methods based on the immediate mode is emerging and helpful for reducing the digital control delay. When employing the immediate mode, the induced vertical crossings may arouse the duty-cycle loss and dead-band effect during the modulation process, which deteriorate the normal operation of the inverters. Although the duty-cycle loss can be avoided by forcing the PWM signal to flip at the occurrence of vertical crossings, the introduced dead bands still exist. Thus, this paper investigates the phenomenon of vertical crossings and proposes a control algorithm composed of predicting the occurrence of vertical crossings and compensating the dead-band effect for regular sampling methods based on the immediate mode. Finally, experimental results on a single-phase dc–ac inverter prototype are provided to compare the efficacy of different approaches.

A high efficiency multi-module parallel RF inverter system for plasma induced hydrogen

Hydrogen energy plays an important role in achieving carbon neutralization, and plasma induced hydrogen is an effective production method. One challenge is how to guarantee high efficiency operation with wide power output range of the RF inverter system used to generate the plasma. In this paper, a multi-module parallel topology of a high-frequency inverter is analyzed, in which the power combining network can maintain the soft switching characteristics of the inverter modules. A control method of "ON/OFF + phase shift" is adopted to broaden the output power range of the inverter. The equivalent impedances of different modules are analyzed in detail. A four-module 13.56 MHz high-frequency inverter prototype is built and tested. The results show that the inverter can operate at high efficiency and wide output power range with efficiency improved by at least 5% compared with the traditional parameter design method without considering the effect of paralleled modules.

A ZVS-PWM Scheme for Three-Phase Active-Clamping T-Type Inverters

For increasing power density and other performance of T-type three-level inverters, the soft-switching technique is studied. This article proposes a novel zero-voltage switching (ZVS) PWM scheme for active clamping three-phase T-type inverters, which can realize the ZVS operation of all switches and reduce the switching loss. The proposed ZVS PWM scheme is evolved from discontinuous PWM and modified for the requirements of T-type inverter. It enables all switches, including main switches and auxiliary switches, operate at a fixed frequency. However, a larger current on the power semiconductor devices occurs at 60° zone transition. To suppress this current surge, the carriers used in the ZVS PWM scheme are phase shifted. Finally, the novel ZVS PWM scheme is verified on a 10 kW/150 kHz SiC-based ZVS T-type inverter prototype.

Fixed Switching Frequency Hybrid Modulation With ZVS for Single-Phase Inverter

Soft switching technology is an effective way to reduce the switching loss of the single-phase inverter to improve efficiency. Because of the ease of implementing soft switching, inverter works in boundary conduction mode (BCM) is widely used. On the contrary, BCM causes wide variation in switching frequency and large inductor current ripple. In this article, a fixed switching frequency hybrid modulation method for the inverter is proposed, which can achieve zero-voltage switching without changing the switching frequency and reduce the peak value of inductor current. The modulation achieves good tracking of the output current with different loads by switching mode between the triangular mode and the trapezoidal mode accurately. For implementing modulation, the operation states of the inverter with different conditions are analyzed in detail, the number of operation states is deduced and the state machine about mode switching is summarized. In addition, a single-phase inverter prototype is designed to verify the feasibility and effectiveness of the proposed modulation. Compared with BCM, the efficiency of the inverter at both light load and full load is increased.

Dual Boost Five-Level Switched-Capacitor Inverter With Common Ground

This brief presents a five-level common ground type (5L-CGT) inverter topology with double voltage boosting. This topology uses only eight switches, two capacitors that can be charged equal to the input source. The advantageous feature of this topology is the CGT configuration between the input source and output load, which ensures minimal common-mode voltage and leakage current. A detailed analysis is done to select and size capacitors, along with quasi-soft charging to minimize the charging current ripples across the capacitors. The performance of the proposed 5L-CGT inverter is tested for inductive load, varying the modulation index/load/input voltage under experimental test conditions. A detailed comparison is done with the existing state-of-art that shows the merits of the proposed topology in terms of equal voltage stress across the capacitor with voltage boost. The power loss analysis for the inverter is carried out using PLECS with efficiency to be 97.20%, and the experimental efficiency is found to be 96.54% for the 900W inverter prototype.

Modified Passivity-Based Control for LCL-Filtered Grid-Tied Inverter with Output Admittance Reshaping

As a nonlinear control method, the Euler–Lagrange- (EL-) based passivity-based control (PBC) has been studied for grid-tied converters based on energy function to achieve better performance. However, the EL-based PBC method is dependent on an accurate mathematical model. In the traditional EL-based PBC research for LCL-filtered grid-tied inverter, the effect of the digital control delay is rarely considered and the stability under the grid impedance uncertainties is not discussed, especially in the capacitive grid or complex weak grid. To address these concerns, this study proposes a modified EL-based PBC method based on the output admittance reshaping for LCL-filtered grid-tied inverters. The system’ passive region is expanded by adding capacitor current feedback loop up to the Nyquist frequency. The potential resonance is thus eliminated irrespective of the grid impedance. Additionally, the stable region and control parameters design methods of the modified EL-based PBC method with inverter-side control are also carried out. To verify the correctness of the theoretical analysis, both simulation and experimental results are investigated from a 3 kW grid-tied inverter prototype.

DE SHM Based Harmonic Minimization for Modified PUC 15 Level Inverter

A 15-level Modified Packed U-cell (MPUC) Inverter is investigated in this study, and a Selective Harmonic Mitigation (SHM) method is used to reduce and eliminate several harmonic components on the output voltage, resulting in a lower Total Harmonic Distortion (THD) factor. The proposed MPUC-15 inverter can provide a 15-level output with only eight switches, making it the most compact inverter to date. In order to achieve the 15-level output, the inverter's dc link voltage is kept in the ratio of 1/4:3/4:1. A detailed explanation of the PMUC15 inverter's operation with various switching states is provided. The MPUC15 inverter allows for the elimination of more harmonics. However, the equation of the harmonic becomes more complex as additional switching angles emerge in the harmonic equations, which are difficult to solve using typical linear optimization methods. The SHE-PWM equations for a 15-level inverter are created and solved using Deferential Evaluation (DE) with a variable modulation index, a current optimization method. The reported output THD has been less than 5%, and angles for various modulation indexes have been compiled and provided in tabular format. The inverter prototype is built in MATLAB®/Simulink, with a Typhoon HIL SCADA setup for testing the results of the DE algorithm.

Low Frequency Current Ripple Suppression for Two-Stage Single-Phase Inverter Based on Impedance Editing

The instantaneous output power of the two-stage single-phase inverter pulsates at double-line frequency, generating a large amount of second harmonic current (SHC) in the front-end dc-dc converter and input dc source. The SHC is harmful to the system performance. To address the issue, a control strategy based on port-impedance editing, where inductor current feedforward (ICFF) and bus voltage feedforward paths are employed, is proposed to reduce the low frequency ripple in the article. Due to only bandpass filter employed in each feedforward path, the proposed control scheme is relatively easy to be implemented. Under the control strategy, the dc-bus port-impedance of dc-dc converter is increased rapidly at double-line frequency, while staying low impedance for other frequencies. What is more, different ICFF paths are taken into insight to obtain optimized path. Meanwhile, the small signal model of front-end dc-dc converter is established and the design principle of key parameters is provided for the derived control strategy. Furthermore, the dynamic response with bandwidth limitation is also discussed in this article. Finally, a two-stage single-phase inverter prototype was fabricated and tested. The experimental results verify the performance of the proposed strategy with SHC reduction.

Output DM EMI Noise Prediction for MHz TCM-Based Single Phase Inverter

Conventional fast Fourier transform analysis is limited in conducted electromagnetic interference (EMI) prediction for triangle current mode (TCM) based converters. Several prediction strategies based on EMI receiver modeling have been published for this issue, but the prediction range was below 1 MHz. Such a narrow frequency range cannot meet the demands of EMI prediction for MHz converter. In this article, a more accurate differential mode (DM) EMI prediction is proposed for MHz TCM-based single-phase inverter. The accurate drain-to-source voltage model considering the TCM resonant transition is established for different TCM-derived strategies at first. Passive components of the propagation path are also modeled with the measured impedance for more accurate transfer gain. An improved envelope detector model of the EMI receiver is proposed for an accurate quasi-peak spectrum. The prediction range can be extended to 5 MHz. Moreover, the EMI of TCM, hybrid triangle current mode, and sinusoidal triangle current mode are analyzed and compared with the established prediction strategy. The worst spectrum can be determined, and the DM filter can be designed without repetitive measurements. Finally, A 500 W MHz single-phase inverter prototype is built, and the evaluation of the measured conducted EMI spectrum and the EMI filter design can verify the theoretical analysis.

A New Type of Three-Phase Asymmetric-LCL Power Filter for Grid-Tied Voltage Source Inverter With Step-Up Transformer

Power filters have been widely used to suppress switching harmonics caused by the modulation of grid-connected inverters. In order to save the total inductance and cost and reduce the volume, different power filters were proposed for the three-phase three-wire grid-connected voltage source inverter. However, in industrial applications, due to the consideration of production cost, the difficulties caused by the deviation of actual parameters have to be addressed. In this article, we propose a new three-phase three-wire power filter with a simple structure, almost the smallest total inductance, and strong resistance to the adverse effects of parameter shifts. The parameters of the proposed filter and the design of the grid-connected system controller are introduced in detail. When studying the influence of parameter offset, a comparison between different types of notch power filters is also given. Simulation and experimental results on a 380 V/50 Hz/6 kW three-phase inverter prototype verify the performance of the proposed power filter.

A Self-Voltage Balanced Hybrid Three-Level MV Inverter Using 3.3-kV SiC MOSFET Module With False-Trigger-Proof Design

This article presents a self-voltage balanced three-level (3L) active-neutral-point-clamped (ANPC) medium-voltage (MV) inverter. Two switches of this inverter operate at high frequency (HF), while four switches operate at low frequency (LF), which is suitable to be implemented with hybrid “Si IGBTs + SiC MOSFETs” for MV applications. A 3.3-kV SiC MOSFET power module with low parasitic packaging is applied as HF switches, and the dc-link capacitor voltages can be self-balanced through periodic charging/discharging processes with a small decoupling capacitor. However, the inrush current occurs during voltage balancing processes, resulting in the false trigger of desat protection for LF switches. In this article, the mechanism of inrush current during voltage balancing processes is analyzed and a 3L gate driving method is proposed for LF switches to solve the false-triggering issue and improve the inrush energy loss distribution. In addition, high dv/dt of SiC switching transients may cause the false-triggering issue of HF switches, and desat protection design equations are therefore derived for this 3.3-kV SiC MOSFET power module to achieve a fast (< 440 ns) short-circuit response and maintain a good noise immunity to high dv/dt. A 4-kV dc, 40-kVA inverter prototype is built in the laboratory and the experimental results are provided to verify the proposed methods.

Reducing Circling Currents in a VHF Class Φ2 Inverter Based on a Fully Analytical Loss Model

This paper proposes a fully analytical loss model to reduce circling currents and improve the power efficiency of a class Φ2 inverter. Firstly, analytical expression of the switching node voltage is derived by analyzing its harmonic components. Based on the result, the power switch is modeled as a voltage source, where the circuit is simplified to a linear network and analytical expressions of branch currents are solved. Secondly, root mean square (RMS) values of branch currents and component losses are calculated to form the analytical loss model for a Φ2 inverter. The influence of circuit parameters on the circling current and power efficiency are thoroughly analyzed, which derives optimal design constraints to reduce circling currents of a class Φ2 inverter. Furthermore, detailed design guidance and equations are provided to calculate circuit parameters of a class Φ2 inverter, which reduces its circling currents and improves overall power efficiency. Finally, a class Φ2 inverter prototype is built, and experimental results demonstrate a 7% efficiency improvement compared to conventional empirical design methods.

Performance evaluation of grid-following and grid-forming inverters on frequency stability in low-inertia power systems by power hardware-in-the-loop testing

Developing advanced control functions for inverter-based resources (IBRs) to replace the inertial response of retiring synchronous generators (SGs) is progressing rapidly. Although various control mechanisms have been proposed for grid-following (GFL) inverters and grid-forming (GFM) inverters, the comprehensive comparison of their performance in contributing to grid stabilization based on hardware testings has not been studied well. This paper performs power hardware-in-the-loop (PHIL) testing for multiple inverter prototypes from different manufacturers and compares their performance concerning the difference in inverter types, control methods, and IBR penetration conditions in the power system. It also tests the possible interference between islanding detection methods (IDMs) and frequency control capabilities of GFL and GFM inverters.

A zero‐current‐transition soft‐switching technique for T‐type NPC three‐level inverter

Based on the commutation property of the T-type neutral point clamped (T-NPC) three-level inverter, a novel zero-current-transition (ZCT) soft-switching topology is proposed. The proposed topology employs only two auxiliary switches and one inductor and capacitor (LC) resonant tank on each phase leg. The commutation process of the soft-switching technique is analyzed. The results show that all switches on main leg and auxiliary leg can achieve soft commutation without changing pulse width modulation (PWM) strategy. The control family of T-NPC three-level ZCT soft-switching topology are analyzed respectively, and then the resonant tank and timing schemes of different modes are given. Using two auxiliary switches in resonance can produce greater resonance current due to the combination of external excitation sources, which is more conducive to realize the soft-switching commutation of the main switch. At last, a half bridge prototype of T-NPC three-level inverter is built. The influence of equivalent internal resistance of power switches, diode reverse recovery and stray inductance for soft commutation is analyzed. The advantages of ZCT soft-switching technology is verified.