Interposer Package Research Articles

Market & Technology Trends for the Fanout and 2.5D/3D Packaging Technology

The industry is seeking alternatives to design and manufacture the latest Systems on Chips (SoCs) using System in Package (SiP) and chiplet-based approaches by leveraging Advanced Packaging to mix both the latest and mature nodes. In this regard, fan-out & 2.5D/3D packaging has emerged as the key technology choice for the heterogeneous integration. Fan-out packaging is growing at > 15% CAGR to reach ~ $3.4B by 2026. Key applications driving the fan-out are mobile, HPC, networking and automotive. Core-FO is expected to see slow growth and remain flat as many device requirements can be fulfilled by fan-in WLCSP and more reliable FCCSP configurations. HD-FO is mainly driven by application processor for high end phones and the growth will remain healthy. UHD-FO (Ultra High Density), such as FoCoS & InFO-OS, is expected to gain more traction in networking and HPC applications. With rise of the need for heterogeneous integration, 3D stacked packaging is coming at the forefront of advanced packaging arena as Moore’s law slows down due to increased cost of Si transistor scaling. 3D stacked packages are expected to grow at ~24% CAGR reaching $7.4B revenue by 2026. 3D stacked packages include SoC (System on Chip), active interposer packages such as Foveros and Co- EMIB, 3D NAND, 3DS, HBM, and Stacked CIS packages.

On the optimization of molding warpage for wafer-level glass interposer packaging

On the optimization of molding warpage for wafer-level glass interposer packaging

Time-resolved Spectroscopy of Glass Ablation during Micro-via Processing using 248 nm Excimer Laser for Semiconductor Interposer Packaging

Time-resolved Spectroscopy of Glass Ablation during Micro-via Processing using 248 nm Excimer Laser for Semiconductor Interposer Packaging

A mm-Wave 5G System Architecture With Enhanced-Gain Antenna Solution

A millimeter-wave (mm-wave) system architecture with enhanced-gain antenna solution is proposed for fifth-generation (5G) wireless communications. To enhance the antenna gain, the surface wave currents are converted to constructive far-field radiations through a novel two-stage metallic and dielectric rings. By applying low-profile dielectric ring, the electric near-field distributions of the grounded quarter-wavelength metallic ring are modified to create radiation apertures with appropriate polarization and orientation. The mutual coupling between transmit/receive antennas and cross polarizations is reduced by 7 and 5 dB, respectively, and the gain is enhanced over 4 dB. Low-loss mm-wave transitions are implemented in a standard FR-4 printed circuit board and in an interposer substrate to integrate the active antenna with the rest of the wireless system on a compact universal serial bus (USB)-interface platform. To evaluate the interposer package and define the output power of the embedded 60-GHz RF IC, an evaluation module with a standard WR-15 waveguide interface is designed and implemented. A prototype of the architecture, which is entirely realized using low-cost organic substrates, is presented and evaluated by experiments. Excellent correlations are achieved between simulations and measurements, demonstrating more than 25 dBm of equivalent isotropically radiated power (EIRP) over the unlicensed 60-GHz frequency band.

Methods to Enable Fault Isolation on 2.5D Molded Interposer Packages

Abstract This article discusses the failure analysis challenges associated with large overmolded 2.5D packages and explains how laser decapsulation followed by microwave-induced plasma (MIP) spot etching removes overmold while keeping everything else intact. It also describes a defect isolation procedure in which the sample is analyzed in a large chamber environmental SEM with its ball grid array directly wired to an EBAC amplifier.

Analysis on Signal and Power Integrity of 2.3D Structure Organic Package

Abstract Heterogeneous packaging is one of the advanced technologies. Especially for high-end applications such as data center server, HPC and Artificial-Intelligence (AI), High-Bandwidth Memory (HBM) integration is a key and strongly required. As we know, the 2.5D silicon interposer packaging is an expanded solution for HBM interconnections. However, we developed 2.1D high density organic package called i-THOP® (integrated-Thin film High density Organic Package) to take advantages of an organic solution. Furthermore, we are now focusing on 2.3D i-THOP® to have more benefits in the manufacturing. The 2.3D structure consists of two substrates. One is a thin i-THOP® interposer, the other one is a conventional build-up (BU) substrate. These two substrates are combined as the interposer placed onto the build-up substrate. In this paper, the electrical properties of 2.3D i-THOP® are studied to confirm the possibility of the 2.3D structure organic packages from the perspective of signal and power integrity. Firstly, the signal integrity between two devices is simulated, comparing the differences between i-THOP® and the 2.5D silicon interposer. Secondly, the signal integrity in die-to-substrate vertical interconnection is simulated, comparing between 2.1D, 2.3D i-THOP® and the 2.5D silicon interposer. Finally, as for the power delivery point of view, power distribution network (PDN) impedance is compared between 2.1D and 2.3D i-THOP®.

Silicon Interposer Package for MMIC Heterogeneous Integration Based on Gold/Solder Ball Flip-Chip Technique

Novel silicon interposer package solution is proposed for monolithic microwave integrated circuit (MMIC) heterogeneous integration. The GaAs/InP MMICs are integrated into the high-resistance silicon interposer by the gold ball flip-chip technique. Then, the whole silicon interposer with the heterogeneous integrated MMICs is assembled to the printed circuit board (PCB) top layer by the solder ball flip-chip technique. In this proposed silicon interposer package solution, the microwave signal can be transmitted from the PCB to the heterogeneous integrated MMICs without deterioration. For the experimental study, two low-noise amplifier (LNA) MMICs are cascaded to integrate within the high-resistance silicon interposer, and the measured results show that the proposed package solution can succeed in integrating MMICs for system-on-package applications.

Superior decoupling capacitor for three-dimensional LSI with ultrawide communication bus

The superior noise reduction performance of an in-stack decoupling capacitor (DECAP) is demonstrated. A three-tier stacked demonstrator is manufactured with an ultrawide data bus that connects a top memory chip and a bottom logic chip. An in-stack evaluation circuitry on a middle tier (Si interposer) captures voltage variation waveforms during chip-to-chip data communication. In-stack DECAPs in arrays on a Si interposer and discrete ceramic capacitors on an organic interposer of a ball-grid array package are compared. Silicon measurements with an in-stack noise monitoring technique show that the DECAPs on the Si interposer more locally shunt out the AC components of power supply current over a wider frequency range than the capacitors on the package interposer.

From Chip to Cloud: Optical Interconnects in Engineered Systems

The high-performance server compute landscape is changing. The traditional model of building general-purpose enterprise compute boxes that end-users can configure with storage and networking to assemble their desired compute environments, has evolved to purpose-built systems optimized for specific applications. This tight integration of hardware and software components together with high-density midboard optical modules and an optical backplane allows for unprecedented levels of switching and compute efficiencies and has fueled the penetration of optical interconnects deep “inside the box,” particularly for switch scale-up. We briefly review earlier 40 G/port switching systems based on active optical cables, and present our newest system: An all-optically-interconnected 100 G/port 8.2 Tb/s InfiniBand packet switch ASIC with 41 ports running 100 Gb/s per port interconnected by 12-channel midboard optical transceivers with 25 Gb/s per channel per direction of optical I/O. Using a blind-mate optical backplane, these components enable systems with up to 50 Tb/s bandwidth in a 2U standard rack mount configuration with industry-leading density, efficiency, and latency. For even tighter co-integration of optical interconnects with switch and processor ASICs, we discuss photonic multichip module and interposer packaging technologies that will further improve system energy efficiencies and overcome impending system I/O bottlenecks.

Prediction of deformation during manufacturing processes of silicon interposer package with TSVs

The purpose of this paper is to analyze and predict the thermal deformation of the through silicon via (TSV) interposer package during the manufacturing process and to perform a parametric study to minimize the warpage and thermal stress. Samples were selected during different stages of the assembly to observe the thermal behavior change. The Digital Image Correlation (DIC) technique was employed to measure the real-time deformation of the samples under thermal loading. To make a finite element analysis (FEA) model, material properties were characterized by DIC and Dynamic Mechanical Analysis (DMA). Based on the material properties and deformation data determined by experiments, a validated FEA model was established. To reduce the modeling complexity and the computing time in the simulation, the C4/underfill layer, micro bump/underfill layer, and TSV interposer were assumed to be isotropic. The most effective material properties for the isotropic layers were calculated by the composite theory. Also, the simulation followed the sequential manufacturing processes to investigate the thermal deformation change of each step and to obtain a more accurate prediction result. The thermal behavior from simulation showed a good agreement with the experimental result and this verified simulation model was implemented for the parametric study. A series of simulations were carried out to minimize the package warpage. To avoid any delamination failures, the stresses at the interface between the interposer and underfill were also evaluated. The effect of the interposer underfill material property, substrate material property, substrate thickness, and TSV density (Cu volume fraction) in the interposer were studied. It has been shown that low modulus, low coefficient of thermal expansion (CTE), and high glass transition temperature (Tg) underfill, as well as a low modulus and low CTE substrate can mitigate the package warpage and stress development at the interface between interposer and underfill. Also, a larger Cu volume TSV interposer and thick substrate can lessen the warpage of the package and stress at the interface.

Design and Demonstration of Fine-Pitch and High-Speed Redistribution Layers for Panel-Based Glass Interposers at 40-μm Bump Pitch

This article analyzes redistribution layer (RDL) technologies needed for 2.5-dimensional (2.5-D) die integration on thin glass interposers and developed using low-cost processes. The design, fabrication, and characterization of a four-metal layer RDL buildup required for wide input/output (I/O) routing at 40-μm bump pitch and a two-metal layer RDL buildup fabricated directly on glass for high-speed, off-package signaling are described. Such RDL technologies are targeted at 2.5-D glass interposer packages to achieve up to 1 Tb/s die-to-die bandwidth and off-interposer data rates > 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5-D and 3-D interposers require fine-line lithography beyond the capabilities of current organic package substrates. High electrical loss and high cost are characteristic of silicon interposers fabricated using back-end-of-line (BEOL) processes that can achieve RDL wiring densities required for 2.5-D die integration. Organic interposers with high wiring densities have also been demonstrated using a single-sided, thin-film process. This article goes beyond silicon and organic interposers in demonstrating fine-pitch RDL on glass interposers fabricated by low-cost, double-side, and panel-scalable processes. The high modulus and smooth surface of glass help to achieve lithographic pitch close to that of silicon. Furthermore, the low permittivity and low loss tangent of glass reduce dielectric losses, thus improving high-speed signal propagation. A semiadditive process flow and projection excimer laser ablation were used to fabricate four-metal layer (2 + 0 + 2) fine-pitch RDL and two-metal layer RDL directly on glass. A minimum of 3 μm lithography and 20 μm microvia pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.

Design and Demonstration of Power Delivery Networks With Effective Resonance Suppression in Double-Sided 3-D Glass Interposer Packages

Ultrathin 3-D glass interposers with through-package vias at the same pitch as through-silicon vias (TSVs) have been proposed as a simpler and cheaper alternative to the direct 3-D stacking of logic and memory devices. Such 3-D interposers provide wide-I/O channels for high signal bandwidth (BW) between the logic device on one side of the interposer and memory stack on the other side, without the use of complex TSVs in the logic die. However, this configuration introduces power delivery design challenges due to resonance from: 1) the low-loss property of the glass substrate and 2) the parasitic inductance due to additional length from lateral power delivery path. This paper presents for the first time, the design and demonstration of power delivery networks (PDNs) in 30- $\mu \text{m}$ thin, 3-D double-sided glass interposers, by suppressing the noise from mode resonances. The self-impedance of the 3-D glass interposer PDN was simulated using electromagnetic solvers, including printed-wiring-board and chip-level models. The 3-D PDN was compared with that of the 2-D glass packages having fully populated ball grid array connections. The resonance mechanism for each configuration was studied in detail, and the corresponding PDN loop inductances were evaluated. High impedance peaks in addition to the 2-D PDN were observed at high frequencies (near 7.3 GHz) in the 3-D interposer structure due to the increased inductances from lateral power delivery. This paper proposes and evaluates three important resonance suppression techniques based on: 1) 3-D interposer die configuration; 2) the selection and placement of decoupling capacitors; and 3) 3-D interposer package power and ground stack-up. Two-metal and four-metal layer test vehicles were fabricated on 30- and 100- $\mu \text{m}$ thick panel-based glass substrates, respectively, to validate the modeling and analysis of the proposed approach. The PDN test structures were characterized up to 20 GHz for plane resonances and network impedances, with good model-to-hardware correlation. The results in this paper suggest that the ultrathin 3-D interposer PDN structure can be effectively designed to meet the target impedance guidelines for high-BW applications, providing a compelling alternative to 3-D-IC stacking with the TSVs.

System level IC packaging - Integration of Key Technologies: TSVs, Interposers, and Advanced IC Packaging

New system level IC package integration requires a flexible assembly portfolio. A review of current wafer scale processing and assembly solutions and new development directions is warranted. 2.5D TSV System level IC packaging is not new, but the performance levels that are being attained today with memory stacking, interposers, advanced silicon nodes and advanced packaging are new and are unparalleled. Several key technologies have come together to create this bold shift to higher performance. The Thru-Silicon Via (TSV) technology has been foremost, whether in the interposer, memory or logic devices, the importance of the this electrical pass through connection in silicon cannot be overstated. To commercialize the TSV package constructions, IC packaging technology had to be developed to permit its use. This included TSV reveal on TSV-bearing interposers, new ways of controlling warpage due to the presence of large x-y interposers, new functional IC bumping technologies and attachment methods. This portfolio of advanced technologies are then combined to provide package constructions that are increasingly compelling as a result of the higher electrical performance attained, while at the same time minimizing unwanted die to die interface power requirements. 2.5D TSV bearing products have enabled an array of multi-die products and have a significant role to play in the semiconductor industry going forward. Examples include new economics for SOC-splitting, and especially for combinations of logic and high speed memory (HBM), with performance levels heretofore unachievable. With fine line damascene Cu Back End of Line (BEOL) typical of a 65nm Cu backend, the signal routing resources available for multi-die implementation is unparalleled. Functionally, the TSV is required to provide a suitable power deliver network (PDN), and to enable off-package IO signaling. 3D TSV The COS Chip last is a proven approach for 2.5D TSV packages and is already in early production. This process flow is also being developed for 3D packages applications as well. New technologies being developed for 3D applications include new UF processing technologies that will be used to extend this technology to a 2-die stack with the same die size top and bottom, as well as 50 um large die silicon handling. These will include logic on logic combinations and memory on logic configurations, as well as stacked memory offerings. SLIMTM Amkor's most advanced integrated modular based package development program is for SLIMTM (Silicon-Less Integrated Module). The roots of SLIM innovation were forged during the 2.5D TSV-bearing interposer package development. SLIMTM attempts to retain all the best features of a 2.5D TSV interposer approach, but without bulk silicon for TSVs. The objective of SLIM is to retain the very strong signal routing capability afforded by the damascene BEOL, and provide that benefit without the requirement for a TSV. This can enable a lower total cost than the 2.5D interposers, and some specific electrical performance improvements as well. The primary mechanical feature of the SLIMTM construction is the lack of TSVs. For SLIM, the TSV is not in the electrical path from the top die to the C4, providing electrical benefits. In the case of SLIM the bulk silicon has been removed from the interposer, so that only the thin-film metal and dielectric layers present in the BEOL construction are retained. Connection to the BEOL metal stack is made directly using thin film techniques developed for 2.5D TSV. The end result is a very thin package, with signal routing resources on par with the 2.5D interposer, and without bulk silicon or a TSV. This can have electrical signaling advantage, especially for very high speed IO off package signals which avoid bulk silicon dielectric losses that can be significant above 20 Gigabit/sec. The process flow developed for SLIM is essentially a truncated version of the 2.5D production line. Key steps not required are CVD deposition of inorganic dielectrics and CMP processing. In summary, the final system package construction can be derived with different process approaches as previously discussed, each with their own particular benefits. Amkor continues in its commitment to the development of these critical process modules to enable customers to achieve their ultimate system-in-module product designs.

Design and Demonstration of 40 micron Bump Pitch Multi-layer RDL on Panel-based Glass Interposers

This paper describes the design, fabrication, and characterization of a two-metal layer RDL structure at 40 um pitch on thin glass interposers. Such an RDL structure is targeted at 2.5D glass interposer packages to achieve up to 1 TB/s die-to-die bandwidth and off-interposer data rates greater than 400 Gb/s, driven by consumer demand of online services for mobile devices. Advanced packaging architectures including 2.5D and 3D interposers require fine line lithography beyond the capabilities of current organic package substrates. Although silicon interposers fabricated using back-end-of-line processes can achieve these RDL wiring densities, they suffer from high electrical loss and high cost. Organic interposers with high wiring densities have also been demonstrated recently using a single sided thin film process. This paper goes beyond silicon and organic interposers in demonstrating fine pitch RDL on glass interposers fabricated by low cost, double sided, and panel-scalable processes. The high modulus and smooth surface of glass helps to achieve lithographic pitch close to that of silicon. Furthermore, the low loss tangent of glass helps in reducing dielectric losses, thus improving high-speed signal propagation. A semi-additive process flow and projection excimer laser ablation was used to fabricate two-metal layer RDL structures and bare glass RDL layers. A minimum of 3 um lithography and 20 um mico-via pitch was achieved. High-frequency characterization of these RDL structures demonstrated single-ended insertion losses of −0.097 dB/mm at f = 1 GHz and differential insertion losses of −0.05 dB/mm at f = 14 GHz.

Electrical Characterization of Test Sockets With Novel Contactors

Novel spring contactors were designed and characterized for wafer-level interposer and high-speed package test system applications, especially for wafer-level packages. These contactors can be used as replacement for vertical wafer probes as well as test sockets used in the final test. The contactor pin consists of a plunger section made of beryllium copper and a plated helical stainless steel spring wire. It is 5 mm in uncompressed total length, including the plunger and the spring. The overall diameter of the spring wire section was 0.51 mm. The design of the contactor is much simpler and more scalable than that of traditional spring pins called Pogo pins used in package tests. A test socket containing 36 contactor pins was constructed for tests and measurements. The experimental characterization shows -1-dB bandwidth of 3.73 GHz for 0.8-mm pitch, measured by the direct contact method. This experimental result correlates well with the simulated results. The rise time was 82 ps as measured by TDR, and the propagation delay was 23 ps. The electrical conduction path is through the pin and the spring, making it a reliable contact. However, the electrical path is known to be through the barrel, not the spring for the regular spring pins.

FEM Analysis on Warpage and Stress at the Micro Joint of Multiple Chip Stacking

Flip chip plastic ball grid array (FCPBGA) utilizing an interposer for multiple chip stacks, so called 2.5D or 3D package, is gaining prominence in order to achieve the next generation high performance computing. The multi-tier stacking of Si chip, Si interposer and organic substrate induces complicated warpage behavior and stress at the micro joints during the joining process. The authors studied warpage behavior and thermo-mechanical stress of multiple chip stacks on Si interposer package with different thickness of top chip, different thickness of Si interposer, different middle chip stacks and different metallurgy of micro joints after joining of stacked chips on the interposer using finite element method (FEM). Thicker stacked Si chips and thicker Si interposer showed higher von Mises stress at chip-to-interposer joint. Comparing SnAg joint and CuSn joint, CuSn joint always shows higher stress than SnAg joint because of its higher elastic modulus.

3D Integration of System-in-Package (SiP): Toward SiP-Interposer-SiP for High-End Electronics

The demand for high-performance, lightweight, portable computing power is driving the industry toward 3D integration to meet the demands of higher functionality in ever smaller packages. To accomplish this, new packaging needs to be able to integrate multiple substrates, multiple dies with greater function, higher I/O counts, smaller pitches, and greater heat densities, while being pushed into smaller and smaller footprints. The approaches explored in this paper include eliminating active chip packages by directly attaching the chip to the System-in-Package (SiP) with flip chip technology. Additionally, the area devoted to passive components can be greatly reduced by embedding many of the capacitors and resistors. In some instances, the connector systems that were consuming large amounts of space in the traditional Printed Wiring Board (PWB) assembly can be reduced with a small pitch connector system. This PWB assembly can then be transformed into a much smaller SiP with the full surface area on both sides of the package effectively utilized by active and passive components. The miniaturized SiP with its reduced package size and demand for passives requires a high wireability package with embedded passives and excellent communication from top to bottom. In the present study, we also report novel 3D “Package Interposer Package” (PIP) solution for combining multiple SiP substrates into a single package. A variety of interposer structures were used to fabricate SiP-Interposer-SiP modules. Electrical connections were formed during reflow using a tin-lead eutectic solder paste. Interconnection among substrates (packages) in the stack was achieved using interposers. Plated through holes in the interposers, formed by laser or mechanical drilling and having diameters ranging from 50 m to 250 m, were filled with an electrically conductive adhesive and cured. The adhesive-filled and cured interposers were reflowed with circuitized substrates to produce a PIP structure. In summary, the present work describes an integrated approach to develop 3D PIP solutions on various SiP configurations.

Low-Cost Thin Glass Interposers as a Superior Alternative to Silicon and Organic Interposers for Packaging of 3-D ICs

Interconnecting integrated circuits (ICs) and 3-D-ICs to the system board (printed circuit board) are currently achieved using organic or silicon-based interposers. Organic interposers face several challenges in packaging 2-D and 3-D-ICs beyond the 32-nm node, primarily due to their poor dimensional stability and coefficient of thermal expansion (CTE) mismatch to silicon. Silicon interposers made with back-end of line wafer processes can achieve the required wiring and I/O density, but their high-cost limit them to high-performance applications. Glass is proposed as a superior alternative to organic and silicon-based interposers for packaging of future ICs and 3-D-ICs with highest I/Os at lowest cost. This paper presents for the first time a novel thin and large panel glass interposer capable of scaling to 700 mm and larger panels with potential for significant cost reduction over interposers made on 200-mm or 300-mm wafers. The formation of small through vias at high speed has been the biggest technical barrier for the adoption of glass as an interposer and system substrate; and this paper describes pioneering research in via-formation in thin glass substrates, using a novel “polymer-on-glass” approach. Electrical modeling and design of through package vias (TPVs) in glass is discussed in detail, and the feasibility of 50-μm pitch TPVs in 180-μm thin glass substrates has been demonstrated. The excellent surface finish and low CTE of glass leads to increased I/O density, and increased functionality per unit area leading to system miniaturization.

TSV Developments

Abstract The pace of development for 2.5-D packaging solutions appears to be accelerating as the timeline for the adoption of 3D through-silicon via (TSV) technology continues to slide. This column discusses the latest advancements in 2.5-D or interposer packaging technology and the growing number of applications.

Silicon Interposer Reliability Optimization through Process-Oriented Stress Modeling

ABSTRACTA process-oriented stress modeling methodology is developed to investigate the stress evolution during the silicon interposer packaging process. An FEM based 3D TCAD simulator is used to perform the process steps to construct the silicon interposer stack in sequential order. These steps include TSV fabrication for passive silicon interposer, micro-bumping and reflow process for integrating active dies and passive interposer, C4-bumping and reflow for interposer BT-substrate stacking, and epoxy mold curing for interposer encapsulation. Stress simulations are carried out for each process step to obtain accurate stress evolution history. To resolve micron features within millimeter structures, the modeling strategy employs symmetry conditions, and equivalent materials for regions away from structure features of interest. The detailed structure includes 3x3 arrays of microbumps, TSV arrays, and C4-bumps with multiple material layers at the stack corner. Important design parameters include interposer thickness and edge clearance. For different silicon interposer configurations critical stresses in the outmost microbump and C4-bump are analyzed and compared. The reliability implications are discussed.