Interpoly Dielectric Research Articles

High quality interpoly dielectrics deposited on the nitrided-polysilicon for nonvolatile memory devices

High quality interpoly dielectrics have been fabricated by using NH/sub 3/ and N/sub 2/O nitridation on polysilicon and deposition of tetra-ethyl-ortho-silicate (TEOS) oxide with N/sub 2/O annealing. The surface roughness of polysilicon is improved and the value of weak bonds is reduced due to nitrogen incorporation at the interface, which improves the integrity of interpoly dielectrics. The improvements include a higher barrier height, breakdown strength, and charge-to-breakdown, and a lower leakage current and charge trapping rate than counterparts. It is found that this method can simultaneously improve both charge-to-breakdown (up to 20 C/cm/sup 2/) and electric breakdown field (up to 17 MV/cm).

High quality interpoly-oxynitride grown by NH/sub 3/ nitridation and N/sub 2/O RTA treatment

In this letter, a method to grow high quality interpolysilicon-oxynitride (interpoly-oxynitride) film is proposed. Samples, nitridized by NH/sub 3/ with additional N/sub 2/O annealing and CVD TEOS deposited on poly-oxynitride (poly-I) with RTA N/sub 2/O oxidation, show excellent electrical properties in terms of very high electric breakdown field, low leakage current, high charge to breakdown, and low electron trapping rate. This novel film is a good candidate for an interpoly dielectric of future high density EEPROM and flash memory devices.

Highly reliable ECR N2O-plasma polyoxide grown on heavily phosphorus-doped polysilicon films

Reliability of polyoxide grown by electron cyclotron resonance (ECR) N2O-plasma on heavily phosphorus-doped polysilicon has been investigated for the interpoly dielectrics (IPDs) of nonvolatile memories (NVMs). ECR N2O-plasma polyoxide grown on polysilicon with phosphorus of 1 × 1021 cm−3 exhibits a significantly high breakdown field of 10 MV/cm and low electron trapping rate of 0.5 V, which are regardless of phosphorus concentration. The improvements are attributed to the smooth polyoxide/polysilicon interface, low phosphorus concentration, and nitrogen-rich layer with strong silicon-nitrogen bonds at the polyoxide/polysilicon interface.

Impact of Floating Gate Dopant Concentration and Interpoly Dielectric Processing on Tunnel Dielectric Reliability

The influence of gate dopant concentration and thermal budget on the reliability of tunnel dielectric films was studied. Metal oxide semiconductor (MOS) capacitors were furnace annealed after gate formation, floating gate devices were fabricated with interpoly dielectric films either grown by furnace oxidation or deposited by rapid thermal chemical vapor deposition (RTCVD); the latter process is associated with a much lower thermal budget. Ion implanted amorphous silicon was employed for the gate electrodes of the MOS capacitors and for the floating gate layers of the memory devices. The reliability of the dielectrics was evaluated under a constant current stress, and the cycling endurance of the floating gate devices was examined. It was found that tap generation and charge trapping increase with increasing annealing time and increasing dopant concentration, while charge to breakdown (Qbd) decreases with increasing annealing time. The cycling endurance plot for the floating gate devices revealed little distortion of the threshold voltage window for devices with the low thermal budget RTCVD interpoly dielectric film. Based on this study, a low thermal budget process is preferable for the formation of the interpoly dielectric.

Effect of Bottom Polysilicon Doping on the Reliability of Interpoly Oxide Grown Using Electron Cyclotron Resonance N2O-Plasma

The Effects of the bottom polysilicon doping on the reliability of polyoxides grown using electron cyclotron resonance (ECR) N2O-plasma have been investigated for the interpoly dielectrics (IPDs) of nonvolatile memories (NVMs). In situ doped polysilicon films have a smooth surface. ECR N2O-plasma polyoxide on in situ doped polysilicon has a lower leakage current and a higher breakdown field, furthermore, a lower electron trapping rate and a larger charge-to-breakdown (Qbd) up to 10 C/cm2, which is comparable to the electrical properties of ONO IPD. This is mainly attributed not only to a nitrogen-rich layer with strong Si–N bonds but also to a smooth interface. We conclude that ECR N2O-plasma polyoxide on in situ doped polysilicon is a good candidate for an interpoly dielectric of future high density NVMs.

Highly reliable polysilicon oxide grown by electron cyclotron resonance nitrous oxide plasma

Highly reliable inter-polysilicon oxide (polyoxide) for nonvolatile memory applications has been achieved using electron cyclotron resonance (ECR) N/sub 2/O-plasma. It is demonstrated that the N/sub 2/O-plasma polyoxide grown on doped poly-Si has a low leakage current and high breakdown field due to a smooth polyoxide/poly-Si interface and nitrogen incorporation during oxidation. Moreover, the polyoxide has much less electron trapping and over one order larger charge-to-breakdown (Q/sub bd/) up to 10 C/cm/sup 2/ than thermal polyoxide. The N/sub 2/O-plasma polyoxide can be a good choice for the interpoly dielectric of nonvolatile memories.

Simplified 0.35-μm flash EEPROM process using high-temperature oxide (HTO) deposited by LPCVD as interpoly dielectrics and peripheral transistors gate oxide

A simplified flash EEPROM process was developed using high-temperature LPCVD oxide both as flash cells interpoly dielectrics and as peripheral transistors gate oxide (decoding logic). An O/sub 2/ anneal at 850/spl deg/C lowers charge trapping and interface trap density induced by Fowler-Nordheim injection. However, electron trapping remains slightly higher than with dry thermal oxide. Similar memory charge loss and write-erase endurance are obtained as for ONO-insulated cells. HTO thus proves to have the required quality and reliability to be used in flash EEPROMs.

A highly robust process integration with scaled ONO interpoly dielectrics for embedded nonvolatile memory applications

We have developed a process sequence for a flash EEPROM memory embedded in an advanced microcontroller circuit. This process simultaneously forms a thick top oxide on the interpoly ONO dielectric in the memory array and a stacked gate-oxide for the logic transistors. We have fabricated one-transistor, flash bit-cells with good data retention characteristics that incorporate a 17 nm ONO film along with high-quality stacked gate oxides. >

Current Conduction and Charge Trapping in Thin Interpoly Dielectrics Prepared by In Situ Multiple Rapid Thermal Processing

In this paper we report a systematic and comprehensive study of the effects of post‐oxidation anneals on the electrical properties of thin polyoxide films. Thin (≤20 nm) interpoly dielectrics have been grown on phosphorus implanted polysilicon by in situ multiple rapid thermal processing (RTP) including rapid thermal oxidation (RTO1), rapid thermal nitridation (RTN), and subsequent rapid thermal reoxidation (RTO2). In comparison with polyoxides grown in conventional furnace, RTO1 polyoxides exhibit a significantly reduced leakage current. In addition, both the dielectric breakdown strength and breakdown field distribution have been improved. It is found that RTN of RTO1 results in polyoxides with an unusual polarity asymmetry dependence of electrical conduction and trapping properties, i.e., a higher electrical conduction and electron trapping rate for electrons injected from the top poly‐Si electrode than for electrons injected from the bottom poly‐Si electrode. Subsequent RTO2 of nitrided polyoxides results in a reduction of both the leakage current and electron trapping rate. Longer RTO2, however, increases the leakage current due to the progressively deteriorated poly‐Si/ polyoxide interfacial texture.

Polyoxide thinning limitation and superior ONO interpoly dielectric for nonvolatile memory devices

Results obtained from a study on thin interpoly dielectrics, especially for nonvolatile memories with stacked-gate structures, are presented. First, the key factors which dominate the leakage current in polyoxide are reviewed, and intrinsic limitations in thinner polyoxide for device applications are investigated considering defect densities and edge leakage current. Second, the ONO (oxide/nitride/oxide) structure which overcomes polyoxide-thinning limitations is described. This stacked film reveals superior electric-field strength due to the inherent electron-trapping-assisted process. UV erase characteristics for EPROM cells with ONO structure are discussed. The slower erasing speed for EPROM cells with ONO interpoly dielectric is due to the decrease in photocurrent flow from a floating gate to a control gate.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

A 23-ns 256 K EPROM with double-layer metal and address transition detection

A 256 K EPROM (electrically programmable read-only memory) is described in which 23-ns access time was achieved by a combination of advanced CMOS processing, double-layer metal (DLM), differential sensing, address transition detection (ATD), and a ground-switched decoding scheme. DLM is used to strap wordlines in the array and bus signals in the periphery. Performance is obtained by reducing bit line length to 256 cells, with 2048 cells per word line. This results in a 70.5-mil*229.8-mil array with an efficiency of 41.2%. Die size is 116 mil*339 mil. Short bit lines result in a total column and Y-select capacitance of 1.3 pF. Word line RC delay is only 0.8 ns. DLM saves 7.3 ns over an optimized silicide design using two word line drivers. The 0.8- mu m CMOS DLM EPROM technology yields a typical unloaded ring oscillator gate delay of 115 ps. Lightly doped drain (LLD) is used on both NMOS and PMOS devices for reliability and performance. Ti/Al metalization improves metal reliability. A composite interpoly dielectric is used for improved FAMOS (floating-gate avalanche-injection MOS) reliability. >

Nitride, Nitrided Oxide and Oxidized Nitride for Thin Dielectrics

ABSTRACTIn this paper, comparisons of material and electrical parameters between qate and interpoly dielectrics consistinq of thermal oxides, nitrides, nitrided oxides and oxidized nitrides are reported. A range of dielectrics, 5 nm to 30 nm thick, are thermally grown using a matrix of oxidation cycles, ammonia concentration and nitridation temperatures and pressures. Fabrication of polysilicon gate and interpoly capacitors is typical of industry standards. AES, RBS and ellipsometric analysis of dielectric material properties are discussed and electrical characterization results are presented.