International Technology Roadmap For Semiconductors Research Articles

Optimized leakage control in CMOS NAND gates: The In-Triggering technique

Abstract Leakage power, now the largest contributor to integrated circuit power consumption, is rising quickly, according to the International Technology Roadmap for Semiconductors (ITRS). As CMOS (complementary metal-oxide semiconductor) technology continues to shrink to deep submicron levels, gate leakage and subthreshold have become important components that contribute to total power dissipation. To address this problem, many methods have been put forth, especially at the circuit level. In 45 nm CMOS, variability and short-channel effects limit noise margins and compromise gate delays, thereby compromising the timing closure and robustness of ultra-low voltage circuits. The resulting supply voltage guardband may reduce energy efficiency in order to achieve a reasonable production yield. Furthermore, the high leakage currents of these technologies decrease energy efficiency when idle intervals are prolonged. In this study, two designs of a novel two-input NAND gate at 45 nm CMOS technology are constructed using eight transistors (8-T). A novel circuit technique named "In-Triggering (INDEP with Bi-Triggering)" is presented in this study with the goal of lowering subthreshold leakage in digital circuits. This method is thoroughly contrasted with other leakage reduction strategies now in use, such as Base, Sleepy LECTOR, LECTOR, INDEP, and Bi-Triggering procedures. Evaluation is done using key performance measures such power-delay product (PDP), latency, subthreshold leakage power, and total power consumption. 45-nm Predictive Technology Models (PTM) with a nominal supply voltage of 1V are used in the investigation. According to our findings, the suggested In-Triggering technique outperforms the conventional NAND gate in terms of speed by 12% and significantly reduces leakage power by up to 56%. Furthermore, compared to the Base, Trig01, and INDEP NAND gates, the method offers mean power savings of 58.8%, 36.1%, and 30.7%, respectively. At supply voltages of 1V, a comprehensive comparison and verification are then conducted utilizing the several proposed and existing methodologies. The effectiveness of the In-Triggering technique in reducing leakage power in CMOS circuits is confirmed by comparing these results to the most well-known design strategies for both active operation and sleep modes.

Dual-gated MOSFETs of α-In2Se3 monolayer for high performance and low power logic applications

As a well-known van der Waals 2D material with entangled ferroelectricity and semiconductivity, α-In2Se3 has garnered significant attention in recent years to develop novel nonvolatile (photo) electronic devices mainly based on its ferroelectricity. However, the ability of its semiconductivity to design 2D transistors for high-performance (HP) and low-power (LP) logic applications remains unclear. Herein, this article reveals the potential of α-In2Se3 as a semiconductor in sub-10 nm 2D transistors. We analyze a dual-gated metal–oxide–semiconductor field-effect transistor (MOSFET) based on monolayer (ML) α-In2Se3 with a 5 nm channel-length, utilizing density functional theory (DFT) in combination with non-equilibrium Green’s function method. The transport performance indicators of n-type MOSFET along the zigzag direction can satisfy or nearly satisfy the HP and LP application requirements of the International Technology Roadmap for Semiconductor (ITRS) 2013, while p-type MOSFET along the armchair direction exhibits an outstanding on-current attributed to effective mass and the density of states modulation. The p-type MOSFETs also exhibit ultralow leakage current and subthreshold swing below 60 mV/dec. Meanwhile, our simulated MOSFETs demonstrate large on-current and high ON/OFF ratios. These findings highlight the application prospect of α-In2Se3 as a conventional 2D semiconductor material for further 2D FETs in HP and LP logic applications.

Taguchi Method Statistical Analysis on Characterization and Optimization of 18-nm Double Gate MOSFETs

A bi-layer graphene with a multigate structure was intensified and analysed on an 18-nm Metal Oxide Semiconductor Field-Effect Transistor (MOSFET) device to obtain an optimal performance parameter. The device has a gate structure made of Titanium Dioxide (TiO2) that serves as a high-k material and a metal gate made of Tungsten Silicide (WSix). The Silvaco TCAD Software which are ATHENA and ATLAS modules were used to enhance the fabrication process of virtual devices and to verify the electrical properties of a specific device. According to the International Technology Roadmap Semiconductor (ITRS) specifications of 0.179 V ± 12.7% for threshold voltage (VTH) and 20 nA/m for leakage current (ILEAK), the Taguchi L9 orthogonal array strategy was used to improve the device process parameters for optimum VTH and ILEAK. For the NMOS device, the process parameter of VTH Adjust Implant Dose was used as the dominant factor while Source/Drain (S/D) Implant Energy was used as the adjustment factor whereby for PMOS device, S/D Implant Energy was the dominant factor while S/D Implant Tilt was the adjustment factor in order to achieve a robust design through the Taguchi method implementation. The percentage affecting the process parameter is then applied to the results of the signal to noise ratio (SNR) of Nominal-the-best (NTB) for VTH and Smaller-the-better (STB) for ILEAK.

(Invited) Biofabricated Carbon Nanotube Electronics: Toward Energy-Efficient Switches in Multi-Dimensional Integration

High-performance Si devices are approaching their physical boundaries during the continuous miniaturization following Moore's Law. New semiconductor materials are in urgent necessity, among which, carbon nanotubes（CNTs）are suggested by the International Technology Roadmap for Semiconductors（ITRS）as potential candidate to continue Moore's Law due to its quasi-one-dimensional structure and excellent electrical properties.To unleash the advantages of CNTs in the post-Moore era, optimizing materials morphology, interfaces composition, and integrated structure proves to be pivotal, which constitutes the basic idea of our research. Regarding material morphology, we have fabricated evenly spaced parallel CNT materials with a spacing down to 10nm, by employing the DNA-directed high-precision assembly method. At CNT interface, we have realized fast on/off switching high-performance switches by engineering the interfacial compositions. Individual CNT displays 1G0 conductance with subthreshold swing superior to conventional Si transistors. Furthermore, we built the preliminary foundation to integrate CNT transistors into multi-dimensional circuits. Based on the control of material, interface, and integration structure, our work elucidates the potential of constructing energy-efficient computing circuit using carbon nanotube electronics.

High-Performance Sub-10 nm Two-Dimensional SbSeBr Transistors through Transport Orientation.

Exploring two-dimensional (2D) materials with a small carrier effective mass and suitable band gap is crucial for the design of metal oxide semiconductor field effect transistors (MOSFETs). Here, the quantum transport properties of stable 2D SbSeBr are simulated on the basis of first-principles calculations. Monolayer SbSeBr proves to be a competitive channel material, offering a suitable band gap of 1.18 eV and a small electron effective mass (me*) of 0.22m0. The 2D SbSeBr field effect transistor (FET) with 8 nm channel length exhibits a high on-state current of 1869 μA/μm, low power consumption of 0.080 fJ/μm, and small delay time of 0.062 ps, which can satisfy the requirements of the International Technology Roadmap for Semiconductors for high-performance devices. Moreover, despite the monolayer SbSeBr having an isotropic me*, the asymmetrical band trends enable SbSeBr FETs to display transport orientation, which emphasizes the importance of band trends and provides valuable insights for selecting channel materials.

SiX2 (X = S, Se) Nanowire Gate-All-Around MOSFETs for Sub-5 nm Applications.

The gate-all-around (GAA) field-effect transistor (FET) holds great potential to support next-generation integrated circuits. Nanowires such as carbon nanotubes (CNTs) are one important category of channel materials in GAA FETs. Based on first-principles investigations, we propose that SiX2 (X = S, Se) nanowires are promising channel materials that can significantly elevate the performance of GAA FETs. The sub-5 nm SiX2 (X = S, Se) nanowire GAA FETs exhibit excellent ballistic transport properties that meet the requirements of the 2013 International Technology Roadmap for Semiconductors (ITRS). Compared to CNTs, they are also advantageous or at least comparable in terms of gate controllability, device dimensions, etc. Importantly, SiSe2 GAA FETs show superb gate controllability due to the ultralow minimum subthreshold swing (SSmin) that breaks "Boltzmann's tyranny". Moreover, the energy-delay product (EDP) of SiX2 GAA FETs is significantly lower than that of the CNT FETs. These features make SiX2 nanowires ideal channel material in the sub-5 nm GAA FET devices.

CMOS Scaling for the 5 nm Node and Beyond: Device, Process and Technology.

After more than five decades, Moore's Law for transistors is approaching the end of the international technology roadmap of semiconductors (ITRS). The fate of complementary metal oxide semiconductor (CMOS) architecture has become increasingly unknown. In this era, 3D transistors in the form of gate-all-around (GAA) transistors are being considered as an excellent solution to scaling down beyond the 5 nm technology node, which solves the difficulties of carrier transport in the channel region which are mainly rooted in short channel effects (SCEs). In parallel to Moore, during the last two decades, transistors with a fully depleted SOI (FDSOI) design have also been processed for low-power electronics. Among all the possible designs, there are also tunneling field-effect transistors (TFETs), which offer very low power consumption and decent electrical characteristics. This review article presents new transistor designs, along with the integration of electronics and photonics, simulation methods, and continuation of CMOS process technology to the 5 nm technology node and beyond. The content highlights the innovative methods, challenges, and difficulties in device processing and design, as well as how to apply suitable metrology techniques as a tool to find out the imperfections and lattice distortions, strain status, and composition in the device structures.

High-performance Schottky-barrier field-effect transistors based on two-dimensional GaN with Ag or Au contacts

The performance of two-dimensional (2D) monolayer GaN Schottky barrier field effect transistors (SBFETs) with four different metals (Ag, Au, Al, and Pt) as electrodes were studied by using ab initio simulations. The N-type Schottky contact is formed on Ag-GaN, Au-GaN, and Pt-GaN, characterized by electron Schottky barrier heights (SBH) of 0.6, 0.5, and 0.38 eV, respectively. Whereas, Al-GaN contact formed P-type Schottky contact with hole SBH of 1.42 eV. The 5.1 nm GaN SBFETs with four metal electrodes all could overcome the short-channel effect. Additionally, GaN SBFETs with Ag and Au electrodes have excellent performance, whose ON-currents are 1151.1 μA/μm and 1258.9 μA/μm, respectively. They could satisfy the demands of International Technology Roadmap for Semiconductors for high-performance transistor. Furthermore, research indicates that the device's current increases with increasing temperature. Notably, under the constant bias and gate voltage, the current is unaffected by temperature variations between the left and right electrodes.

Polythiophene-based organic transistors：Time to a single nanowire and sub-5 nm gate length

Future organic field-effect transistors (FETs) may utilize one-dimensional (1D) semiconductor materials in their channels. In this study, we used the ab initio method to explore the transport characteristics of 1D nanowire polythiophene FETs comprehensively. Based on the 2028 map in the International Technology Roadmap for Semiconductors (ITRS) in 2013, our theoretical simulations showed that n-type and p-type gate-all-around (GAA) 1D polythiophene FETs with 5-nm gate length (Lg) and appropriate underlap (UL) satisfy the basic high-performance and low-power-consumption device applications. Moreover, both the n-type and p-type GAA 1D polythiophenee FETs (Lg = 3 nm) meet the high-performance needs of ITRS. Our numerical results revealed that the organic transistors can be designed by using a single nanowire and the minimum Lg of transistors can scale to 3 nm.

Sub-5 nm Ultrathin In2O3 Transistors for High-Performance and Low-Power Electronic Applications.

Ultrathin oxide semiconductors are promising candidates for back-end-of-line (BEOL) compatible transistors and monolithic three-dimensional integration. Experimentally, ultrathin indium oxide (In2O3) field-effect transistors (FETs) with thicknesses down to 0.4 nm exhibit an extremely high drain current (104 μA/μm) and transconductance (4000 μS/μm). Here, we employ ab initio quantum transport simulation to investigate the performance limit of sub-5 nm gate length (Lg) ultrathin In2O3 FETs. Based on the International Technology Roadmap for Semiconductors (ITRS) criteria for high-performance (HP) devices, the scaling limit of ultrathin In2O3 FETs can reach 2 nm in terms of on-state current, delay time, and power dissipation. The wide bandgap nature of ultrathin In2O3 (3.0 eV) renders it a suitable candidate for ITRS low-power (LP) electronics with Lg down to 3 nm. Notably, both the HP and LP ultrathin In2O3 FETs exhibit superior energy-delay products as compared to those of other common 2D semiconductors such as monolayer MoS2 and MoTe2. These findings unveil the potential of ultrathin In2O3 in HP and LP nanoelectronic device applications.

Quantum transport in WSe2/SnSe2 tunneling field effect transistors with high-k gate dielectrics

Combining two-dimensional materials and high-k gate dielectrics offers a promising way to enhance the device performance of tunneling field-effect transistor (TFET). In this work, the device performance of WSe2/SnSe2 TFET with various gate dielectric materials is investigated based on quantum transport simulation. Results show that TFETs with high-k gate dielectric materials exhibit improved on-off ratio and enhanced transconductance. The optimized WSe2/SnSe2 TFET with TiO2 gate dielectrics achieves an on-state current of 1560 μA/μm and a subthreshold swing (SS) of 48 mV/dec. The utilization of high-k gate dielectric materials results in shorter tunneling length, higher transmission efficiency, and increased electron tunneling probability. The performance of the WSe2/SnSe2 TFET would be affected by the presence of the underlap region. Moreover, WSe2/SnSe2 TFETs with La2O3 dielectric can be scaled down to 3 nm while meeting high-performance (HP) device requirements according to the International Technology Roadmap for Semiconductors (ITRS). This research presents a practical solution for designing advanced logic devices in the sub-5 nm technology node.

Performance limits exploration of sub-5 nm monolayer germanane transistors: A first-principle quantum transport simulation

Two-dimensional germanium is considered a promising new channel material to replace silicon owing to its lower effective mass and larger electron–hole mobility. To investigate the transport characteristics of single-layer germanane transistors with gate lengths (Lg) below 5 nm, we utilize an ab initio quantum transport methodology. It was found that the n-type germanane transistors having Lg of 3 and 5 nm satisfy the International Technology Roadmap for Semiconductors (ITRS) requirements for the on-state current (Ion), effective delay time, and power-delay products of high-performance (HP) devices. Notably, by introducing a negative capacitive (NC) dielectric layer, the p-type germanane transistor having an Lg of 5 nm is almost able to meet the ITRS demands for HP devices. Despite reducing the gate length to 2 nm through the incorporation of the NC dielectric layer, the on-state currents for both n-type and p-type still satisfy approximately 80% of the ITRS standard. Therefore, monolayer germanane presents promising potential as a channel material in a sub-5 nm scale for HP applications.

Low-Power Transistors with Ideal p-type Ohmic Contacts Based on VS2/WSe2 van der Waals Heterostructures.

Achieving low-resistance Ohmic contacts with a vanishing Schottky barrier is crucial for enhancing the performance of two-dimensional (2D) field-effect transistors (FETs). In this paper, we present a theoretical investigation of VS2/WSe2-vdWHs-FETs with a gate length (Lg) in the range of 1-5 nm, using ab initio quantum transport simulations. The results show that a very low hole Schottky barrier height (-0.01 eV) can be achieved with perfect band offsets and reduced metal-induced gap states (MIGS), indicating the formation of p-type Ohmic contacts. Additionally, these FETs also exhibit an impressive low subthreshold swing (SS) (69 mV/dec) and high Ion/Ioff (>107) with an appropriate underlap (UL) structure consisting of pristine WSe2. Furthermore, even when the Lg is scaled down to 3 nm, the device can still meet the low-power (LP) requirements of the International Technology Roadmap for Semiconductors (ITRS) by controlling the UL. Consequently, this study provides valuable insights for the future development of LP 2D FETs.

A next-generation transistor with low supply voltage operation constructed based on 2D materials' metal-semiconductor phase transition.

Power dissipation, a fundamental limitation for realizing high-performance electronic devices, may be effectively reduced by an external supply voltage. However, a small supply voltage simultaneously brings another serious challenge, that is, a remarkable device inability in transistors. To deal with this issue, we propose a new transistor design based on the metal-semiconductor phase transition in a AsGeC3 monolayer, which provides a switching mechanism of band-to-band tunneling at on- and off-states by gate-voltage modulation. Our first-principles calculations uncover that the monolayer AsGeC3 field-effect transistors (FETs) with gate lengths of 5, 4, and 3 nm may meet well the requirements for on-state current (Ion), power dissipation (PDP), and delay period (τ) as outlined by the International Technology Roadmap for Semiconductors (ITRS) in 2013 to achieve higher performance by the year 2028. Importantly, high performances are achieved only under a very low supply voltage (VDD = 0.05/0.10 V). Significantly, the AsGeC3 FETs exhibit remarkably lower values of both PDP and τ than those of nearly all the transistors reported up to date. These novel 2D metal-semiconductor phase transition-based FETs open up a new door for designing next-generation low-power electronic devices.

Ballistic transport in sub-10 nm monolayer InAs transistors for high-performance applications.

As an outstanding two-dimensional (2D) semiconductor among III-V compounds, InAs has attracted significant attention due to its much higher electron mobility than silicon and potential for enhanced opportunities in the field of electronic and optical devices. Recently, 2D semiconducting InAs with a thickness of 4.8 nm has been successfully prepared. Here, we systematically investigated the ballistic transport characteristics of sub-10 nm monolayer InAs (InAsH2) metal-oxide-semiconductor field-effect transistors (MOSFETs) by using ab initio quantum transport simulation, which includes on-state current, subthreshold swing, intrinsic delay time, and power consumption. The results suggest that the monolayer (ML) InAsH2 MOSFETs exhibit excellent performance with a beneficial doping concentration and underlap, which can meet the high-performance requirements of the International Technology Roadmap for Semiconductors (ITRS) for the 2013 version until the length of the gate is decreased to 4.0 nm. Moreover, we studied the influence of high-k dielectric effects. We found that both the on-state current and subthreshold swing with a 5.0 nm-gate-length are apparently improved. This work indicates that ML InAsH2 is a suitable nominee for the upcoming generation of channel materials.

Towards ultralow-power and high-speed electronics: Tunnel transistor based on single-chain Tellurium

The application of tunnel field-effect transistors (TFETs) in the sub-5.1 nm range meets the challenges of low on-state current (Ion), elevated leakage current (Ileak) and a limited bias range with sub-thermionic subthreshold swing (SS) characteristics. Here, by the design of gate-all-around (GAA) single-chain Te (1Te) TFETs, the sub-thermionic SS characteristics span nearly six orders of magnitude of drain current, overcoming the above challenges. While there usually exists trade-offs between maximizing Ion and minimizing Ileak, our optimized 5.1 nm GAA 1Te TFET defies this convention. Its steep turn-on characteristics result in an ultra-low Ileak of 7.9 × 10−10 μA/μm coupled with a high Ion of 1352 μA/μm, surpassing other low-dimensional materials-based FETs. These exceptional performances are attributed to the desirable properties from ultra-thin 1Te, including its moderate bandgap, anisotropic effective mass, and reduced screening length. Crucially, this device demonstrates key figure of merits for digital electronics that fulfill both the requirements of high-performance and low-power device specified by the International Technology Roadmap for Semiconductors, indicating the potential as energy-efficient and high-speed electronic switch. Our findings are expected to stimulate further research into sub-5.1 nm quasi-1D materials-based TFETs and provide valuable insights for optimizing their performance.

The interfacial properties of 2D metal-monolayer blue phosphorene heterojunctions and transport properties of their field-effect transistors

Monolayer blue phosphorene (BlueP) has attracted much interest as a potential channel material in electronic devices. Searching for suitable two-dimensional (2D) metal materials to use as electrodes is critical to fabricating high-performance nanoscale channel BlueP-based field effect transistors (FETs). In this paper, we adopted first-principles calculations to explore binding energies, phonon calculations and electronic structures of 2D metal-BlueP heterojunctions, including Ti3C2-, NbTe2-, Ga(110)- and NbS2-BlueP, and thermal stability of Ti3C2-BlueP heterojunction at room temperature. We also used density functional theory coupled with the nonequilibrium Green function method to investigate the transport properties of sub-5 nm BlueP-based FETs with Ti3C2-BlueP electrodes. Our calculated results indicate that Ti3C2-BlueP has excellent thermal stability and may be used as a candidate electrode material for BlueP-based FETs. The double-gate can more effectively improve the device performance compared with the single-gate. The estimated source leakage current of sub-5 nm transistors reaches up to 369 µA µm−1, which is expected to meet the requirements of the international technology roadmap for semiconductors for LP (low-power) devices. Our results imply that 2D Ti3C2 may act as an appropriate electrode material for LP BlueP-based FETs, thus providing guidance for the design of future short-gate-length BlueP-based FETs.

Scaling limits of monolayer AlN and GaN MOSFETs

The shrinking of transistors to ultra-scale limits is in great demand to extend Moore’s law, where the search for proper alternative channel materials is significant. The III-V group compounds are regarded as post-Si candidates for their high electron mobility. Herein, we simulate the monolayer (ML) AlN and GaN metal–oxidesemiconductor field-effect transistors (MOSFETs) with ab initio quantum transport simulation to evaluate their scale limit. The ML AlN and GaN MOSFETs exhibit much better n-type performances than their p-type counterparts, and the n-type ML AlN (GaN) MOSFETs can surpass the International Roadmap for Device and Systems (IRDS, 2022 version) lower-power (LP) and high-performance (HP) target for the year 2028 even at gate length (Lg) of 3 and 2 nm, respectively. Encouragingly, the optimal n-type ML AlN (GaN) MOSFETs possess the highest (second-highest) Ion against all studied n-type ML MOSFETs and propel the Lg limit that outperforms the International Technology Roadmap for Semiconductors (ITRS, 2013 version) LP and HP targets to 2 and 1 (2) nm, respectively.

Ultrahigh current and ultralow power dissipation of Janus monolayer IIIA-VIA Ga2XY MOSFETs

With the advances of two-dimensional semiconductors, it is promising for the miniaturization of highly integrated circuits. However, the high leakage current, small on-state current and unnecessary power consumption hinder the development of high-performance nanodevices. Here, we design sub-5-nm double-gate monolayer Ga2XY (X, Y = S, Se and Te) metal–oxidesemiconductor field-effect transistors. For all the designed devices, the on-state current, intrinsic delay time and power delay product can meet the standard of the International Technology Roadmap for Semiconductor in 2028. Additionally, the devices based on large bandgap materials have strong inhibition effect on leakage current. In particular, the Ga2SSe device has optimized subthreshold swing as low as 60.7 mV/dec and Ion of 5082 μA/μm (about 6 times higher than the high-performance requirements). The extremely low energy-delay product of 3.64 × 10−31 Js/μm is obtained for the Ga2SeTe device. Therefore, monolayer Ga2XY can be expected for the application of next-generation high-performance electronic nanodevices.

Geometric, Electronic, and Transport Predictions on Two-Dimensional Semiconducting Silicon with Kagome Lattice: Implications for Nanoscale Field-Effect Transistor Applications

Two-dimensional (2D) semiconducting silicon (Si) is significant for the development of micro/nanoelectronics because of their compatibility with the current Si-based technology and the advantages common to 2D electronic materials. Here, by focusing on the kagome lattice (KL), we design a set of semiconducting 2D KL-Si for nanoscale field-effect transistor (FET) applications. First-principles calculations demonstrate that both stable geometric properties and tunable semiconducting electronic properties can be obtained for the 2D KL-Si with different thicknesses. The 2D KL-Si features electronic band gaps ranging from 2.82 to 1.36 eV as a function of increasing the layer thickness and hole/electron mobility as large as about 103 cm2·V–1·s–1. By applying the KL-Si to nanoscale FETs, we obtain giant negative differential resistances with peak-valley ratios over 107 and excellent switching performance fulfilling the requirements of the International Technology Roadmap for Semiconductors. Our study demonstrates the importance of kagome topology in the design of 2D Si crystals with excellent semiconducting properties as well as their promising application in nanoelectronic devices.