Interfacial SiO2 Layer Research Articles

Investigation of scale formation and degeneration of silicide coating on Nb–Si based alloy in the temperature range from 1250 °C to 1560 °C

Nb silicide coatings modified with active elements have good oxidation resistance, but there is a lack of systematic research on their oxidation behavior at high temperatures above 1250 °C. The aim of this work is to investigate the oxidation behavior of an Al–Y modified silicide coating on Nb–Si based alloy in the temperature range from 1250 °C to 1560 °C. After oxidation at 1250 °C, the scale displays a typical layered structure consisting mainly of a TiO2 outer layer, an amorphous SiO2 matrix layer embedded with TiO2 and ZrSiO4, and an inner layer consisting of SiO2 and Cr2O3. Above 1350 °C, the evaporation reaction of Cr2O3 into CrO3 (g) is significantly accelerated and Cr2O3 disappeared gradually with temperature or time. The TiO2 layers covering on the scales formed at 1250–1500 °C grow along the crystallographic orientation of [100]. The micropores formed on the surface of TiO2 should be attributed to the further oxidation of Cr2O3 into volatile oxide CrO3 (g). The scales exhibit a similar structure consisting mainly of a SiO2 glass matrix embedded with ZrSiO4 and a surface TiO2 layer until 1500 °C. Above the eutectic temperature of SiO2–TiO2 system, the scale is mainly composed of a matrix layer of SiO2–TiO2 eutectic embedded with block TiO2 particles, and a thin SiO2 interface layer at 1560 °C. The degeneration path of the (Nb,X)Si2 coating is (Nb,X)Si2 → (Ti,Nb)5Si4 → γ-(Nb,X)5Si3.

Sensitivity enhancement using triple metal gate work function engineering of junctionless cylindrical gate all around SiNW MOSFET based biosensor for neutral biomolecule species detection for upcoming sub 14 nm technology node

In the present work Dielectric Modulation (DM) technique along with Triple Metal (TM) gate engineering has been used for the junctionless (JL) cylindrical gate all around (CGAA) Si nanowire (NW) MOSFET based biosensor for label free electrical detection of neutral biomolecules species like Uricase, Streptavidin, Protein, Biotin, ChOx (choline oxidase), and APTES etc. For this device, the Drift Diffusion approach has been used along with self-consistent solution of Schrodinger’s equation with Poisson’s equation. For the biomolecule immobilization, a nanogap cavity region is formed in the JL SiNW MOSFET by etching gate oxide layer above the SiO2 interfacial layer. The change in the drain current (ID), threshold voltage (Vth), off-current sensitivity (SIoff), threshold voltage sensitivity (SVth) and Ion/Ioff current ratio of the device have been considered as the sensing parameters for detection of biomolecules under dry environment condition. In present work a new sensing metric of sensing of biomolecules – DIBL has been added which has never been reported in literature. In this work for JL SiNW, sensitivity metrics like smaller DIBL ∼50.47 mV/V, higher SIoff9.33×105, higher SVth28.72, nearly ideal subthreshold slope (SS) ∼60 mV/dec, and higher Ion/Ioff current ratio ∼9.01 × 1012 have been obtained in comparison to available literature results.

Optoelectronic properties of Au/n-type Si semiconductor structures with SiO2 interlayer

In this study, we investigated the effect of light intensity on electrical and photovoltaic properties using current-voltage (I–V) measurements at room temperature of Au/n-type Si structures with SiO2 interface layer. At each light intensity, the obtained main electrical characteristics such as ideality factors (n), barrier heights (Φbo), rectification ratios (RR), saturation currents (I0) and series resistances (RS) of Au/SiO2/n-type Si structures were calculated from both thermionic emission (TE) and Cheung methods using I–V measurements and compared to each other. Experimental results showed that while the n and I0 values increased with the increase in the light intensity, the Φbo and RR values decreased. While the ideality factor values obtained using the TE method ranged between 1.973 (at dark) and 2.250 (for 100 mW/cm2), these values were obtained between 3.227 and 3.482 using the Cheung method. At the same time, while the barrier height values obtained using the TE method ranged between 0.865 eV (at dark) and 0.817 eV (for 100 mW/cm2), these values were obtained between 0.773 eV and 0.742 eV using the Cheung method. It was observed that while the n values obtained from TE theory were smaller than the values obtained from the Cheung method, the Φbo values were larger than the values obtained from the Cheung function. Furthermore, for the Au/SiO2/n-type Si structures, the photovoltaic parameters such as short circuit current (Isc) and open circuit voltage (Voc) and photocurrent (Iph) were examined under dark, daylight and various light intensities (from 20 to 100 mW/cm2).

Structural, chemical, and metal-oxide-semiconductor characteristics of RF magnetron sputtered thulium oxide passivation layer on 4H-silicon carbide substrate

Thulium oxide (Tm2O3) passivation layer (PL) deposited on 4H-silicon carbide (SiC) that was subjected to postdeposition annealing at 700 °C in forming gas-oxygen-forming gas ambient was reported for the first time in this work. X-ray photoelectron spectroscopy characterization revealed the success of annealing process in minimizing the concentration of oxygen vacancies and also curbed the presence of TmO suboxide bonding in the annealed Tm2O3 PL. In addition, XPS characterization has also disclosed the incorporation of nitrogen ions into the Tm2O3 lattice through the annealing process in which grazing incidence X-ray diffraction has also revealed the shift of detected peaks with regards to Tm2O3 phases to small diffraction angles. Although X-ray reflectivity measurements have disclosed the formation of thicker SiO2 interfacial layer (IL) for the annealed Tm2O3 PL, the acquisition of a higher dielectric constant (k) by the annealed PL when compared to as-deposited PL has suggested that the formation of SiO2 IL has minimal effect toward the k value of annealed PL. Metal-oxide-semiconductor characteristics of the annealed Tm2O3 PL on 4H-SiC was systematically reported in this letter.

Nature-inspired parylene/SiO2 core-shell micro-nano pillars: Effect of topography and surface chemistry

We investigated the synergy of surface topography and chemistry in micro/nanostructured pillars inspired by nature, specifically mimicking tokay gecko (Gekko gecko Linnaeus, 1758) feet and sacred lotus (Nelumbo nucifera Gaertn., 1788) leaves. The aim is to understand and replicate their adhesive and self-cleaning properties for diverse applications. Through a detailed fabrication process and chemical modifications, the surfaces exhibit superhydrophobic characteristics. The research precisely examines the fabrication of surfaces with well-defined micropillars using lithography and deep silicon substrate etching. Diverse surface treatments, including silanization and O2 plasma, are applied to tailor the chemical composition of microstructured surfaces. Utilizing a ≈ 5 nm thin SiO2 interface layer, the study reveals superhydrophobic properties post-silanization and an eightfold increase in adhesion force (FA) between the studied surface and reference surfaces. FA measurements using atomic force microscopy reveal an eightfold increase in adhesion on both flat and microstructured surfaces, emphasizing the transformative effects of microstructures on surface morphology. The findings highlight the potential for multifunctional surface designs, elucidating that superhydrophobic properties correlate with structure topography while FA amplitude is predominantly determined by surface termination. Inspired by nature, this research unveils novel possibilities in functional materials and surface engineering, with broad implications across various applications.

Effects of Varying Annealing Ambient towards Performance of Ternary GaxCeyOz Passivation Layers for Metal-Oxide-Semiconductor Capacitor

In this work, different annealing ambient (nitrogen-oxygen-nitrogen (N2-O2-N2), forming gas-oxygen-forming gas (FG-O2-FG), and argon-oxygen-argon (Ar-O2-Ar)) were explored to investigate the feasibility of employing the annealed ternary GaxCeyOz passivation layer (PL) for development of Si-based metal-oxide-semiconductor (MOS) capacitors. The impact of nitrogen and/or hydrogen in hindering the growth of silicon dioxide (SiO2) interfacial layer (IL) was quantitatively evaluated. The combination of effects brought by nitrogen attached to oxygen vacancies, nitrogen-silicon bonding, and nitrogen accumulation at the GaxCeyOz/Si interface effectively minimized the formation of SiO2 IL. Consequently, among all the samples, the GaxCeyOz PL annealed in N2-O2-N2 ambient exhibited superior MOS characteristics in terms of low effective oxide charge, slow trap density, interface trap density, and interface state density, which have translated into good leakage current density-electric field characteristics.

Comprehensive analysis of read-after-write latency in HfZrOX-based ferroelectric field-effect-transistors with SiO2 interfacial layer

In this paper, a quantitative analysis is performed focusing on the read-after-write latency (RWL) phenomenon in HfOX-based ferroelectric field-effect transistors with a metal-ferroelectric-insulator-semiconductor structure. RWL is scrutinized by modifying two variables: the pulse width (tp) for the “write 1” operation and the operating temperature (T); the response of the charge component is found to follow an emission mechanism. Additionally, we identified a notable change in charge behavior at a specific temperature (Tb), where capture and emission are in balance. Experimental investigations have demonstrated that the activation energy (EA) for these charge components is situated between 0.2 and 0.5 eV, and the Tb is ∼50 °C. By elucidating the relationship between T, tp, remnant polarization (Pr), and Tb, we offer insights into the importance of optimizing tp and Pr on the transient response of the balanced charge and the related RWL phenomenon.

(Invited) Physical Understanding of HfZrO2/Si FeFET Memory and Its AI Applications

Since the discovery of ferroelectricity in HfO2-based dielectric films in 2011 [1], FeFETs using HfO2-based ferroelectric films as gate dielectrics have attracted strong interest and have been intensively studied in the worldwide research community for various applications including memory, logic, and AI computing. In this paper, we present our recent activities on HfZrO2 (HZO)/Si FeFETs memory [2-6] and FeFET reservoir computing [7-9] for low-power memory and AI applications.HZO-based FeFETs are currently expected for a variety of applications such as embedded nonvolatile memory, cross-bar Commutation-in-Memory (CiM), and so on. However, the device operation has not been quantitatively understood yet. One of the fundamental questions in FeFETs is a mismatch between areal surface carrier concentration (Ns) in MOSFETs, ~1013 cm-2 at maximum, and typical polarization (P) values, ~10-20 mC/cm2. These polarization values correspond to Ns higher than 1014 cm-2 and induce an electric field across an interfacial layer (IL) of 30 MV/cm or higher, which could cause oxide breakdown. On the other hand, when a large amount of traps is included in an HZO film or an HZO/IL interface, sufficient P values can be obtained without too high Ns and the electric field [2, 4-6]. Thus, it is very important to experimentally characterize P, Ns, and trapped charge density, which were evaluated by P-V, quasi-static split C-V, and Hall measurements, respectively, [2, 3, 6] for 10-nm-thick HZO/Si n- and p-FeFETs with 0.7-nm-thick SiO2 IL. As a result, it has been found that a high trap density of around 1014 cm-2 is observed in n-FeFETs, while there is almost no hole trapping in p-FeFETs. This high electron trap density leads to the high electric field across the HZO film and resulting high P values in n-FeFETs, which is in contrast to p-FETs. Thus, the larger memory window in n-FeFETs than that in p-FeFET is attributed to the difference in P values with applying the positive and negative gate voltages.On the other hand, we have proposed and demonstrated reservoir computing, which is one of AI calculations using a recurrent neural network, by using HZO/Si FeFETs [7-9]. Reservoir computing has recently been attracting strong attention as a method to realize real-time learning of time-series data at the edge. Furthermore, when this reservoir is represented by hardware that has input-history-dependent and nonlinear dynamics (physical reservoir), we can expect significant improvement in the energy efficiency of AI calculations. In our FeFET reservoir, the time response of a drain current of Si FeFETs was utilized as the virtual nodes. We have experimentally demonstrated high classification accuracy in speech recognition by using this HZO/Si FeFET reservoir computing with parallel data processing [9]. The spoken digit recognition task, which is an example of speech recognition applications, was performed on a basis of multiple frequency channel (cochleagram) data, which were input to multiple FeFETs. The final inference was conducted by a majority vote of the multiple FeFET reservoirs. We introduced several approaches in the proposed FeFET reservoir computing system, such as optimization of the number of virtual nodes per time step, analog and digital input waveforms, the utilization of other currents than the drain current, and the combination of different frequency channels, in order to improve the classification accuracy. The choice of a combination of frequency channels was effective in improving recognition accuracy. Also, combining the time responses of the drain, source, and substrate currents was also important. These various methods additively improved the recognition accuracy. As a result, we have experimentally demonstrated a classification accuracy of 95.9 % in the task to classify the audio waveforms of ‘0’ to ‘9’ spoken digits.This work was supported by JST CREST (JPMJCR20C3) and JSPS KAKENHI (21H01359).

(Invited) Fabrication Technique of Ferroelectric HfxZr1−XO2 Thin Films Using ALD-ZrO2 Nucleation Layers

Ferroelectric HfxZr1−xO2 (HZO) thin films have attracted considerable attention towards high-density and low-power ferroelectric memory devices of ferroelectric random access memory (FeRAM) and ferroelectric field-effect transistors (FeFETs) [1]. To obtain ferroelectric orthorhombic (O) phase of HZO films, several techniques have been investigated, such as the TiN stressor layer technique [2] and controlled annealing conditions [3]. On the other hand, we pay attention to the ZrO2 nucleation layer technique because ZrO2 films deposited by atomic layer deposition (ALD) method formed a nanocrystalline structure and consisted dominantly of O, tetragonal (T), and cubic (C) phases, whose lattice constants are considerably close to that of ferroelectric O phase for HfO2 [4]. In this paper, we report the crystallinity and ferroelectricity of HZO films fabricated using the ZrO2 nucleation layer technique for metal-ferroelectric-metal (MFM) and metal-ferroelectric-semiconductor (MFS) capacitors.First, four types of MFM capacitors of TiN/HZO/TiN (MFM w/o), TiN/HZO/bottom-ZrO2/TiN (MFM B-ZrO2), TiN/top-ZrO2/HZO/TiN (MFM T-ZrO2), and TiN/top-ZrO2/HZO/bottom-ZrO2/TiN (MFM D-ZrO2) were systematically investigated for the FeRAM applications [5]. The thicknesses of the ALD-grown HZO and ZrO2 films were 10 and 2 nm, respectively. The post-deposition annealing was performed at 600°C. The remanent polarization (2P r = P r + − P r −) of the MFM capacitors increased in the following order: MFM w/o (12 µC/cm2) < MFM B-ZrO2 (15 µC/cm2) < MFM T-ZrO2 (23 µC/cm2) < MFM D-ZrO2 (29 µC/cm2), while all capacitors showed almost the same coercive electric field (E c) value of around 1.2 MV/cm. Therefore, maximum 2P rvalue of the MFM capacitor was obtained using the top- and bottom-ZrO2 nucleation layers. For the MFM capacitors with ZrO2 nucleation layers, epitaxial-like grain growth of the HZO film occurred on the nanocrystalline top- and bottom-ZrO2 layers. Moreover, the relative ratio of O/T/C phases in the ferroelectric film, which was estimated using the peak area ratio of O(111)/T(101)/C(111)/{M(−111)+ O(111)/T(101)/C(111)+M(111)}, increased in the following order: MFM w/o < MFM B-ZrO2 < MFM T-ZrO2 < MFM D-ZrO2. Therefore, the top- and bottom-ZrO2 layers play an important role as nucleation layers for the crystallization of the HZO film, resulting in a larger relative ratio of O/T/C phases in the ferroelectric film compared to w/o. Moreover, these results indicate that the top-ZrO2 layer was more effective to form the ferroelectric phase compared to the bottom-ZrO2 layer.Next, two types of MFS capacitors of TiN/HZO/Si (MFS w/o) and TiN/top-ZrO2/HZO/Si (MFS T-ZrO2) were fabricated by low-temperature processes at 300°C of ALD and post-metallization annealing (PMA) for the FeFET applications [6]. The thicknesses of both HZO and ZrO2 films were 10 nm. Both MFS w/o and MFS T-ZrO2 were found to form an extremely thin SiO2 interfacial layer with a thickness of one or two monolayers between the HZO film and Si substrate due to a low temperature fabrication process of 300°C. The HZO film of the MFS T-ZrO2 formed O/T/C phases even with a low thermal budget of 300°C, while that of the MFS w/o had an amorphous structure. This result is attributed to the beneficial role of the nanocrystalline top-ZrO2 nucleation layer for the crystallization of an amorphous HZO film during the PMA process. Therefore, a higher 2P r value of 15 µC/cm2 was obtained for the MFS T-ZrO2 than that (2.2 µC/cm2) for the MFS w/o. Moreover, the endurance properties of the MFS T-ZrO2 were free from the wake-up effect and exhibited less degradation of switching polarization (P sw). This could be attributed to the insertion of a ZrO2 film at the TiN/HZO interface, which promoted the preferential formation of the ferroelectric orthorhombic phase and prevent the formation of oxygen vacancies at the ZrO2/HZO interface. Thus, we concluded that superior ferroelectricity with wake-up free properties and higher fatigue resistance of HZO-based MFS capacitors were achieved by using the ZrO2 nucleation layer technique.These results suggest that the fabrication technique of ferroelectric HZO films using nanocrystalline ALD-ZrO2 nucleation layers is one of the promising processes for the next-generation non-volatile memory device applications.This work was supported by JSPS KAKENHI (Nos. JP21J01667, JP20H02189, and JP18J22998) and MEXT Leading Initiative for Excellent Young Researchers (No. JPMXS0320220213).[1] T. Mikolajick et al., J. Appl. Phys. 129, 100901 (2021).[2] S. J. Kim, et al., Appl. Phys. Lett. 111, 242901 (2017).[3] S. Migita et al., Jpn. J. Appl. Phys. 58, SBBA07 (2019).[4] T. Onaya et. al., Appl. Phys. Express. 10, 081501 (2017).[5] T. Onaya et al., APL Mater. 7, 061107 (2019).[6] T. Onaya et al., APL Mater. 10, 051110 (2022).

Growth of gallium cerium oxide passivation layer on 4H-Silicon carbide substrate and its metal-oxide-semiconductor characteristics

Gallium cerium oxide (GaxCeyOz) passivation layer was successfully grown on 4H-silicon carbide (SiC) through postdeposition annealing at 800 °C in nitrogen-oxygen-nitrogen (N2–O2–N2) ambient. The gracing incident X-ray diffraction and ultraviolet–visible spectrophotometer measurements have confirmed the successful incorporation of Ga3+ cation into the CeO2 lattice to form the ternary GaxCeyOz passivation layer. In addition, the thicknesses of GaxCeyOz passivation layer and silicon dioxide (SiO2) interfacial layer (IL) were determined using field-emission scanning electron microscopy and X-ray reflectivity characterizations. A high dielectric constant (k) value of 24.11 was attained for the investigated Al/GaxCeyOz/4H–SiC/Al metal-oxide-semiconductor (MOS) structure attributable to the nitrogen ions accumulating at the interface that have retarded the growth of SiO2 IL. Besides, the effective oxide charge, slow trap density, interface trap density, interface state density, as well as leakage current density-electric field characteristic of the investigated GaxCeyOz passivation layer on 4H–SiC substrate was presented in this work.

Defect generation and recovery in high-k HfO2/SiO2/Si stack fabrication

The defect generation and recovery are studied in a high-k HfO2/SiO2/Si stack for MOSFETs, at each fabrication step. The stack is fabricated in a well-established manner, via chemical oxidation for a SiO2 interfacial layer and atomic layer deposition for a HfO2 layer, followed by post-deposition annealing (PDA), O2 plasma treatment, and forming gas annealing (FGA). Throughout the fabrication, the carrier lifetime is measured for monitoring the defects in the stack. The measurements indicate that the defects are generated by the HfO2/SiO2 stack formation as well as PDA and O2 plasma treatment, whereas those defects are mostly recovered by FGA.

Experimental investigation of time dependent dielectric breakdown and failure mechanism for Hf0.5Zr0.5O2 ferroelectric field effect transistors

The experimental investigation of the time dependent dielectric breakdown (TDDB) was performed to study the dielectric breakdown mechanisms for Hf0.5Zr0.5O2 (HZO) ferroelectric field-effect transistors (FeFETs) with the SiO2 interfacial layer (IL). Constant voltage stress method combined with the TCAD device simulation was used to study the breakdown mechanism of the TaN/HZO/SiO2/Si gate stack. Due to the much higher electric field in the IL, the breakdown of the SiO2 IL is the major reason for the breakdown of the gate stack. In addition, it is found that the IL breakdown will speed up the disappearance of the memory window (MW), leading to the malfunction of the FeFET as a storage device. Finally, the Weibull distributions of time-to-breakdown (TBD) and charge-to-breakdown (QBD) were characterized, revealing decent TDDB performance of the FeFETs. Careful design of IL thickness is necessary to balance the tradeoff between the device performance and the reliability lifetime of HZO FeFETs.

Synergistic Approach of Interfacial Layer Engineering and READ-Voltage Optimization in HfO2-Based FeFETs for In-Memory-Computing Applications.

This article reports an improvement in the performance of the hafnium oxide-based (HfO2) ferroelectric field-effect transistors (FeFET) achieved by a synergistic approach of interfacial layer (IL) engineering and READ-voltage optimization. FeFET devices with silicon dioxide (SiO2) and silicon oxynitride (SiON) as IL were fabricated and characterized. Although the FeFETs with SiO2 interfaces demonstrated better low-frequency characteristics compared to the FeFETs with SiON interfaces, the latter demonstrated better WRITE endurance and retention. Finally, the neuromorphic simulation was conducted to evaluate the performance of FeFETs with SiO2 and SiON IL as synaptic devices. We observed that the WRITE endurance in both types of FeFETs was insufficient to carry out online neural network training. Therefore, we consider an inference-only operation with offline neural network training. The system-level simulation reveals that the impact of systematic degradation via retention degradation is much more significant for inference-only operation than low-frequency noise. The neural network with FeFETs based on SiON IL in the synaptic core shows 96% accuracy for the inference operation on the handwritten digit from the Modified National Institute of Standards and Technology (MNIST) data set in the presence of flicker noise and retention degradation, which is only a 2.5% deviation from the software baseline.

Effects of post‐deposition annealing of cerium oxide passivation layer in nitrogen‐oxygen‐nitrogen ambient

Effects of post-deposition annealing temperature (400°C, 600°C, 800°C and 1000°C) onto metal-organic decomposed cerium oxide (CeO2) precursor spin-coated on n-type Si substrate was carried out in nitrogen-oxygen-nitrogen ambient. The capability of nitrogen to inhibit further oxidation of the Si surface by attaching to the oxygen vacancies sites was reported. Excessive formation of SiO2 interfacial layer however occurred at 1000°C, surpassing the thickness of the CeO2 passivation layer, leaving behind nitrogen dangling bonds that were inefficient in restricting further oxidation of the Si surface, and hence a permanent dielectric breakdown happened at an electric field of 0.98 MV/cm. The CeO2 passivation layer annealed at 800°C broke down at 4.85 MV/cm and possessed relatively low Dit, Qeff, and slow trap density with negligible formation of interfacial layer, which promoted its use as a promising high k passivation layer.

Wake-up-free properties and high fatigue resistance of HfxZr1−xO2-based metal–ferroelectric–semiconductor using top ZrO2 nucleation layer at low thermal budget (300 °C)

Ferroelectricity and crystallinity of TiN/ZrO2/HfxZr1−xO2 (Hf:Zr = 0.43:0.57; HZO)/SiO2/Si metal–ferroelectric–semiconductor (MFS) capacitors with a top ZrO2 nucleation layer fabricated by low-temperature processes at 300 °C of atomic layer deposition and post-metallization annealing (PMA) were systematically investigated. The HZO (10 nm)-based MFS capacitors without (w/o) and with 2- and 10-nm-thick ZrO2 films (ZrO2-2 nm and ZrO2-10 nm, respectively) were found to form an extremely thin SiO2 interfacial layer (SiO2-IL) with a thickness of one or two monolayers. The HZO film in the TiN/ZrO2/HZO/SiO2/Si capacitors formed the ferroelectric orthorhombic phase even with a low thermal budget of 300 °C; in contrast, that of the w/o capacitor exhibited a predominantly amorphous structure. This result is attributed to the polycrystalline ZrO2 film acting as a nucleation layer for the crystallization of an amorphous HZO film during PMA treatment. Therefore, the remnant polarization (2Pr) increased in the order of w/o (2.2 µC/cm2) &amp;lt; ZrO2-2 nm (6.8 µC/cm2) &amp;lt; ZrO2-10 nm (15 µC/cm2). The endurance properties of the ZrO2-10 nm capacitor were free from the wake-up effect and exhibited less degradation because of the insertion of a thick ZrO2 film of 10 nm at the TiN/HZO interface, which promoted the preferential formation of the ferroelectric orthorhombic phase and prevented the formation of oxygen vacancies at the ZrO2/HZO interface. These results suggest that superior ferroelectricity with wake-up-free properties and higher fatigue resistance of HZO-based MFS capacitors can be achieved by a low-temperature fabrication technique (300 °C) using a top ZrO2 nucleation layer.

Study of gate current in advanced MOS architectures

We have carried out a comprehensive study of the gate current (IG) in advanced MOS architectures for different gate lengths and cross-section areas using an in–house simulation tool. We have considered only direct tunneling under the assumption that trap concentration and therefore the trap assisted current would be small in a matured technology. We have also studied the impact of the interfacial (IL) SiO2 layer on the gate current in the high-κ gate stack. Our results suggest that IL leads to an increase in the gate current for equivalent EOT. They also highlight that reduction in the cross-section area leads to a significant increase in the IG.

Interface state-dependent synaptic characteristics of Pt/CeO2/Pt memristors controlled by post-deposition annealing

Artificial synapses with analog resistance changes have been actively investigated since they are essential elements in brain-inspired neuromorphic systems. In this study, interface state-dependent artificial synaptic characteristics of analog, linear, and symmetric synaptic weight update are demonstrated in Pt/CeO2/Pt memristors controlled by post-deposition annealing of CeO2 layer. The devices with optimized annealing temperature, i.e., 400 and 500 °C-annealed devices, show reliable and analog-type resistance decrease upon applying positive voltage, and vice versa upon applying negative voltage. The resistance change emulates wide-range, linear, and symmetric potentiation and depression behaviors, as being tunable by the number of pulses and its amplitude. It also exhibits short-term and long-term plasticity with respect to pulse conditions. The conduction modes are fitted well with Schottky conduction controlled by interface energy barrier. In addition, negligible resistance changes are observed in reference device with SiO2 interfacial layers inserted at top and bottom Pt/CeO2 interfaces, i.e., Pt/SiO2/CeO2/SiO2/Pt device, supporting that the resistance change is associated with tunable Pt/CeO2 interface states. It is concluded that the resistance change is induced by voltage-driven tuning of Pt/CeO2 interface states, and the control of these interfaces is crucial for reliable synaptic operations.

Boost of orthorhombic population with amorphous SiO2 interfacial layer—a DFT study

Via the density functional theory, the phase diagrams of HZO thin film in MFM (M = TiN, F = HZO) and MFI (I = α-SiO2) structures are constructed with dependences on grain size and temperature. In both MFM and MFI, the region for orthorhombic phase (o-phase) in phase diagram grows when HZO thickness gets thinner. Comparing to MFM, HZO/α-SiO2 interface in MFI suppresses the growth of tetragonal phase (t-phase) to the region of very small grain size ∼1.2 nm. The simulation results agree with the experimental observation by Cheema et al, that the enhanced FE property was obtained in a MFIS (S = silicon) device with ultrathin HZO film (<2 nm). Simulation model indicates more chemical bonds forming between HZO and α-SiO2 interface could stabilize o-phase to greatly enhance the FE property in a MFIS device.

Dipole formation and electrical properties of high-k/SiO2 interface according to the density of SiO2 interfacial layer

The effect of SiO₂ buffer layers with various atomic densities on the interface dipole of high-k/SiO2 is confirmed. An ultrathin SiO₂ layer is formed on Si using the plasma-enhanced chemical vapor deposition (PECVD), H2O2 oxidation and nitric acid oxidation (NAOS). The atomic density ratio between the SiO2 layer with various methods and the high-k is calculated respectively. As the oxygen density of the SiO2 increased, the amount of the dipole and the flatband voltage (VFB) shift decreased. Furthermore, leakage current density of the H2O2 (0.9 × 10−2 A/cm2) due to the formation of low-density SiO2, decreases by approximately six orders of magnitude when SiO2 buffer layer is inserted using the NAOS (5.13 × 10-8 A/cm2). Consequently, it is demonstrated that the dipoles that affects the VFB shift is formed by the diffusion of oxygen ions between the high-k and SiO2 interface, which has a significant effect of the MOS capacitor.

Investigating the physicochemical response of CdS quantum-dots deposition over SiO2-incorporated TiO2 photoanodes for solar cells

There have been many attempts to enhance the performance of quantum-dot-sensitized solar cells (QDSCs) using various interfacial layers (ILs) which served as a passivation layer (PL), seed layer (SL), or blocking layer (BL), separately. Recent works revealed the tendency of these ILs to perform for multiple effects concomitantly, which need to be explored in depth to make used of QDSCs optimally. Herein, we deposited a SiO2 IL via successive ionic layer deposition and reaction (SILAR) method on a thin/mesoporous substrate, revealing the physichochemical influence of SiO2 IL in terms of enhanced deposition of CdS QDs as well as barricaded charge carrier recombination. Scanning electron- and atomic force- microscopic (AFM) techniques were used to affirm the aforementioned increase in QDs deposition while AFM coupled with contact angle measurements and electrochemical investigation (CV and EIS) confirmed the improved electrochemical response of SiO2 IL, which is speculated to originate increased performance (i.e. power conversion efficiency) of QDSCs.