Interfacial SiO2 Layer Research Articles

Effects of post-metallisation annealing on surface–interfacial and electrical properties of HfO2/Ge stacks modified in situ with SiO2 interfacial layer

The effects of post-metallisation annealing (PMA) at 400 °C for 30 min in an NH3 ambient on the interfacial and electrical properties of a structure consisting of a Ge substrate coated with HfO2 by atomic layer deposition with a 3-nm-thick SiO2 interfacial layer formed in situ by a sputtering technique were evaluated. X-ray diffraction and x-ray photoelectron spectroscopy analyses confirmed the crystallinity of HfO2 and chemical bonding of the HfO2/SiO2/Ge interface before and after the annealing. Clear stretch-free distinct capacitance–voltage curves were observed for the sample after the PMA. According to the electrical measurements, the sample after the PMA exhibited a large dielectric constant (k ̃ 17), low interface trap density (Dit = 1.8 × 1012 cm2 eV−1), and small oxide charge (Qeff = 2.54 × 1012 cm2 eV−1). The gate leakage current of the PMA device determined using the current–voltage curve was approximately 0.1 × 10−4 A cm−2 at Vg+ = +1 V. These results suggest that the SiO2 interfacial layer formed in situ and NH3−PMA significantly improved the structural, interfacial, and electrical characteristics of the HfO2/Ge stacks for future Ge-based complementary metal–oxide–semiconductor device applications.

Silicon surface passivation by transparent conductive zinc oxide

Surface passivation is essential for high-efficiency crystalline silicon (c-Si) solar cells. Despite the common use of transparent conductive oxides (TCOs) in the field of solar cells, obtaining surface passivation by TCOs has thus far proven to be particularly challenging. In this work, we demonstrate outstanding passivation of c-Si surfaces by highly transparent conductive ZnO films prepared by atomic layer deposition. Effective surface recombination velocities as low as 4.8 cm/s and 11 cm/s are obtained on 3 Ω cm n- and p-type (100) c-Si, respectively. The high levels of surface passivation are achieved by a novel approach by using (i) an ultrathin SiO2 interface layer between ZnO and c-Si, (ii) a sacrificial Al2O3 capping layer on top of the ZnO film during forming gas annealing, and (iii) the extrinsic doping of the ZnO film by Al, B, or H. A combination of isotope labeling, secondary-ion mass spectrometry, and thermal effusion measurements showed that the sacrificial Al2O3 capping layer prevents the effusion of hydrogen from the crystalline ZnO and the underlying Si/SiO2 interface during annealing, which is critical in achieving surface passivation. After annealing, the Al2O3 capping layer can be removed from the ZnO film without impairing the high levels of surface passivation. The surface passivation levels increase with increased doping levels in ZnO, which can be attributed to field-effect passivation by a reduction in the surface hole concentration. The ZnO films of this work are suitable as a transparent conductor, an anti-reflection coating, and a surface passivation layer, which makes them particularly promising for simplifications in future solar cell manufacturing.

Control of tunneling gap between nanocrystals by introduction of solution processed interfacial layers for wearable sensor applications

In this study, we introduce a strategy to introduce solution-processed interfacial layers in nanocrystal (NC) thin films to fabricate high-performance strain sensors. SiO2 interfacial layers are chemically introduced in ligand-exchanged Ag NC thin films to increase the tunneling gap or inter-particle distance between each Ag NC. In this way, the charge-transport mechanism is manipulated, leading to unique electromechanical properties with a high gauge factor. All solution-processed strain gauge sensors with high stability, durability, and sensitivity are fabricated. The sensor successfully measured delicate movements such as finger motions, demonstrating its possible application in electronic skin.

Improved Interface and Electrical Properties by Inserting an Ultrathin SiO2 Buffer Layer in the Al2O3/Si Heterojunction

AbstractAn ultrathin SiO2 interfacial buffer layer is formed using the nitric acid oxidation of Si (NAOS) method to improve the interface and electrical properties of Al2O3/Si, and its effect on the leakage current and interfacial states is analyzed. The leakage current density of the Al2O3/Si sample (8.1 × 10−9 A cm−2) due to the formation of low‐density SiOx layer during the atomic layer deposition (ALD) process, decreases by approximately two orders of magnitude when SiO2 buffer layer is inserted using the NAOS method (1.1 × 10−11 A cm−2), and further decreases after post‐metallization annealing (PMA) (1.4 × 10−12 A cm−2). Based on these results, the influence of interfacial defect states is analyzed. The equilibrium density of defect sites (Nd) and fixed charge density (Nf) are both reduced after NAOS and then further decreased by PMA treatment. The interface state density (Dit) at 0.11 eV decreases about one order of magnitude from 2.5 × 1012 to 7.3 × 1011 atoms eV−1 cm−2 after NAOS, and to 3.0 × 1010 atoms eV−1 cm−2 after PMA. Consequently, it is demonstrated that the high defect density of the Al2O3/Si interface is drastically reduced by fabricating ultrathin high density SiO2 buffer layer, and the insulating properties are improved.

Remote Phonon Scattering in Two-Dimensional InSe FETs with High-κ Gate Stack.

This work focuses on the effect of remote phonon arising from the substrate and high-κ gate dielectric on electron mobility in two-dimensional (2D) InSe field-effect transistors (FETs). The electrostatic characteristic under quantum confinement is derived by self-consistently solving the Poisson and Schrödinger equations using the effective mass approximation. Then mobility is calculated by the Kubo–Greenwood formula accounting for the remote phonon scattering (RPS) as well as the intrinsic phonon scatterings, including the acoustic phonon, homopolar phonon, optical phonon scatterings, and Fröhlich interaction. Using the above method, the mobility degradation due to remote phonon is comprehensively explored in single- and dual-gate InSe FETs utilizing SiO2, Al2O3, and HfO2 as gate dielectric respectively. We unveil the origin of temperature, inversion density, and thickness dependence of carrier mobility. Simulations indicate that remote phonon and Fröhlich interaction plays a comparatively major role in determining the electron transport in InSe. Mobility is more severely degraded by remote phonon of HfO2 dielectric than Al2O3 and SiO2 dielectric, which can be effectively insulated by introducing a SiO2 interfacial layer between the high-κ dielectric and InSe. Due to its smaller in-plane and quantization effective masses, mobility begins to increase at higher density as carriers become degenerate, and mobility degradation with a reduced layer number is much stronger in InSe compared with MoS2.

Annealing-induced evolution in interface stability and electrical performance of sputtering-driven rare-earth-based gate oxides

Annealing temperature-dependent ultrathin Dy2O3 gate dielectric films, grown on Si substrates by reactive sputtering, were characterized in terms of structural, optical and electrical properties using x-ray diffraction (XRD), x-ray photoelectron spectroscopy (XPS), UV–Vis transmission spectroscopy and electrical measurements of Dy2O3/Si gate stack. Additionally, the thickness of the interfacial SiO2 layer during the deposition and annealing process has been calculated using the Si 2p XPS spectra to exclude its influence on the electrical parameter of Dy2O3 films. XPS analyses for all the samples have shown the abrupt growth of the Dy-silicate for 700°C-annealed sample, which is identified as the primary reason for the dramatic reduction in its electrical performance. In addition, optimized Dy2O3 sample with annealed temperature at 600 °C exhibits the lowest equivalent oxide thickness of 1.6 nm, the highest dielectric constant 16.8, the lower leakage current density 4.45 × 10−8 A/cm2 and the lower frequency dispersion of 6.21%. Based on the experimental analysis, the optimized annealing temperature has been obtained to achieve Dy2O3 gate dielectric thin films as deposition of high-k with high-quality on Si substrates.

In Situ SiO2 Passivation of Epitaxial (100) and (110)InGaAs by Exploiting TaSiO x Atomic Layer Deposition Process.

In this work, an in situ SiO2 passivation technique using atomic layer deposition (ALD) during the growth of gate dielectric TaSiOx on solid-source molecular beam epitaxy grown (100)InxGa1–xAs and (110)InxGa1–xAs on InP substrates is reported. X-ray reciprocal space mapping demonstrated quasi-lattice matched InxGa1–xAs epitaxy on crystallographically oriented InP substrates. Cross-sectional transmission electron microscopy revealed sharp heterointerfaces between ALD TaSiOx and (100) and (110)InxGa1–xAs epilayers, wherein the presence of a consistent growth of an ∼0.8 nm intentionally formed SiO2 interfacial passivating layer (IPL) is also observed on each of (100) and (110)InxGa1–xAs. X-ray photoelectron spectroscopy (XPS) revealed the incorporation of SiO2 in the composite TaSiOx, and valence band offset (ΔEV) values for TaSiOx relative to (100) and (110)InxGa1–xAs orientations of 2.52 ± 0.05 and 2.65 ± 0.05 eV, respectively, were extracted. The conduction band offset (ΔEC) was calculated to be 1.3 ± 0.1 eV for (100)InxGa1–xAs and 1.43 ± 0.1 eV for (110)InxGa1–xAs, using TaSiOx band gap values of 4.60 and 4.82 eV, respectively, determined from the fitted O 1s XPS loss spectra, and the literature-reported composition-dependent InxGa1–xAs band gap. The in situ passivation of InxGa1–xAs using SiO2 IPL during ALD of TaSiOx and the relatively large ΔEV and ΔEC values reported in this work are expected to aid in the future development of thermodynamically stable high-κ gate dielectrics on InxGa1–xAs with reduced gate leakage, particularly under low-power device operation.

Au-nanoparticles doped SiO2 interfacial layer to promote the photovoltaic characteristics of Au/p-Si/Al solar cells

The Au/Au(NPs) doped SiO2/p-Si/Al heterojunction solar cell was achieved. The interfacial insulator layer of SiO2 was, successfully, grown on p-Si (111) wafer using the thermal evaporating technique. The Au-nanoparticles (NPs in the range of 20–85 nm) were well dispersed on the amorphous matrix structure of SiO2 film using flash evaporation method. The structural morphology of the film was investigated using field emission scanning electron microscopy. Some aspects of impedance spectroscopy of the solar cells were studied and in light of which; Nyquist spectra for the complex impedance of the cells were recorded at various frequency (100 KHz −3 MHz). The radii of the semi-circles of the Nyquist plot decreased with increasing the frequency. The capacitance-voltage (C–V) and conductance-voltage (G-V) characteristics were measured. The heterojunction cell showed the negative-capacitance behavior at certain frequencies. Moreover, the current-voltage (I–V) characteristics in dark and under illumination were also studied from which, the electronic transport mechanisms through the solar cell were evaluated. Some important parameters of the junction, such as the ideality factor, barrier height carrier, series and shunt resistances were extracted from the I–V curves. The photovoltaic behavior of the Au(NPs) doped SiO2/p-Si solar cell was evaluated and showed good performance. The photovoltaic parameters of the fabricated solar cell such as: open circuit voltage, short circuit current, fill factor and conversion efficiency were calculated as 0.46 V, 5.4 mA, 0.68 and 5.28%, respectively.

Effect of the interfacial (low-k SiO2 vs high-k Al2O3) dielectrics on the electrical performance of a-ITZO TFT

In this work, the effect of an interfacial low-k dielectric layer such as SiO2 was suggested along with the effect of an interfacial high-k dielectric layer such as Al2O3 on the electrical characteristics and then the electrical properties of the a-ITZO TFT such as the equivalent oxide thickness (EOT) of gate dielectric, gate capacitance per unit area ( $${C_{\text{i}}}$$ ), on-current ( $${I_{{\text{on}}}}$$ ), on–off current ( $${I_{{\text{on}}}}/{I_{{\text{off}}}}$$ ) ratio and field-effect mobility ( $${\mu _{{\text{FE}}}}$$ ) of the a-ITZO TFT. The main purpose of this study is to conduct a comparative study to highlight the impact of the interfacial high-k dielectrics such as Al2O3, compared to low-k SiO2, the existing between the a-ITZO active layer and high-k HfO2 layer in a-ITZO TFT based on the double-layered dielectric. Therefore, the several analyses were implemented through numerical simulation of the device by the Silvaco TCAD Atlas software that was used to carry out a detailed numerical analysis for investigating the relationship between different types of the interfacial (low-k and high-k)dielectric oxides and the performance of a-ITZO TFT. The results showed that TFT based on the double-layered dielectric (Al2O3/HfO2) with a physical thickness ( $${\text{PT}}=30\,{\text{nm}}$$ ) it can provide good electrical properties ( $${\text{EOT}}=6.33\,{\text{nm}}$$ , $${C_{\text{i}}}=5.45 \times {10^{ - 7}}\,{\text{F}}\,{\text{c}}{{\text{m}}^{ - 2}}$$ , $${I_{{\text{on}}}}=1.61 \times {10^{ - 5}}\,{\text{A}}$$ , $${I_{{\text{on}}}}/{I_{{\text{off}}}}=1.56 \times {10^9}$$ and $${\mu _{{\text{FE}}}}=24.11\,{\text{c}}{{\text{m}}^2}\,{{\text{V}}^{ - 1}}\,{{\text{s}}^{ - 1}}$$ ) better than the properties provided by TFT based on the double-layered dielectric (SiO2/HfO2) for the same physical thickness ( $${\text{EOT}}=12.23\,{\text{nm}}$$ , $${{\text{C}}_{\text{i}}}=2.82 \times {10^{ - 7}}\,{\text{F}}\,{\text{c}}{{\text{m}}^{ - 2}}$$ , $${I_{{\text{on}}}}=8.54 \times {10^{ - 6}}\,{\text{A}}$$ , $${I_{{\text{on}}}}/{I_{{\text{off}}}}=8.27 \times {10^8}$$ and $${\mu _{{\text{FE}}}}=29.31\,{\text{c}}{{\text{m}}^2}\,{{\text{V}}^{ - 1}}\,{{\text{s}}^{ - 1}}$$ ). However, we cannot neglect the fundamental role of the interfacial low-k SiO2 layer between the channel and the high-k dielectric, which has some beneficial qualities with regard to the carrier mobility in the transistor channel. In addition, although there is a difference in the value of leakage between the two devices, its effect is very poor on the performance of the device and its reliability, especially for low gate tensions.

Comparision of in situ spectroscopic ellipsometer and ex situ x-ray photoelectron spectroscopy depth profiling analysis of HfO2/Hf/Si multilayer structure

A HfO2 film was grown by RF magnetron sputtering technique on a Si substrate Using in situ Spectroscopic Ellipsometry (SE), the film thickness and refractive index were examined as a function of deposition time. Ex situ x-ray Photoelectron Spectroscopy (XPS) was used in depth profile mode to determine the phase evolution of HfO2/Hf/Si multilayer structure after the growth process. The chemical composition and the crystal structure of the film were investigated by Fourier Transform Infrared (FTIR) spectroscopic measurements and x-ray Diffraction in Grazing Incidence (GI-XRD) mode, respectively. The results showed that the film was grown in the form of HfO2 film. According to SE analysis, reactive deposition of HfO2 directly on Hf/Si results to SiO2 interface of about 2 nm. The final HfO2 films thickness is 5.4 nm. After a certain period of time, the XPS depth profile revealed that the film was in the form of Hf-rich Hf silicate with SiO2 interfacial layer. In reference to XPS quantification analysis from top to bottom of film, the atomic concentration of Hf element reduces from 19.35% to 7.13%, whereas Si concentration increases from 22.99% to 74.89%. The phase change of HfO2 film with time is discussed in details.

Improvement of Inter-face Layer Coating by Plasma Treatment of Carbon Fiber for Carbon Fiber Reinforced Silicon Carbide Composite Applications

Carbon fiber (CF) reinforced SiC (CF/SiC) composites are sought for high temperature application in areas of automobiles, aerospace and nuclear reactors due to their outstanding properties. However, CF/SiC composites have low durability owing to oxidation of CF upon air-exposure during high temperature applications. The inter-phase layer between fiber and SiC matrix is used in order to protect fiber from oxidation. Here, we have aimed to study the effect of air RF (13.56 MHz) plasma treatment on CF tow for improvement of SiO2 inter-face layer coating by dip coating technique. The air RF (13.56 MHz) plasma treatments on CF tows and graphite proxy substrates (for 20, 40 and 60 min) have been analyzed by Scanning Electron Microscopy (SEM) and contact angle measurement, respectively confirmed the enhancement of wettability. Such plasma treated CF tows have been further used for deposition of SiO2 coating and uniform deposition has been achieved for 20 min plasma treated CF as evident from SEM surface analysis. Whereas, Energy Dispersive X-ray Analysis (EDXA) and Fourier Transform Infra-Red spectroscopy (FTIR) measurements have been used to get elemental and bonding information of coated silicon substrates confirmed the high quality of SiO2 coating. While tensile strength measurement verified the enhancement of tensile strength for plasma treated SiO2 coated CF tows as compare to untreated CF tow, and optimum strength (1449 MPa) has been obtained for 20 min plasma treated SiO2 coated CF tow with uniform coating properties. Hence, 20 min plasma treatment on CF tow is confirmed the beneficial effect on SiO2 inter-face layer coating for CF/SiC Composites Applications.

Advanced Millisecond Annealing Approaches for High-k Metal Gate and Contact Scaling

Scaling of semiconductor devices over past decades has been made possible by continuous innovations in materials engineering as well as device geometries and integration [1,2]. Shrinking device features necessitate precise engineering of various materials and interfaces. Thermal processing plays a key role in engineering of ever-evolving materials and processes governed by thermodynamics and kinetics. High-k metal gate (HKMG) and contact to source-drain present key challenges in meeting device performance and yield requirements for continued logic CMOS scaling. In this paper, we will present equipment and process innovations in millisecond annealing that enable HKMG and source-drain contact scaling. Key requirements for HKMG architecture include EOT scaling, device reliability, maintaining desired effective work function, and minimal Vfb roll-off effect. Thermal treatment of HKMG film stack leads to HfO2 crystallization, reaction of HfO2 with the SiO2 interface layer (IL), diffusion of nitrogen (N) and reaction with HfO2, and displacement of oxygen vacancies from HfO2. In addition, nitridation of HfO2 suppresses charge traps, improving reliability. Nitrogen placement in the HKMG stack is a function of annealing conditions, and needs to be controlled precisely to meet device performance and reliability requirements. HKMG integration can benefit greatly from millisecond annealing that offers high temperature processing but in millisecond time scales. In this paper, we will introduce millisecond annealing in ammonia (NH3) ambient. We will demonstrate that millisecond annealing in NH3 ambient offers unique capabilities in controlling the N dose and placement in the HKMG stack. It is extremely important to control the N profile since N penetration to the interface layer degrades PMOS reliability. Fig 1 shows the three film stacks investigated in this work. Millisecond annealing was performed using a scanning continuous wave laser to reach desired surface temperature of a wafer placed on a heated stage. This approach allows for millisecond scale control of thermal energy delivery to the wafer. Fig 2 shows the N concentration as a function of millisecond anneal peak temperature for different heater temperatures. N incorporation increases with peak temperature. Lower heater temperature enables higher N incorporation. As shown in Fig 3, lower heater temperature also results in lesser IL thickening, which is desirable for EOT scaling. Fig 4 shows angle-resolved X-Ray Photoelectron Spectroscopy (AR-XPS) profiles for HfO2/IL film stack annealed at the same peak temperature but with different heater temperatures. Clearly, lower heater temperature leads to shallower, Gaussian-like N profile contained within HfO2. In this paper, we will also demonstrate nitridation of other HKMG film stacks such as TiN/HfO2/IL, and TaN/HfO2/IL with excellent control over N dose and depth profile. We will show that this approach leads to conformal nitridation of HKMG film stack. We will also present MOSCAP data complementing the physical characterization and demonstrating device performance and reliability benefits of millisecond annealing in NH3 ambient. Continued CMOS scaling requires geometric shrinking of device features such as contact to source and drain. Smaller contact dimensions necessitate reduction of bulk and interface resistivity of various materials deposited in the contact structure. Advanced logic devices beyond 10nm node are expected to use Cobalt as contact fill metal [3]. Oxidation of barrier TiN is detrimental to the quality of subsequent Cobalt metal fill and introduces an additional contributor to the overall external resistance of the device. Silicidation anneal after Ti liner/TiN barrier deposition results in oxidation of TiN surface due to the presence of trace amounts of O2 in the anneal chamber. Hence, it is paramount to minimize surface oxidation of TiN to enable optimal contact metal fill. In this paper, we will demonstrate that TiN oxidation can be minimized by improving millisecond anneal chamber background O2 level and cooling down wafers in controlled ambient. The importance of ambient control during silicide anneal was investigated by comparing surface oxidation resulting from annealing with various ambient control schemes. Fig. 5 shows that a silicide anneal run with X ppm ambient O2 during the anneal resulted in significant oxidation of TiN, and oxidation was reduced with reduced ambient O2 during anneal. The least degree of TiN oxidation was achieved with improved ambient control during both the anneal process and wafer cooldown. Improvement in chamber O2 level along with cooler wafer extraction also resulted in better Co adhesion to TiN and ~17% reduction in contact resistivity (Fig 6). Enhanced ambient control capability in the millisecond anneal system is expected to provide further benefits in HKMG EOT scaling and reliability in combination with NH3 thermal processing. Figure 1

Optical band gap analysis and modeling for ultra-thin high-k dielectrics in high-k/metal gate transistors

A highly precise band gap measurement based on deep UV spectroscopic ellipsometry along with Bruggeman effective model approximation was developed for high-k/metal gate CMOS with ultrathin EOT (<1.5 nm). By applying and comparing the measurement for HfO2 on SiO2 and SiON interfacial layers with different thicknesses, N%, and annealing conditions, two new sub band gap states corresponding to nitrogen in the film are observed. Together with X-ray photoelectron spectroscopy and electrical measurements, it is found that the band gap energies can be correlated to N% and the leakage current of the high-k films by linear regression (R2 = 0.95). This indicates that the method is capable of quantifying physical and electrical properties of high-k dielectrics, and therefore a time consuming physical analysis or expensive electrical test on fully built devices for gate dielectrics can be avoided.

Effect of interfacial layer on device performance of metal oxide thin-film transistor with a multilayer high-k gate stack

The amorphous indium gallium zinc oxide thin-film transistors (TFTs) with a multilayer high-k gate stack are investigated in this research. In order to achieve a high quality gate insulator for plastic flexible display application, the multilayer high-k gate stacks (SiO2/TiO2/HfO2) are deposited by a low-temperature physical vapor deposition (PVD) process. On the other hands, an interfacial layer between the high-k stack and metal oxide channel is important for the device performance. The effects of interfacial layer material (SiO2 or Ga2O3) are also discussed in this report. The devices with SiO2 interfacial layer show a high on/off current ratio of ~7 × 107 for its low gate leakage current, a small sub-threshold swing of 0.093 V/decade and a high field-effect mobility of ∼37.8 cm2/Vs for its good interface condition and low interface defeats. This research shows that the interface engineering of multilayer PVD gate stacks is necessary for oxide TFT fabrication.

Thermal phase separation of ZrSiO4 thin films and frequency- dependent electrical characteristics of the Al/ZrSiO4/p-Si/Al MOS capacitors

In this work, the thermal phase separation and annealing optimization of ZrSiO4 thin films have been carried out. Following annealing optimization, the frequency-dependent electrical characteristics of the Al/ZrSiO4/p-Si/Al MOS capacitors were investigated in detail. The chemical evolution of the films under various annealing temperatures was determined by Fourier transform infrared spectroscopy (FTIR) measurements. The phase separation was determined by x-ray diffraction (XRD) measurements. The electrical parameters were determined via the capacitance–voltage (C–V), conductance–voltage (G/ω) and leakage-current–voltage (Ig–Vg). The results demonstrate that zirconium silicate formations are present at 1000 °C annealing with the SiO2 interfacial layer. The film was in amorphous form after annealing at 250 °C. The tetragonal phases of ZrO2 were obtained after annealing at 500 °C. When the temperature approaches 750 °C, transitions from the tetragonal phase to the monoclinic phase were observed. The obtained XRD peaks after 1000 °C annealing matched the crystalline peaks of ZrSiO4. This means that the crystalline zirconium dioxide in the structure has been converted into a crystalline silicate phase. The interface states increased to 5.71 × 1010 and the number of border traps decreased to 7.18 × 1010 cm−2 with the increasing temperature. These results indicate that an excellent ZrSiO4/Si interface has been fabricated. The order of the leakage current varied from 10−9 Acm−2 to 10−6 Acm−2. The MOS capacitor fabricated with the films annealed at 1000 °C shows better behavior in terms of its structural, chemical and electrical properties. Hence, detailed frequency-dependent electrical characteristics were performed for the ZrSiO4 thin film annealed at 1000 °C. Very slight capacitance variations were observed under the frequency variations. This shows that the density of frequency-dependent charges is very low at the ZrSiO4/Si interface. The barrier height of the device varies slightly from 0.776 eV to 0.827 eV under frequency dispersion. Briefly, it is concluded that the devices annealed at 1000 °C exhibit promising electrical characteristics.

Study of Lanthanum Diffusion in HfO2-Based High-k Gate Stack

La2O3 has been selected as a threshold voltage (Vt) tuning material for advanced nodes because of its uniqueness of reducing effective work function towards NFET band edge by creating dipoles at SiO2/HfO2 interface [1,2]. In this paper, we study the factors which influence the diffusion of Lanthanum (La) atoms through HfO2 during anneal. These factors include: (1) Crystallization state of HfO2; (2). HfO2 thickness; (3) Drive-in anneal temperature; (4) TiN capping material during drive-in anneal. We prepare the following stack: Si/SiO2/ HfO2/ La2O3 /TiN/a-Si, and anneal the stack to diffuse the La atoms into HfO2 layer. Then a-Si, cap TiN and excessive La2O3 were sequentially removed by wet etch. Final structure Si/SiO2/La-doped HfO2 is measured by XPS/XRF to determine the amount of La atoms that were diffused in. The diffusion of La is governed by its initial dosage (La2O3 deposition thickness), its adjacent layers (bottom HfO2, and top cap TiN), and the annealing temperature. By varying these parameters, we systematically study the effects of each factor, and correlate them to final Vt shift in the devices. The Vt shift in the MOSFET device is found to be proportional to the final diffused La amount in HfO2. The Vt shift shows obvious dependence on initial La dosage, annealing temperature and HfO2 thickness. On the other hand, the crystallization of HfO2 display a surprising blocking effect for La diffusion, indicating that La diffusion doesn’t follow the common grain-boundary diffusion mechanism. We found that HfO2 starts to crystallize when post-deposition anneal temperature is greater than 880C. La diffusion through crystallized HfO2 is significantly reduced compared to the case when HfO2 is still amorphous. On the contrary, Nitrogen atoms, which were incorporated during cap TiN deposition process, shows enhanced diffusion through HfO2. Fig.1 (a) shows the La signal in gate stack prior to and after La diffusion. The final La amount is much less for crystallized HfO2 (Hk PDA temp =900C and 950C) than for amorphous HfO2 (Hk PDA temp =800C and 850C). However, N signal, in Fig.1 (b) shows increased value for crystallized HfO2. Fig. 1(c) (d) show the Vt shift from NFET and PFET devices respectively, confirming less La diffusion (less Vt shift) in crystallized HfO2. The Vt of NFET is reduced while the Vt of PFET is enhanced because of the unipolar nature of the La-Si-O dipoles. We also conducted Angle-resolved XPS (AR-XPS) and TEM/EELS analysis and they both show that in crystallized HfO2, the La distribution is away from HfO2/SiO2 interface, while in amorphous HfO2, more La reside at HfO2/SiO2 interface. The capping material is also crucial for La diffusion in HfO2. We tested two types of TiN: (1) ALD TiN using a metalorganic precusor, tetrakis (dimethylamido) titanium and Nitrogen (TDMAT-TiN), (2) ALD TiN using TiCl4 precursor and NH3 (TiC4-TiN). We observe significant Vt difference between devices using these two TiN materials. The final diffused La is much less for TiC4-TiN based cap than TDMAT-TiN based cap. This is attributed to different La diffusion rate in the capping TiN material which in turn affects the La diffusion into HfO2. In summary, we evaluate the factors that influence La diffusion in HfO2-based Hk gate stack. Both crystallization of HfO2 and the absorption of La in top TiN material have great contributions to the effectiveness of La diffusion in HfO2. Some of these factors for La diffusion are especially intertwined with the growth of SiO2 interfacial layer (IL) which affects the Tinv and Toxgl of the MOSFET devices. Cares have to be taken to engineer the stack structure and integration scheme to achieve desired Vt shift and device performance. REFERENCE: [1] H. N. Alshareef et.al. Appl. Phys. Lett. 89, 232103 (2006) [2] Koji Kita and Akira Toriumi, Appl. Phys. Lett. 94, 132902 (2009) Figure 1

Low Frequency Noise Analysis of Impact of Metal Gate Processing on the Gate Oxide Stack Quality

A review is given about the impact of the metal gate (MG) in a High-κ/Metal Gate (HKMG) stack on the quality and defectivity of the dielectric, assessed by low-frequency (LF) noise spectroscopy. In a first part, processing aspects are discussed, like, the thickness of the MG and the implementation of a gate-last approach. In the latter case, it is shown that both the cleaning (or dummy gate removal), the growth of the interfacial SiO2 layer (chemical versus thermal) and a post-HfO2-deposition heat or SF6 plasma treatment need to be optimized for reducing the gate oxide trap density. In a second part, different MGs are compared from a viewpoint of noise magnitude. It is generally found that alternatives to the standard TiN gate yield better static and noise performance. Results will be presented both for scaled planar and FinFET technologies; the latter fabricated on either bulk or Silicon-on-Insulator (SOI) substrates. Also results on Gate-All-Around NanoWire FETs (GAA NWFETs) fabricated on SOI will be included.

Nitrogen Engineering in the Ultrathin SiO2 Interface Layer of High- ${k}$ CMOS Devices: A First-Principles Investigation of Fluorine, Oxygen, and Boron Defect Migration

The further development of future semiconductor devices necessitates methods for characterization on an atomic scale. This ab initio investigation reveals consequences of nitrogen treatment of the state-of-the-art high- $k$ gate-stacks. The model allows a profound characterization of the SiO2 interface layer for different impurity concentrations. The presented results explain recent experimental observations qualitatively as well as quantitatively. Beyond that, a fundamental understanding is given, which can be used as an essential instrument for future reliability engineering.

Improving interfacial and electrical properties of HfO2/SiO2/p-Si stacks with N2-plasma-treated SiO2 interfacial layer

The effect of N2-plasma-treated SiO2 interfacial layer on the interfacial and electrical characteristics of HfO2/SiO2/p-Si stacks grown by atomic layer deposition (ALD) was investigated. The microstructure and interfacial chemical bonding configuration of the HfO2/SiO2/Si stacks were also examined by high-resolution transmission electron microscopy (HRTEM) and X-ray photoelectron spectroscopy (XPS). Compared with the samples without N2-plasma treatment, it is found that the samples with N2-plasma treatment have less oxygen vacancy density for SiO2 interfacial layer and better HfO2/SiO2 interface. In agreement with XPS analyses, electrical measurements of the samples with N2-plasma treatment show better interfacial quality, including lower interface-state density (D it, 9.3 × 1011 cm−2·eV−1 near midgap) and lower oxide-charge density (Q ox, 2.5 × 1012 cm−2), than those of the samples without N2-plasma treatment. Additionally, the samples with N2-plasma treatment have better electrical performances, including higher saturation capacitance density (1.49 μF·cm−2) and lower leakage current density (3.2 × 10−6 A·cm−2 at V g = V fb − 1 V). Furthermore, constant voltage stress was applied on the gate electrode to investigate the reliability of these samples. It shows that the samples with N2-plasma treatment have better electrical stability than the samples without N2-plasma treatment.

Qualifying ultrathin alumina film prepared by plasma-enhance atomic layer deposition under low temperature operation

Preparation of ultrathin alumina (Al2O3) films through Plasma-Enhanced Atomic Layer Deposition (PE-ALD) at low substrate temperature is discussed. The present work aims to investigate the physical mechanism of the PE-ALD deposition process and also the characteristics of the ultrathin alumina films on silicon 〈100〉 wafer deposited using the technique. The deposition was performed using trimethyl aluminum (Al (CH3)3) as the precursor and argon gas for purging. During deposition, the target temperature was kept constant at ~80, 100 and 150°C and the pressure was ~1.3×10−2Pa. Two deposition cycles were tested, 400 and 800 cycles. As for understanding the process, the films deposited with and without oxygen plasma were compared. Various thin film characterization techniques, including Atomic Force Microscope (AFM), ellipsometry, Raman spectrometry measurement, X-ray diffraction (XRD), and indentation technique, were applied for investigating the film properties. A transmission electron microscope (TEM) equipped with high-angle annular dark-field imaging line scan modes and energy-dispersive X-ray spectroscopy acquisition was used for imaging thin film cross-sections. We found that the number of deposition cycles did not affect the substrate surface roughness as evidenced by AFM images. The mechanical property, the hardness of the film deposited with 800 cycles and plasma was the best. Raman spectroscopy measurements showed that a Al-O-Si phase exists when the films were deposited at 100°C and 150°C for 400 and 800 cycles under oxygen plasma atmosphere. While no Al-O-Si phase existed after the same number of ALD deposition cycle without plasma. Results from XRD measurements indicated that the films deposited at 100°C and 150°C for 400 and 800 cycles under oxygen plasma atmosphere has an Al-O structure. TEM images clearly displayed the interface between the thin films, SiO2 interface layers and Si substrates. As for the sample deposited at 80°C, an Al2O3 film was hardly seen, but when increasing the deposition temperature to 100°C and 150°, films started to build on top of the substrate. However, for all deposition conditions, TEM revealed that the amounts of carbon atoms in the reaction site remained relatively high.