Formation Of Interfacial Oxide Research Articles

SET Kinetics of Ag/HfO2-Based Diffusive Memristors under Various Counter-Electrode Materials

The counter-electrode (CE) material in electrochemical metallization memory (ECM) cells plays a crucial role in the switching process by affecting the reactions at the CE/electrolyte interface. This is due to the different electrocatalytic activity of the CE material towards reduction-oxidation reactions, which determines the metal ion concentration in the electrolyte and ultimately impacts the switching kinetics. In this study, the focus is laid on Pt, TiN, and W, which are relevant in standard chip technology. For these, the influence of CE metal on the switching kinetics of Ag/HfO2-based volatile ECM cells is investigated. Rectangular voltage pulses of different amplitudes were applied, and the SET times were analyzed from the transient curves. The results show that CE material has a significant effect on the SET kinetics, with differences being observed depending on the voltage regime. The formation of interfacial oxides at the CE/electrolyte interface, particularly for non-noble metals, is also discussed in relation to the findings. Overall, this work highlights the important role of the CE material in the switching process of Ag/HfO2-based diffusive memristors and the importance of considering interfacial oxide formation in the design of these devices.

Reaction Mechanisms of Non-hydrolytic Atomic Layer Deposition of Al2O3 with a Series of Alcohol Oxidants

Atomic layer deposition (ALD) of Al2O3 using trimethylaluminum (TMA) and H2O is the most widely and deeply studied ALD process owing to the superior properties of the deposited Al2O3 thin films and usability of TMA and H2O. However, H2O can cause undesirable substrate oxidation during ALD. While previous studies have shown that alcohol oxidants can be used to deposit Al2O3 thin films with less substrate oxidation, the reaction mechanism of ALD Al2O3 with alcohol oxidants has not been elucidated yet. In this study, the reaction mechanism of ALD of Al2O3 thin films using various alcohol oxidants was systematically investigated by computational and experimental methods. Various possible reaction pathways are considered for the oxidation of Al–CH3 with methanol (MeOH), ethanol (EtOH), and propanol (n-PrOH). It is found that the feasible reaction mechanism for removal of the surface-adsorbed alkoxy group is autocatalytic liberation of alkene through β-hydrogen transfer. ALD processes were developed using the alcohol oxidants. Our process using EtOH showed a growth rate of 0.96 Å/cycle and a moderate level of carbon impurities (2.6%). In addition, we investigated the properties of ALD-deposited Al2O3 thin films with alcohol oxidants, which indicated superior electrical properties and decreased formation of interfacial oxide on the Si substrate.

Growth and Characterization of Ternary Hf x Ta y O z Films via Nitrogen-Infused Wet Oxidation.

Nitrogen-infused wet oxidation at different temperatures (400–1000 °C) was employed to transform tantalum–hafnia to hafnium-doped tantalum oxide films. High-temperature wet oxidation at 1000 °C marked an onset of crystallization occurring in the film, accompanied with the formation of an interfacial oxide due to a reaction between the inward-diffusing hydroxide ions, which were dissociated from the water molecules during wet oxidation. The existence of nitrogen has assisted in controlling the interfacial oxide formation. However, high-temperature oxidation caused a tendency for the nitrogen to desorb and form N–H complex after reacting with the hydroxide ions. Besides, the presence of N–H complex implied a decrease in the passivation at the oxide–Si interface by hydrogen. As a consequence, defect formation would happen at the interface and influence the metal–oxide–semiconductor characteristics of the samples. In comparison, tantalum–hafnia subjected to nitrogen-infused wet oxidation at 600 °C has obtained the highest dielectric constant, the largest band gap, and the lowest slow trap density.

Interface between Al2O3 and 4H-SiC investigated by time-of-flight medium energy ion scattering

The formation of interfacial oxides during heat treatment of dielectric films on 4H-SiC has been studied. The 4H-SiC surface has been carefully prepared to create a clean and abrupt interface to Al2O3. An amorphous, 3 nm thick, Al2O3 film has been prepared on 4H-SiC by atomic layer deposition and rapid thermal annealing was then performed in N2O ambient at 700 °C and 1100 °C during 1 min. The samples were studied by time-of-flight medium energy ion scattering (ToF-MEIS), with sub-nanometer depth resolution and it is seen that, at both annealing temperatures, a thin SiOx (1 ⩽ x ⩽ 2) is formed at the interface. Our results further indicate that carbon remains in the silicon oxide in samples annealed at 700 °C. Additional electrical capacitance voltage measurements indicate that a large concentration of interface traps is formed at this temperature. After 1100 °C annealing, both MEIS and XRD measurements show that these features disappear, in accordance with electrical data.

Interfacial Oxide Formation during Anodization of Hafnium/Aluminium Superimposed Layers

The anodization behaviour of Hf/Al stacked thin films, sequentially deposited from vapour phase without breaking vacuum, was investigated using scanning droplet cell microscopy. Surface microstructure and crystallographic analysis revealed the formation of highly textured and compact hexagonal Hf films for thicknesses above 7.5nm. Cyclic voltammetry suggested the formation of discrete anodic layers starting with pure HfO2 on the surface, a mixture of HfO2 and Al2O3 as an intermediate layer and pure Al2O3 in depth of the films. Coulometric investigations revealed oxide formation factors of 2.2nmV−1 for HfO2 while for pure Al2O3 a maximum of 1.4nmV−1 was measured. Electrochemical impedance spectroscopy performed for various Hf thicknesses and different final anodization potentials revealed almost ideal dielectrics formed from mixed HfO2/Al2O3, permittivities up to 26 being measured for the anodized Hf/Al films. Surface analytical investigations and depth profiling as well as high resolution transmission electron microscopy confirmed the discrete anodic layer growth and the mixing of both anodic oxides. The significant thickness values found for the mixed oxide layer must redefine the general expectations for the use of anodized superimposed layers in various applications.

Functional materials integrated on III–V semiconductors

The integration of ferroelectric oxides on semiconductors has been achieved through the use of molecular beam epitaxy and solution spin coating. The oxide layers were determined to be single phase and crystalline and were oriented with the (100) along the growth direction. Epitaxial SrTiO3 and BaTiO3 buffer layers were grown on GaAs and Si using a unique MBE process for nucleation that suppressed the formation of interfacial oxide. The deposition of ferroelectric Pb(Zr)TiO3, on STO buffered Si and GaAs was carried out using solution spin coating. The nucleation of the oxide growth by solution spin coating was promoted by the crystallinity of the surface structure of the SrTiO3 buffer layer. Ab initio Density Functional Theory calculations were used to determine the interfacial structure and band alignments for the STO/GaAs and BTO/GaAs interfaces. Initial electrical characterization of the PZT grown on GaAs was determined by measuring the polarization versus electric field which suggests evidence of ferroelectricity.

Improved thermal stability and electrical properties of atomic layer deposited HfO2/AlN high-k gate dielectric stacks on GaAs

The thermal stability and electrical properties of atomic layer deposited HfO2/AlN high-k gate dielectric stacks on GaAs were investigated. Compared to HfO2/Al2O3 gate dielectric, significant improvements in interfacial quality as well as electrical characteristics after postdeposition annealing are confirmed by constructing HfO2/AlN dielectric stacks. The chemical states were carefully explored by the x-ray photoelectron spectroscopy, which indicates the AlN layers effectively prevent from the formation of defective native oxides at elevated temperatures. In addition, it is found that NH3 plasma during AlN plasma-enhanced atomic layer deposition also has the self-cleaning effect as Al(CH3)3 in removing native oxides. The passivating AlN layers suppress the formation of interfacial oxide and trap charge, leading to the decrease of capacitance equivalent thickness after annealing. Moreover, HfO2/AlN/GaAs sample has a much lower leakage current density of 2.23 × 10−4 A/cm2 than HfO2/Al2O3/GaAs sample of 2.58 × 10−2 A/cm2. For the HfO2/AlN/GaAs sample annealed at 500 °C, it has a lowest interface trap density value of 2.11 × 1011 eV−1 cm−2. These results indicate that adopting HfO2/AlN dielectric stacks may be a promising approach for the realization of high quality GaAs-based transistor devices.

Study on the Effect of Plasma Treatment on Flat-band-voltage and Equivalent Oxide Thickness using Metal-organic Chemical Vapor Deposition TiN Film as p-MOSFETS Metal Gate Electrode

This work aimed to study on the effects of plasma treatment on flat band voltage (Vfb) and equivalent oxide thickness (EOT) using Metal-organic Chemical Vapor Deposition (MOCVD) TiN film as p-MOSFETs metal gate electrode. Theplasma treatment conditions effect on the resistance and composition properties of MOCVD TiN, consequently, they can modulate work function and control threshold voltage. The effects of “plasma treatment” were imposed to favor the formation of Ti-N bonds, thus decreasing the rate Ti-C bond and favoring a crystallized stoichiometric TiN phase to increase PMOS Vfb shift. Meanwhile, plasma treatments accelerate interfacial oxide formation and increase EOT. On the other hand, EOT increases with the increase of plasma treatment time and power in this work, but Vfb does not always increase and reach a max value.

Multi-layer graphene on Co(0001) by ethanol chemical vapor deposition

N layer (1 ⩽ N ⩽ 10) monolayer films of graphene were formed by the chemical vapor deposition of ethanol on either clean or oxidized Co(0001) substrates at 1000 K, with no evidence of either interfacial oxide formation or graphene/substrate charge transfer. Low energy electron diffraction data indicate that the graphene layers or domains are azimuthally rotated, but otherwise show the characteristics of graphene with a Raman spectra D/G intensity ratio of 0.25 or less, and a C 1s binding energy of 284.5 eV with an observable π → π* transition. Magneto optic Kerr effect spectra indicate only the ferromagnetic hysteresis with high remanence, with no evidence of Co/graphene exchange bias. This is very different from the negligible remanent magnetization of graphene/Co3O4/Co trilayer structures.

Metallization strategies for In2O3-based amorphous oxide semiconductor materials

Abstract

Large-scale parallel arrays of silicon nanowires via block copolymer directed self-assembly

Extending the resolution and spatial proximity of lithographic patterning below critical dimensions of 20 nm remains a key challenge with very-large-scale integration, especially if the persistent scaling of silicon electronic devices is sustained. One approach, which relies upon the directed self-assembly of block copolymers by chemical-epitaxy, is capable of achieving high density 1 : 1 patterning with critical dimensions approaching 5 nm. Herein, we outline an integration-favourable strategy for fabricating high areal density arrays of aligned silicon nanowires by directed self-assembly of a PS-b-PMMA block copolymer nanopatterns with a L(0) (pitch) of 42 nm, on chemically pre-patterned surfaces. Parallel arrays (5 × 10(6) wires per cm) of uni-directional and isolated silicon nanowires on insulator substrates with critical dimension ranging from 15 to 19 nm were fabricated by using precision plasma etch processes; with each stage monitored by electron microscopy. This step-by-step approach provides detailed information on interfacial oxide formation at the device silicon layer, the polystyrene profile during plasma etching, final critical dimension uniformity and line edge roughness variation nanowire during processing. The resulting silicon-nanowire array devices exhibit Schottky-type behaviour and a clear field-effect. The measured values for resistivity and specific contact resistance were ((2.6 ± 1.2) × 10(5)Ωcm) and ((240 ± 80) Ωcm(2)) respectively. These values are typical for intrinsic (un-doped) silicon when contacted by high work function metal albeit counterintuitive as the resistivity of the starting wafer (∼10 Ωcm) is 4 orders of magnitude lower. In essence, the nanowires are so small and consist of so few atoms, that statistically, at the original doping level each nanowire contains less than a single dopant atom and consequently exhibits the electrical behaviour of the un-doped host material. Moreover this indicates that the processing successfully avoided unintentional doping. Therefore our approach permits tuning of the device steps to contact the nanowires functionality through careful selection of the initial bulk starting material and/or by means of post processing steps e.g. thermal annealing of metal contacts to produce high performance devices. We envision that such a controllable process, combined with the precision patterning of the aligned block copolymer nanopatterns, could prolong the scaling of nanoelectronics and potentially enable the fabrication of dense, parallel arrays of multi-gate field effect transistors.

Gate Stack Engineering and Thermal Treatment on Electrical and Interfacial Properties of Ti/Pt/HfO2/InAspMOS Capacitors

Effects of gate stack engineering and thermal treatment on electrical and interfacial properties of Ti/Pt/HfO2/InAs metal insulator semiconductor (MIS) capacitors were systematically evaluated in terms of transmission electron microscopy, energy dispersive X-ray spectroscopy, current-voltage, and capacitance-voltage characterizations. A 10 nm thick Pt metal effectively suppresses the formation of interfacial oxide, TiO2, between the Ti gate and HfO2gate dielectric layer, enhancing the gate modulation on the surface potential of InAs. Anin situHfO2deposition onto then-InAs channel with an interfacial layer (IL) of one-monolayer InP followed by a 300°C post-metal-anneal produces a high-quality HfO2/InAs interface and thus unravels the annoying Fermi-level pinning, which is evidenced by the distinct capacitance dips in the high-/low-frequencyC-Vcharacteristics. The interface trap states could be further suppressed by replacing the InP IL by an As-rich InAs, which is substantiated by a gate leakage reduction and a steep voltage-dependent depletion capacitance.

The NH3 Nitridation Effects on a Al2O3 Passivation by Atomic Layer Deposition (ALD) in the HfO2/GaAs Systems

We investigated the nitridation effects on a passivating Al2O3 layer formed by atomic layer deposition (ALD) process at the interface of HfO2/GaAs. Results reveal that formation of Ga-O is suppressed greatly when annealed under NH3 ambient for the HfO2/GaAs system. Moreover if the Al2O3 layer is thick enough, diffusion of Ga into the high-k dielectric is blocked effectively, even after heat treatment at 500oC. This not only suppresses formation of interfacial oxide, but also improves the electrical properties. The nitrogen contents present in NH3 ambient lead to a decrease in the interfacial layer, which in turn decreases the effective oxide thickness (EOT). Results of chemical analyses by x-ray photoelectron spectroscopy (XPS) and micro-structure analyses by high-resolution transmission electron microscopy (HR-TEM) are presented.

The effect of surface treatment on omni-directional efficiency of the silicon solar cells with micro-spherical texture/ITO stacks

A “bottom-up” surface texturing method based on nozzle-sprayed microspheres and spin-coated dielectric film has been proposed. The fill factor was improved by the use of indium tin oxide (ITO) as an antireflection coating (ARC) due to an increased effective area for carrier collection. The pretreatment using HCl prior to ITO deposition was found to suppress the formation of interfacial oxide at the ITO/Si junction. An enhancement in the short-wavelength response (400–600 nm) and an improvement in the short-circuit current ( J SC) were accomplished. The difference in the efficiency (Δ η) between the cells fabricated with ITO incorporating micro-spherical textures (MSTs) and those by KOH texturing was 13.5% at a light incident angle of 60°, comparatively larger than the difference in efficiency of 7.4% observed at normal incidence. These results demonstrate the superior omnidirectional antireflection property of the ITO+MST structure.

Scaling equivalent oxide thickness with flat band voltage (VFB) modulation using in situ Ti and Hf interposed in a metal/high-k gate stack

This study aimed to control the work-functions and scaling equivalent oxide thicknesses (EOTs) of metal-oxide-semiconductor (MOS) devices using an “in situ” thin metal layer interposed between the gate dielectric and the metal gate. The effects of “in situ thin metal layers” were imposed to suppress low-k interfacial oxide formation, leading to a thin EOT (down to 0.5 nm) scaling due to the scavenging of excess oxygen sources through gate stacks and to allow for the tuning of nMOS and pMOS-compatible work-functions using Hf and Ti layers, respectively. Different high-k gate dielectrics (HfO2, HfOxNy), two types of transition metals (Ti, Hf), and various annealing temperature conditions were studied. The EOT became thinner as the thicknesses of the Hf and Ti thin layers increased. However, the thickening Hf cap provided a negative flat band voltage (VFB) shift, while the increasing Ti exhibited a positive VFB shift.

Investigation of the Interface Oxide of Al2O3/HfO2 and HfO2/Al2O3 Stacks on GaAs(100) Surfaces

The physical and the electrical properties of ALD Al2O3/HfO2 and HfO2/Al2O3 stacks on GaAs systems before after heat treatment are investigated. Results reveal that the addition of Al2O3 layers suppresses not only the poly-crystallization of HfO2 even after heat treatment, but also the formation of interfacial oxide. High-resolution transmission electron microscopy (HR-TEM) and X-ray photoelectron spectroscopy (XPS) analysis results are presented.

Plasma Nitridation of HfO2 Gate Dielectric on p-GaAs Substrates

Plasma nitridation (PN) method has been used for nitrogen incorporation in HfO2 based gate dielectrics for future GaAs-based CMOS devices. It has been demonstrated that the introduction of nitrogen in HfO2 on p-GaAs improves the interface quality and bulk oxide properties. X-ray photoelectron spectroscopy and transmission electron microscopy results show that the plasmanitridation of HfO2 effectively suppresses the interfacial oxide formation and elemental out diffusion of As during thermal treatment. Such suppression of out-diffusion led to a substantial enhancement in the overall dielectric properties of the HfO2 film. It has been found that the metal-oxide-semiconductor device characteristics such as interface-state-density, accumulationcapacitance, hysteresis, and leakage current improve for nitrided HfO2 films on p-GaAs. An equivalent-oxide-thickness of 3.5 nm and leakage current density of 10-6 Acm-2 has been achieved at VFB -1 V, for nitrided-HfO2 films. In addition, the effects of nitrogen in HfO2 on band alignments have also been studied.

Characterization of sputtered TiO2 gate dielectric on aluminum oxynitride passivated p-GaAs

Structural and electrical characteristics of sputtered TiO2 gate dielectric on p-GaAs substrates have been investigated. It has been demonstrated that the introduction of thin aluminum oxynitride (AlON) layer between TiO2 and p-GaAs improves the interface quality. X-ray photoelectron spectroscopy and transmission electron microscopy results show that the AlON layer effectively suppresses the interfacial oxide formation during thermal treatment. The effective dielectric constant value is 1.5 times higher for the TiO2∕AlON gate stack compared to directly deposited TiO2 on p-GaAs substrates, with a comparable interface state density. The capacitance-voltage (C-V), current-voltage (I-V) characteristics, and charge trapping behavior of the TiO2∕AlON gate stack under constant voltage stressing exhibit an excellent interface quality and high dielectric reliability, making the films suitable for GaAs based complementary metal-oxide-semiconductor technology.

Characteristics of Nanocomposite ZrO2/Al2O3 Films Deposited by Plasma-Enhanced Atomic Layer Deposition

Nanocomposite ZrO2/Al2O3 (ZAO) films were deposited on Si by plasma-enhanced atomic layer deposition and the film characteristics including interfacial oxide formation, dielectric constant (k), and electrical breakdown strength were investigated without post-annealing process. In both the mixed and nano-laminated ZAO films, the thickness of the interfacial oxide layer (T(IL)) was considerably reduced compared to ZrO2 and Al2O3 films. The T(IL) was 0.8 nm in nano-composite films prepared at a mixing ratio (ZrO2:Al2O3) of 1:1. The breakdown strength and the leakage current level were greatly improved by adding Al2O3 as little as 7.9% compared to that of ZrO2 and were enhanced more with increasing content of Al2O3. The k of ZrO2 and mixed ZAO (Al2O3 7.9%) films were 20.0 and 16.5, respectively. These results indicate that the addition of Al2O3 to ZrO2 greatly improves the electrical properties with less cost of k compared to the addition of SiO2.

Interfacial oxide formation from intrinsic oxygen in W–HfO2 gated silicon field-effect transistors

We report the effects of ultrahigh vacuum and nitrogen annealing on self-aligned W-gated HfO2 n-field-effect transistors. While rapid thermal annealing in a nitrogen ambient significantly improved the channel mobility, there is a corresponding increase in the gate dielectric thickness of up to 20Å. Here we show that this increase is due to the formation of interfacial oxides between the HfO2 and the silicon, caused by the diffusion of oxygen from the W gates. The results point to the importance of oxygen solubility in metals, which may be significant in many candidate gate electrodes.