Gate Stack Engineering and Thermal Treatment on Electrical and Interfacial Properties of Ti/Pt/HfO2/InAspMOS Capacitors

Chung-Yen Chien,Pei-Wen Li,Jen-Inn Chyi,Jei-Wei Hsu,Pei-Chin Chiu

doi:10.1155/2012/729328

Chung-Yen Chien, Pei-Wen Li + Show 3 more

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https://doi.org/10.1155/2012/729328

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Abstract

Effects of gate stack engineering and thermal treatment on electrical and interfacial properties of Ti/Pt/HfO2/InAs metal insulator semiconductor (MIS) capacitors were systematically evaluated in terms of transmission electron microscopy, energy dispersive X-ray spectroscopy, current-voltage, and capacitance-voltage characterizations. A 10 nm thick Pt metal effectively suppresses the formation of interfacial oxide, TiO2, between the Ti gate and HfO2gate dielectric layer, enhancing the gate modulation on the surface potential of InAs. Anin situHfO2deposition onto then-InAs channel with an interfacial layer (IL) of one-monolayer InP followed by a 300°C post-metal-anneal produces a high-quality HfO2/InAs interface and thus unravels the annoying Fermi-level pinning, which is evidenced by the distinct capacitance dips in the high-/low-frequencyC-Vcharacteristics. The interface trap states could be further suppressed by replacing the InP IL by an As-rich InAs, which is substantiated by a gate leakage reduction and a steep voltage-dependent depletion capacitance.

Highlights

Motivation to study low band-gap InAs and InSb channels for next-generation metal oxide semiconductor (MOS) transistors is strong in light of their superior carrier mobility [1] and established epitaxy techniques [2, 3] among other emerging technologies such as carbon nanotube and graphite
The progress of realizing highperformance InAs and InSb MOS transistors has been impeded by the stringent restraint on thermal budget as well as the lack of robust gate dielectrics and suitable surface treatments for unraveling annoying Fermi-level pinning [4] at the oxide/semiconductor interface
The undesired interfacial TiOx and Hf-rich oxide layers deteriorate the oxide integrity and thicken the gate dielectrics thickness, which are evidenced by a highgate leakage, a poor gate modulation on the surface potential of InAs channel but a slightly higher breakdown voltage as illustrated in the I-V and C-V characteristics (Figure 3)

Summary

Introduction

Motivation to study low band-gap InAs and InSb channels for next-generation metal oxide semiconductor (MOS) transistors is strong in light of their superior carrier mobility [1] and established epitaxy techniques [2, 3] among other emerging technologies such as carbon nanotube and graphite. Encouraging experimental demonstrations of high-K gate dielectrics (Gd2O3, Al2O3, and HfO2) on GaAs [5,6,7], InP [8], and InAs [9,10,11] channels using atomic-layer deposition (ALD) techniques have shed lights and attracted tremendous attentions on this venerable subject. The authors report the interfacial and electrical properties of Ti/Pt/HfO2/InAs pMOS capacitors, in which a high-K gate dielectric, HfO2 was grown on an nInAs epitaxial layer without breaking vacuum by means of the integration of a molecular beam epitaxy system (Riber MBE) with an atomic layer deposition system (Picoson R100 ALD). In order to prevent thermal evaporation of InAs, all the device fabrication processes were kept below 300◦C Both Ti and Pt metals were evaluated for the gate materials. The interfacial layer effect arising from one-monolayer InP or As-rich InAs between HfO2 and InAs channel, the deposition conditions of HfO2, and post-metal-anneal (PMA) processes were systematically studied for improving the interfacial and electrical properties of HfO2/InAs pMOS capacitors

Experimental

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Results and Discussion

Measurement temperature

Conclusion