Amorphous Interfacial Layer Research Articles

Improvement in sensitivity of an indirect-type organic X-ray detector using an amorphous IGZO interfacial layer

To improve the power conversion efficiency (PCE) and sensitivity of indirect-type organic X-ray detectors, we examined the role of amorphous indium-gallium-zinc-oxide (a-IGZO) as an interfacial layer placed between the PBDB-T: PCBM active layer and the LiF/Al cathode. By RF magnetron sputtering, a-IGZO films with different thicknesses were deposited on a PBDB-T: PCBM active layer at room temperature. The optimized detector with a 10.1 nm a-IGZO layer achieved the highest PCE of 7.45% under artificial solar illumination, which was higher than the PCE (5.43%) of the detector without an a-IGZO layer. Furthermore, the highest sensitivity of 2.82 mA/Gy⋅cm2 under X-ray exposure was achieved for the detector with the 10.1 nm a-IGZO layer, which was an improvement of 26% over the X-ray detector without an a-IGZO layer.

Intragranular glass/crystal conjugated particles in strip cast Nd-Fe-B flakes

Intragranular rare earth-rich phases play a vital role in affecting the intrinsic coercivity of sintered Nd-Fe-B permanent magnets. To explore the origin of these intragranular rare-earth-rich phases, the starting material-strip cast Nd-Fe-B flakes were characterized by a variety of high-end microscopy techniques. It was surprisingly found that the intragranular rare-earth-rich phase is spherical in a diameter of ~150–300 nm and consists of amorphous regions rich in additive elements (e.g., Cu, Co, and Ga) and crystalline regions which are a combination of hexagonal light-rare-earth-rich phases and body centered cubic phases rich in light and heavy rare earth, and oxygen. Amorphous interfacial layers between the glass/crystal particles and the crystalline matrix were observed, probably due to insufficient time to reach a crystalline equilibrium state. Based on the microstructural observation, we proposed a formation mechanism of these intragranular glass/crystal conjugated particles in strip cast Nd-Fe-B flakes, which may facilitate to minimize the volume of these detrimental intragranular phases during the strip casting process.

Process Development of Radical Based Dry Clean for Advanced 3D NAND Fabrication

As semiconductor device scaling marching toward sub-5 nm logic, 128+ layers 3D NAND, and advanced 1x nm DRAM technology nodes, wafer surface cleaning and residue removal in nanoscale, high aspect ratio structures become increasingly critical. Dry clean technologies are developed as alternatives for traditional wet clean applications with significant advantages in process extendibility and environmental friendliness. Furthermore, in comparison with gas only processes, radicals are considered as attractive precursors for dry clean applications due to their high reactivity en route to a high cleaning efficiency. In this work we report a novel inductively coupled remote plasma source design for radical based dry clean applications. The inductively couple plasma (ICP) source yields a high gas dissociation efficiency and a high radical density. Plasma potential and electron temperature are minimized with a unique grounded Faraday shield design and can be further suppressed with a pulsed plasma operation. Ions and electrons generated in the plasma are effectively filtered by charge separation grids, thus only leaving high flux radicals to impinge onto the wafer surface. Different radical chemistries are developed for selective removal of different dielectric, metal, and semiconductor materials, specifically for efficient cleaning inside nanoscale and high aspect ratio structures in advanced semiconductor devices. Here we report the following applications tailored toward 3D NAND manufacturing. Pre-epitaxial deposition clean in high-aspect-ratio channel holes: The requirements are to remove SiOx-like residues and damaged silicon layer at the bottom of high-aspect-ratio channel holes without damage to the exposed SiO2/SiN stacks. The aspect ratio of channel holes can exceed 50:1. A multi-step process is developed based on remote plasma chemistries containing hydrogen and fluorine radicals, in conjunction of a RF bias on wafer surface to improve directionality. SiOx-like residues of various thickness are initially completely removed at the bottom of high-aspect ratio structures. With a customized radical chemistry and a unique anisotropic process, there is no sidewall SiN/SiO2 damage and a minimal CD change. Followed by a selective removal of damaged silicon layer and surface contamination from prior etch process, a pristine and coherent surface can be prepared for the subsequent epitaxial deposition. Contact hole clean: The main objective is to remove amorphous silicon or silicon oxide interface layer at bottom of high aspect ratio contact hole structures in order to minimize metal contact resistance. The aspect ratio of contact hole structures can exceed 50:1 in advanced 3D NAND devices. Device process flow requires a high selectivity towards tungsten. A fluorine-containing remote plasma process was developed to effectively remove oxidized Si residues, create enough gouging depth, and maintain contact hole structure integrity at the same time. Contact resistance is significantly reduced with the radical based dry clean process.

High strength/density ratio in a syntactic foam made from one-part mix geopolymer and cenospheres

By designing a composite of one-part mix geopolymer and hollow cenospheres, a commercially viable and environmentally-friendly foam was synthesised with a high strength/density ratio. The composite is made of a dry mix powder of geopolymer source materials, sodium silicate alkali activator and cenospheres, which starts to react when mixed with water. As the geopolymer reacts and gains strength over time, the surface of the cenospheres takes part in the reaction and forms a strong bond with the binding matrix. Synchrotron-based Fourier transform infrared microspectroscopy revealed, for the first time, the chemical bonding interaction of the amorphous interfacial layer between the geopolymer and cenospheres. The resulting foam composite gained a strength of 17.5 MPa at a density of 978 kg/m3, which is noticeably higher than that of existing environmentally-friendly lightweight foams made under ambient conditions. The thermal conductivity of the foam was measured to be around 0.28 kW/mK, which is similar to that of foam concrete. This foam produced in this study is found to be lightweight, strong and possess a desirable insulating capacity, while the preparation process of the one-part mix composite is maintained simply by adding water and curing the mixture at an ambient temperature.

Very large remanent polarization in ferroelectric Hf1-xZrxO2 grown on Ge substrates by plasma assisted atomic oxygen deposition

Plasma assisted atomic oxygen deposition was used to grow polycrystalline ferroelectric Hf1-xZrxO2 (x = 0.5–0.7) on technologically important (100) Germanium substrates showing sharp crystalline interfaces free of interfacial amorphous layers and strong evidence for the presence of a predominately orthorhombic phase. The electrical properties, evaluated using metal-ferroelectric-semiconductor (MFS) capacitors, show symmetric and robust ferroelectric hysteresis with weak or no wake-up effects. The MFS capacitors with x = 0.58 show very large remanent polarization up to 34.4 μC/cm2 or 30.6 μC/cm2 after correction for leakage and parasitics, combined with good endurance reaching 105 cycles at a cycling field of 2.3 MV/cm. The results show good prospects for the fabrication of Ge ferroelectric field effect transistors (FeFETs) for use in 1 T FeFET embedded nonvolatile memory cells with improved endurance.

An excellent performance of a C-Te OTS device with amorphous Ge interfacial layer for selector application

The effect of the interfacial layer on the reliability and off-current of a C-Te-based Ovonic threshold switching (OTS) device is investigated. By introducing an amorphous Ge (a-Ge) layer between both the top and bottom electrodes and the OTS film, a nearly 2-order of off-current reduction is confirmed. This could be attributed to the formation of a virtual electrode in the a-Ge layer that can scale down the effective area and localize electric field in a specific region. Area independent current-voltage characteristics were observed in the a-Ge introduced device while the without the barrier shows area dependent behavior, thus supporting the presence of a relatively small conductive filament that can act as a virtual electrode in the a-Ge inserted device. In addition, variabilities of the threshold voltage, hold voltage, and off-current are considerably improved owing to the confinement of the electric field. Transmission electron microscopy and energy dispersive spectroscopy analyses were employed to reveal the role of Ge at the interface. The findings are further supported by simulation using the thermally assisted hopping model.

Effect of Ion-Implantation Temperature on Contact Resistance of Metal/n-Type 4H-SiC With Ar Plasma Treatment

It has been reported that Ar plasma treatment on the n-type 4H-SiC surface before metal deposition can reduce the contact resistance. In that work, the n+ layer was formed by ion implantation at room temperature (RT). In this paper, it is found that Ar plasma treatment on the high-temperature (HT) implanted n+ layer degrades but not improves the contact resistance. A composition of RT/low-energy and HT/high-energy ion implantation can achieve low sheet resistance of the n+ layer and low contact resistance simultaneously. A twofold mechanism is proposed that the amorphous interfacial layer produced by Ar plasma treatment reduces the Schottky barrier height and the defects generated by RT ion implantation enhance current conduction by trap-assisted tunneling.

Attractive In Situ Self‐Reconstructed Hierarchical Gradient Structure of Metallic Glass for High Efficiency and Remarkable Stability in Catalytic Performance

AbstractMetallic glass (MG), with the superiorities of unique disordered atomic structure and intrinsic chemical heterogeneity, is a new promising and competitive member in the family of environmental catalysts. However, what is at stake for MG catalysts is that their high catalytic efficiency is always accompanied by low stability and the disordered atomic configurations, as well as the structural evolution, related to catalytic performance, which raises a primary obstacle for their widespread applications. Herein, a non‐noble and multicomponent Fe83Si2B11P3C1 MG catalyst that presents a fascinating catalytic efficiency while maintaining remarkable stability for wastewater remediation is developed. Results indicate that the excellent efficiency of the MG catalysts is ascribed to a unique atomic coordination that causes an electronic delocalization with an enhanced electron transfer. More importantly, the in situ self‐reconstructed hierarchical gradient structure, which comprises a top porous sponge layer and a thin amorphous oxide interfacial layer encapsulating the MG surface, provides matrix protection together with high permeability and more active sites. This work uncovers a new strategy for designing high‐performance non‐noble metallic catalysts with respect to structural evolution and alteration of electronic properties, establishing a solid foundation in widespread catalytic applications.

Electrical properties of FCVA deposited nano-crystalline graphitic carbon thin films with in situ treatment techniques

In this report, detailed studies of the nano-crystalline graphitic (NCG) carbon thin films deposited by filtered cathodic vacuum arc (FCVA) following its first discovery and first electrical characterization have been performed. The microstructure of carbon thin film can be modified by applying in situ treatment techniques (such as altering the thermal and carbon ion deposition energy). It was found that highly electrical conductive carbon thin films with graphitic planes can also be deposited at a low deposition temperature instead of the previously reported high deposition temperature with a 20% improvement in electrical characteristic. The detailed electrical characterization comparison between amorphous carbon and NCG has been conducted. To conclude, NCG carbon can be fabricated at deposition temperature above 400 °C and exhibits increasing through film Ohmic electrical conductivity with increasing deposition temperature. At low temperatures, NCG carbon can be produced by increasing the negative substrate bias above 300 V (impinging carbon ion energy). Higher negative substrate bias leads to thinner amorphous interface layer hence better electrical conductivity.

PEALD-deposited crystalline GaN films on Si (100) substrates with sharp interfaces**Project supported by the Fundamental Research Funds for the Central Universities (Grant Nos. FRF-BR-16-018A, FRF-TP-17-022A1, and FRF-TP-17-069A1), the National Natural Science Foundation of China (Grant Nos. 61274134 and 51402064), USTB Start-up Program (Grant No. 06105033), China Postdoctoral Science Foundation (Grant No. 2018M631333), Beijing Natural Science Foundation (Grant Nos. 2184112 and

Polycrystalline gallium nitride (GaN) thin films were deposited on Si (100) substrates via plasma-enhanced atomic layer deposition (PEALD) under optimal deposition parameters. In this work, we focus on the research of the GaN/Si (100) interfacial properties. The x-ray reflectivity measurements show the clearly-resolved fringes for all the as-grown GaN films, which reveals a perfectly smooth interface between the GaN film and Si (100), and this feature of sharp interface is further confirmed by high resolution transmission electron microscopy (HRTEM). However, an amorphous interfacial layer (∼2 nm) can be observed from the HRTEM images, and is determined to be mixture of GaxOy and GaN by x-ray photoelectron spectroscopy. To investigate the effect of this interlayer on the GaN growth, an AlN buffer layer was employed for GaN deposition. No interlayer is observed between GaN and AlN, and GaN shows better crystallization and lower oxygen impurity during the initial growth stage than the GaN with an interlayer.

Nanostructure and Optical Property Investigations of SrTiO₃ Films Deposited by Magnetron Sputtering.

Strontium titanate thin films were deposited on a silicon substrate by radio-frequency magnetron sputtering. The structural and optical properties of these films were characterized by X-ray diffraction, high-resolution transmission electron microscopy, X-ray photoelectron spectroscopy, and spectroscopic ellipsometry, respectively. After annealing at 600–800 °C, the as-deposited films changed from amorphous to polycrystalline. It was found that an amorphous interfacial layer appeared between the SrTiO3 layer and Si substrate in each as-deposited film, which grew thicker after annealing. The optical parameters of the SrTiO3 film samples were acquired from ellipsometry spectra by fitting with a Lorentz oscillator model. Moreover, we found that the band gap energy of the samples diminished after thermal treatment.

(Invited) Full Wafer CMOS-Compatible Integration of Ge with Si By Direct Wafer Bonding

Silicon is the base material for electronic technologies and has emerged as a very attractive platform for photonic integrated circuits (PICs). PICs allow optical systems to be made more compact with higher performance than discrete optical components. Some of the applications of PICs are in the areas of fibre-optic communications, biomedical devices, photovoltaics and imaging. Germanium, due to its low bandgap, maturity and compatibility with Si technology is preferred over III-V compounds as an integrated on-chip detector at near infrared wavelengths. In the integration of Ge with Si a high-quality defect-free, 100% Ge layer is desirable for realising high-performance photodiodes. Low defect density in the Ge layer will lower the dark current by minimising the leakage mechanisms and noise sources. There are two main approaches for Ge/Si integration: epitaxial growth [1] and wafer bonding [2]. Lattice mismatch of ~4.2% between Ge and Si is the main problem of the former technique leading to high density of dislocations and hence increased leakage current, while the bond strength and conductivity of the interface are the main challenges of the latter. Both result in the formation of trap states which are expected to play a critical role in the device performance. Understanding the physics of the interface is key in the design of Ge/Si devices. In this talk, an alternative integration approach of low-temperature CMOS-compatible plasma activated direct wafer bonding, developed in order to accommodate the lattice mismatch, will be discussed. Electronic and optical devices fabricated exploiting this full wafer integration technique will be demonstrated. The focus will be on the physics of the heterojunction interface and its role in the band alignments. In the first part, a proof of concept of Ge/Si integration by using wafer bonding and layer exfoliation (Smart Cut™ process) with low thermal budget will be outlined. Mesa diodes made by transferring a 700nm-thick Ge layer onto Si using this technique will be reported. Fabrication, characterisation, and analysis of the electrical transport across the interfacial oxide present between the Ge and Si wafers will also be discussed. Highly-doped n-type Si and p-type Ge wafers are used to allow the electric field distribution to drop within short distances from the interface enabling us to investigate the influence of bonded interface on carrier transport through the p-n junction. Effects of low-temperature annealing on the device performance and on the conductivity of the interface will be reviewed. The carrier transport mechanism is shown to be dominated by generation-recombination before anneal and direct tunnelling in forward bias and band-to-band tunnelling in reverse bias after annealing which are defined by the role of interface traps. In the next part of the talk, we report on a remarkably-high responsivity photodiodes especially at low incident powers made by integrating low-doped p-Ge with highly-doped n-Si (p −-Ge/n +-Si heterojunction) by direct wafer bonding. The p −-Ge/n +-Si photodiode arrangement was selected to enable collection of electrons into the Si due to the more favourable band-offset. Responsivities in excess of 3.5 A/W at wavelength of 1.55 µm under surface normal illumination is measured for photodiodes with 5.4 µm Ge layer transferred onto Si by wafer bonding followed by chemical mechanical polishing (CMP). Detailed analysis regarding the temperature-dependent carrier transport across the junction and the band alignments at the interface will be presented. The high responsivity of the detectors is shown to be due to light-induced potential barrier lowering at the interface. To our knowledge, this is the first report of light-gated responsivity for vertical illuminated Ge/Si photodiodes. The developed wafer bonding process followed by either layer exfoliation or CMP is a low-temperature wafer-scale process. The unique results discussed in this talk are compatible with surface normal illumination and are capable of being integrated with CMOS electronics and readout circuits in the form of 2D arrays of detectors. One potential future application is a low-cost back-end-of-line compatible dual-band near infrared/visible cameras. [1] Y. Kang, et al., Nature Photonics, pp. 59-63, 2009. [2] H. Kanbe, et al., Japanese Journal of Applied Physics, pp. L644-L646, 2006. The figure shows a schematic illustration of a Ge/Si photodiode made by wafer bonding followed by CMP. The XTEM images confirm the presence of interfacial amorphous layer at the bonded interface. Photoresponse of the detector as a function of input optical power at a wavelength of 1.55 µm is also presented at two different temperatures. Schematic representation of the band diagram at the Ge/Si interface at equilibrium and under illumination is shown indicating the potential barrier lowering due to filling of acceptor-type traps at interface by the photogenerated carriers. Figure 1

Large Area Growth of MoS2 By Chemical Vapour Deposition

Transition Metal Dichalcogenindes (TMD) have considerable potential for applications spanning electronics, sensors and optoelectronics due to the wide ranging electronic and optical properties which are displayed by this class of 2D layered materials [1]. Research is focused on issues such as: large area growth [2, 3], stable approaches to doping [4] and achieving required values of specific contact resistivity [5]. We are contributing to the research effort by investigating the structural, optical and electronic properties of crystalline molybdenum disulfide (MoS2) grown by chemical vapour deposition (CVD) in a commercial 300mm atomic layer deposition reactor. In this work we report on the properties of monolayer and multilayer MoS2 growth at 550oC using Mo(CO)6 and H2S precursors on a number of different substrates, including SiO2, sapphire and amorphous alumina. This work focuses on the topology, Raman response and electronic properties of the CVD grown MoS2 thin films. Figure 1 (a) shows the Raman spectrum for an as-grown 10nm MoS2 on a SiO2/Si substrate. MoS2 can be determined by the peaks at approximately 385cm-1 (E1 2g) and 410cm-1 (A1g). There are two other peak characteristics of MoS2 which cannot be seen due to back-scattering at 286cm-1 (E1g), and lack of sensitivity below 200cm-1 at 32cm-1 (E2 2g )[6]. Additional peaks are detected at wavenumbers between 2000-3000cm-1, seen in Fig. 1 (b). Further investigation is needed to establish if these peaks are from photoluminescence, contaminants within the structure or purely a surface effect. Fig. 1 (c) shows an AFM image of an annealed 1.2nm MoS2 sample on a SiO2/Si substrate. The blue marks indicate areas on the material that are above a height of 0.6nm. Further results will be presented as a function of the number of MoS2 monolayers using Conductive AFM (C-AFM) and Kelvin Probe analysis. XTEM images seen in Fig. 1 (d), (e) show MoS2 grown on SiO2/Si and sapphire substrates respectively. They show that polycrystalline and layered MoS2 is formed at the growth temperature of 550oC, with no subsequent post growth annealing. There is no interfacial layer formed at the MoS2/SiO2 interface, but an amorphous interfacial layer of ~0.5nm is observed between MoS2 and sapphire, which is still being investigated. Plan view TEM analysis (not shown) confirms aligned MoS2 with grain sizes (over a local area of around 100 nm x 100nm) in the range 5nm to 20nm. The carrier concentration, carrier type and carrier mobility were studied with Hall measurements carried out at room temperature using a Van der Pauw structure (1cm x 1 cm). Excellent ohmic behavior is achieved on MoS2 (nominally 10nm) deposited on both sapphire and a-Al2O3/sapphire substrates. Table 1 provides a summary of the Hall analysis, showing that the non-intentionally doped MoS2 grown by CVD is n-type with very low carrier concentrations on the order of ~1014cm-3, electron mobility in the range 3.3-16.7cm2/V.s. Mobility values up to ~ 15 cm2/Vs for a grain size in the 10nm to 60nm range, is an interesting result, as in the work of K. Kang et al., [3], the monolayer grain size is around 1 mm with an associated electron mobility of 30 cm2/V. These results suggests that grain boundary defects in 2D MoS2 may not be the main factor limiting carrier mobility, as is typically the case in polycrystalline 3D semiconductors (see for example [7]). In addition, the unintentional n type doping in the CVD grown MoS2 is low, with values around 1-3x1014 cm-3. This low value of unintentional doping provides a useful baseline in-situ for doping studies with elements such as Nb [8] and Re [9].

Si-Ge Heterostructures Fabricated by Room Temperature Wafer Bonding

A newly developed technology was used for in situ surface activation and wafer bonding of silicon and germanium substrates in order to achieve high quality, full strength, room temperature covalent wafer bonding. An ion beam was employed for the surface preparation procedure, resulting in contamination-free substrates with low bulk damage.After surface preparation the substrates were handled and placed into contact under high vacuum environment. Cross section HR-TEM analysis revealed the presence of a thin amorphous interfacial layer after room temperature bonding.Thermal annealing was performed in order to prepare the samples for electrical characterization. Current-voltage measurements showed near-ideal diode characteristics with an ideality factor of 1.1 obtained after correcting for the series resistance which consists of a contact and an interface resistance.

Formation of amorphous interfacial layer between Zn-based alloy and SiC particles under ultrasonic-assisted brazing

Abstract The joining of an aluminium matrix composite to a titanium alloy by ultrasonic-assisted brazing using a Zn-based filler metal was investigated. An approximately 50-nm-thick amorphous Zn–Mg–Si interfacial layer formed between the Zn-based filler metal and SiC particles adjacent to the Ti alloy side of the brazed joint. Many of the Zn crystals that formed during brazing nucleated in this amorphous layer, suggesting that the amorphous layer acted as a diffusion layer between the Zn-based filler metal and SiC ceramic during brazing. This work not only explains the improvement in the performance of the brazing joints by the ultrasonic action but also proposes a strategy to optimise the interfacial structure for other metallic alloys.

Insight into the Near-Conduction Band States at the Crystallized Interface between GaN and SiN x Grown by Low-Pressure Chemical Vapor Deposition.

Constant-capacitance deep-level transient Fourier spectroscopy is utilized to characterize the interface between a GaN epitaxial layer and a SiN x passivation layer grown by low-pressure chemical vapor deposition (LPCVD). A near-conduction band (NCB) state ELP ( EC - ET = 60 meV) featuring a very small capture cross section of 1.5 × 10-20 cm-2 was detected at 70 K at the LPCVD-SiN x/GaN interface. A partially crystallized Si2N2O thin layer was detected at the interface by high-resolution transmission electron microscopy. Based on first-principles calculations of crystallized Si2N2O/GaN slabs, it was confirmed that the NCB state ELP mainly originates from the strong interactions between the dangling bonds of gallium and its vicinal atoms near the interface. The partially crystallized Si2N2O interfacial layer might also give rise to the very small capture cross section of the ELP owing to the smaller lattice mismatch between the Si2N2O and GaN epitaxial layer and a larger mean free path of the electron in the crystallized portion compared with an amorphous interfacial layer.

Characterization of BaTiO3 nanocubes assembled into highly ordered monolayers using micro- and nano-Raman spectroscopy

We investigated the influence of heat treatment on the crystallographic structure and ferroelectric phase transition behavior of barium titanate (BaTiO3, BT) nanocubes assembled into highly ordered monolayers, using tip-enhanced Raman spectroscopy (TERS), temperature-dependent micro-Raman spectroscopy, and scanning transmission electron microscopy (STEM). TER spectra from individual BT nanocubes with the size of about 20 nm were obtained with a side-illumination optical setup, and revealed that heat treatment enhances their tetragonality. The result of temperature-dependent micro-Raman spectroscopy showed that the ferroelectric phase transition behavior of the monolayers becomes similar to that of bulk BT through heat treatment in spite of their thickness. STEM observation for the cross-section of the heated BT nanocube monolayer showed that amorphous layers exist at the interface between BT nanocubes in face-to-face contact. These results indicate that the tetragonal crystal structure of BT nanocubes is stabilized by heat treatment and the formation of the interfacial amorphous layer during heat treatment may be a key to this phenomenon.

The study of metal enhanced fluorescence property of Ag/ZnO composite structure

In this paper, Ag nanoparticles were successfully prepared by chemical reduction, and then Ag/ZnO composite particles were successfully prepared and deposited onto glass substrates to form Ag/ZnO thin films. Hereafter, the structure, the morphology and the metal enhanced fluorescence (MEF) property of Ag nanoparticles and ZnO/Ag composite particles were studied by XRD, SEM, EDS, TEM, UV-vis absorption and fluorescence (FL) spectrometer. The results showed that the average size of Ag nanoparticles increased with the increase of prepared time. Moreover, ZnO layer consisted of polycrystalline structure and amorphous interface layer, but nano-Ag particle was polycrystalline structure. Annealing process was carried out to investigate the influence of annealing process parameters on MEF property of Ag/ZnO composite structure. Due to annealing treatment, the amorphous component of Ag/ZnO thin films was reduced, which might improve the density of Ag/ZnO thin films and the diameter of composite particles. Furthermore, FL enhancement phenomenon of fluorescein isothiocyanate (FITC) molecules might be attributed to the joint influence of the roughness and the density of these films and the average diameter of composite particles.

Dual‐functional crystalline BeO layer in enhancement‐mode ZnO/Si thin film transistors

Integration of oxides with Si opens promising opportunities for novel multifunctional devices and new applications. To optimize the device performances through the hybrid integration, keeping the oxide/Si interface abrupt is critically important and challenging due to the seemingly unavoidable formation of amorphous SiOx or silicide interfacial layers. Here, we report an interface‐engineering approach to this issue by molecular beam epitaxy. A BeO thin layer (∼5 nm) was deposited on Si (111) surface using a two‐step process of Be deposition and oxidation. The initially formed BeO served as a template for subsequent homo‐epitaxial growth of a 10‐nm crystalline BeO layer. The well‐defined interface between BeO and Si is clearly discerned by high‐resolution transmission electron microscopy, implying the role of crystalline BeO as a barrier layer against oxygen atoms’ diffusion. High‐resolution X‐ray photoelectron spectroscopy further confirmed that the combined BeO layers sufficiently protect the Si surface from oxidation. A bottom‐gate enhancement‐mode thin film transistor was established on a ZnO (130 nm)/BeO (70 nm)/Si architecture, where BeO was functionalized both as a diffusion barrier and as a high‐k gate insulator. It indicates that this methodology can be potentially extended to hybrid integration of other technologically important crystalline oxides with Si infrastructures.

Multilevel resistance in ZnO nanowire memristors enabled by hydrogen annealing treatment

In non-volatile memory technology, various attempts to overcome both technology and physical limits have led to development of neuromorphic devices like memristors. Moreover, multilevel resistance and the potential for enhanced memory capability has attracted much attention. Here, we report memristive characteristics and multilevel resistance in a hydrogen annealed ZnO nanowire device. We find that the memristive behavior including negative differential resistance arises from trapped electrons in an amorphous ZnO interfacial layer at the injection electrode that is formed following hydrogen annealing. Furthermore, we demonstrate that it is possible to control electrons trapping and detrapping by the controlled application of voltage pulses to establish a multilevel memory. These results could pave the way for multifunctional memory device technology such as the artificial neuromorphic system.