Interface Trap Charge Research Articles

Analytical drain current model of stacked oxide SiO2/HfO2 cylindrical gate tunnel FETs with oxide interface charge

In this paper, we have developed an analytical drain current model of stacked oxide SiO2/HfO2 cylindrical gate tunnel field-effect transistor (CG TFET) by considering the effect of interface trap charge at Si–SiO2 interface nearby the source–channel junction. To model the channel potential, Poisson’s equation has been solved by using the parabolic approximation method in a cylindrical coordinate system with appropriate boundary conditions. The potential model has then been utilized for developing some expressions for minimum tunneling length, lateral electric field, and the drain current of stacked oxide SiO2/HfO2 CG TFET. The impact of the source/drain depletion region has been considered for improving the accuracy of the proposed model. The commercially available ATLAS™ 3D-based TCAD simulation data have been used to validate the proposed model results.

Influence of surface restructuring on the activity of SrTiO3 photoelectrodes for photocatalytic hydrogen reduction

Perovskite photoelectrodes are being extensively studied in search for photocatalytic materials that can produce hydrogen through water splitting. The solar-to-hydrogen efficiency of these materials is critically dependent on the electrochemical state of their surface. Here, we develop an embedded quantum-mechanical approach using the self-consistent continuum solvation model to predict the relation between band alignment, electrochemical stability, and photocatalytic activity taking into account the long-range polarization of the semiconductor electrode under electrical bias. Using this comprehensive model, we calculate the charge-voltage response of various reconstructions of a solvated ${\mathrm{SrTiO}}_{3}$ surface, revealing that interfacial charge trapping exerts primary control on the electrical response and surface stability of the photoelectrode. Our results provide a detailed molecular-level interpretation of the enhanced photocatalytic activity of ${\mathrm{SrTiO}}_{3}$ upon voltage-induced restructuring of the semiconductor-solution interface.

Sensitivity Improvement of Medical Dosimeters Using Solution Processed TIPS-Pentacene FETs

In this paper, we have explored the electrical and material properties of TIPS-Pentacene for low doses of gamma irradiation. Interface trap/defect generation was studied post gamma irradiation of TIPS-Pentacene transistors. This paper demonstrates that the traps/defects at the bulk/surface of TIPS-Pentacene and SiO2/Si interface states significantly influence the sensing behavior. It is demonstrated that the interface trap charges introduced by the gamma radiation are significant in the TIPS-Pentacene thin-film instead of the SiO2/Si. The detector exhibits a record high sensitivity of ~3 V/Gy at 1 Gy in ambient air. A theoretical model was developed to understand the change in ON-current and channel doping. The change in surface potential of film was studied by Kelvin probe force microscopy (KPFM). Developed model was in good agreement with the KPFM results. These promising results indicate that our device can be used as a dosimeter for medical applications with high sensitivity.

Mechanism of Degradation Rate on the Irradiated Double-Polysilicon Self-Aligned Bipolar Transistor

The latent enhanced low dose rate sensitivity (ELDRS) effect is observed in the double-polysilicon self-aligned (DPSA) technology PNP bipolar junction transistor (BJT) irradiated with a high and low dose rate gamma ray, which is discussed from the perspective of the three-stage degradation rate of the excess base current. The great degradation rate as a result of the high dose irradiation of the first stage is dominantly ascribed to the positive oxide trap charges accumulated during a short irradiation, and then due to the competition between the recombination of electrons and capture of the hole by the traps. It declined sharply into a degradation rate saturated region of the second stage. However, for the low dose rate, the small increase in the degradation rate in the first stage is caused by the holes escaping from the initial recombination and being transported to the interface to form the interface states. Then, the competition between the steadily increasing interfacial trap charge and the continuously annealed shallow level oxide trap charge leads to the stable increase of degradation under low dose irradiation. Finally, in stage three, the increases of the degradation rates for high and low dose irradiation result from the different amounts of the hydrogen molecules generated by the hole reactive with depassiviated Si suspended bonds, which can interact with the deep level defects and release protons, causing an increase of interfacial trap charges with prolonged irradiation.

Program/Erase Cycling Degradation Mechanism of HfO2-Based FeFET Memory Devices

The mechanism of memory window (MW) degradation of Hf0.5Zr0.5O2-based ferroelectric field-effect transistors (FeFETs) with program/erase (P/E) cycling is investigated. First, the P/E cycling properties of the FeFETs are characterized at different cycling voltages. Then, the midgap voltage method is proposed to address the underlying drivers for the threshold voltage shift and MW degradation by separating the effects of oxide-trapped charges and interface-trapped charges. The mechanism for different threshold voltage evolutions between programed and erased states during P/E cycling is revealed. Moreover, the amount of MW degradation is nearly equal to the difference of midgap voltage shift values between programed and erased states, and the interface trap generation contributes to the midgap voltage shift.

Interface trap-dependent linearity assessment in single and dual metal gate junctionless accumulation mode (surrounding gate) nanowire MOSFET

This paper examines the reliability issue of single metal gate (SMG) and dual metal gate (DMG) junctionless accumulation mode surrounding gate (JAM-SG) MOSFET. The impact of trap charges has also been considered along with the variation of different temperature range (200–400 K). In addition, the analog/RF performance of SMG-JAM-SG and DMG-JAM-SG MOSFET evaluated in terms of the fundamental figure of merits such as ON-state current (ION), OFF-state current (IOFF), ION/IOFF, transconductance (gm), cutoff frequency (fT), current gain, transducer power gain, VIP2, VIP3, IIP3, IMD3 and higher order transconductance parameters gm1, gm2 and gm3. An extensive comparative analysis in terms of overall performance degradation is accomplished between DMG-JAM-SG and SMG-JAM-SG MOSFET using numerical simulation tool (ATLAS 3-D). The temperature sensitivity of device has also been explained with the effect of trap charges. The results reveal that DMG-JAM-SG MOSFET has better immunity contrary to impact of interface trap charges and exhibit high linearity performance, as compared to SMG-JAM-SG MOSFET and DMG-JAM-SG MOSFET is appropriate for highly efficient RFICs and wireless device applications.

Fast Response UV Photodetection Using TiO2 Nanowire/Graphene Oxide Thin-Film Heterostructure

A UV detector was fabricated based on vertical TiO2 nanowires (NWs) grown over spin-coated graphene oxide (GO) thin film (TF) using glancing angle deposition technique. A small dark current ( $0.0254~\mu \text{A}$ /cm $^{2}$ at 4 V) was observed for the Au/TiO2 NW/GO TF/Si device. Interface trap charges played a significant role in high photocurrent under 380 nm light illumination, which leads to high trap-assisted tunneling. The modified band bending at higher energy light illumination of 300 nm opposed the carrier to tunnel through the junction and forced to decrease the current. Variation in photocapacitance was obtained, which verified the presence of interface trap charges. A high responsivity of 48.3 mA/W and also photosensitivity and detectivity of 82.7 and $2.26\times 10^{11}$ Jones, respectively, were measured under 380 nm ( $113.8~\mu \text{W}$ /cm $^{2}$ ) illumination. A high rise time (48 ms) and fall time (40 ms) due to efficient charge separation between the TiO2 and the GO device are reported.

Effect of HCl cleaning on InSb–Al2O3 MOS capacitors

In this work, the role of HCl treatments on InSb surfaces and InSb–Al2O3 dielectric interfaces is characterised. X-ray photoelectron spectroscopy measurements indicate that HCl diluted in and rinsed with isopropanol (IPA) results in a surface layer of InCl3 which is not present for similar HCl-water processes. Furthermore, this InCl3 layer desorbs from the surface between 200 °C and 250 °C. Metal–oxide–semiconductor capacitors were fabricated using atomic layer deposition of Al2O3 at 200 °C and 250 °C and the presence of InCl3 was associated with a +0.79 V flatband voltage shift. The desorption of the InCl3 layer at 250 °C reversed this shift but the increased process temperature resulted in increased interface-trapped charge (D it) and hysteresis voltage (V H ). This shift in flatband voltage, which does not affect other figures of merit, offers a promising route to manipulate the threshold voltage of MOS transistors, allowing enhancement-mode and depletion-mode devices to be fabricated in parallel.

On the C-V characteristics of nanoscale strained gate-all-around Si/SiGe MOSFETs

Gate-all-around (GAA) metal-oxide-semiconductor field-effect transistors (MOSFETs) is one of the mainstream research topics of the current era in the field of semiconductor devices since they are the most efficient architectures among all multiple-gate (MG) devices. Incorporating strain in GAA device can boost the device performance significantly. As such, strained-Si (S-Si) GAA MOSFETs can have vast technological importance in future high performance logic technologies. Due to imperfections in the fabrication process, the cross-section of a GAA device may deviate from its ideal circular nature, giving rise to an elliptical structure. Capacitance-Voltage (C-V) characteristics is an important tool for characterizing such devices. For the first time, we analytically model the quasi-static C-V characteristics of elliptical S-Si GAA MOSFETs for various operating regions. We have incorporated quantum mechanical effects (QMEs) which cannot be neglected in devices having ultra-nanometre dimensions. Computations were carried out to investigate the effects of device dimensions, interface trap charges, doping concentration, germanium mole fraction and stress on the C-V characteristics of S-Si GAA MOSFETs. The possibilities for enhancing the device performance by using high-k dielectrics have also been investigated.

Effect of interface trap charges on the performance of asymmetric dielectric modulated dual short gate tunnel FET

In this paper, the influence of interface trap charges on the characteristics of asymmetric dielectric modulated dual short gate tunnel field effect transistor (ADMDG-TFET) has been analyzed. The effect of a donor (positive) and acceptor (negative) trap charges with various concentrations on the device d.c characteristics are studied. A comparative analysis has been performed between symmetric silicon dual gate tunnel field effect transistor (DG-TFET) and ADMDG-TFET (both Si and Si0.3Ge0.7) with matching dimensions in the presence/absence of interface trap charges. It is found that a shift in threshold voltage (Vth) and subthreshold swing (SS) degradation are observed due to the presence of interface traps in both devices. However, the ADMDG TFET is more immune to Vth shift and SS degradation by acceptor and donor interface traps compared to silicon DG TFET. Also, the ambipolar current in ADMDG TFET is more suppressed than the silicon DG TFET in the presence of trap charges.

Subthreshold modeling of nanoscale germanium-tin (GeSn)-on-insulator MOSFETs including quantum effects

Although germanium-tin (GeSn) channel p-MOSFETs exhibit outstanding performance compared to other p-MOS transistors, their accurate analytical model has not yet been reported. In this paper, we present, for the first time, a 2-D surface-potential-based sub-threshold model for GeSn-on-insulator (GeSnOI) MOSFETs taking into account the interface-trapped and fixed-oxide charge densities, and also quantum effects. Unlike most of the earlier models applied to elementary and undoped semiconductor channels, the present model embraces variations in the alloy composition as well as doping concentration in the channel. Furthermore the model neither supports iterations nor involves any fitting parameters throughout the derivation, and hence it is physical, predictive, and applicable to circuit simulators like SPICE. We calculate various device parameters such as threshold voltage Vth, threshold voltage roll-up, drain induced barrier lowering DIBL and subthreshold slope SS related to short channel effects (SCEs) of GeSnOI p-MOSFETs for Sn contents ranging 0–6% and channel thickness from 5 to 10 nm. The obtained results show that the GeSnOI MOSFET with channel thickness of 5 nm yields the lowest value of Vth, DIBL, SS and Vth-shift indicating suppression of SCEs. Our model is verified by comparing analytical results for various device parameters with corresponding numerical simulation results and also with limited experimental data available in the literature.

Impact of interface traps on performance of Gate-on-Source/Channel SOI TFET

Here, one of most important reliability issue of the semiconductor device, the effects of traps present at the oxide-semiconductor interfaces on gate-on-source/channel SOI TFET are investigated. Conventional SOI TFET, gate-on-source only TFET, and gate-on-source/channel TFET are compared and it is found that gate-on-source/channel TFET has better immunity to the interface trap charge variation. The gate-on-source/channel TFET exhibits higher on current and on-off current ratio than gate-on-source device. Preliminary analyses are presented for the proposed architecture for the parameters: gate-channel overlap, back gate voltage and buried oxide thickness in absence of interface traps. The back gate voltage has a significant effect on the channel-drain junction of the device, and hence, on the ambipolar current. Further, the device characteristics in presence of traps at the gate oxide-semiconductor interface and buried oxide-semiconductor interface are reported. The effect of trap concentration is observed on the transfer characteristics, capacitance, and cut off frequency. The front gate dielectric-semiconductor interface traps degrade on current, while the buried oxide-semiconductor interface traps affect the ambipolar current. The effect of back gate voltage on ambipolarity and on current of the proposed device is studied in detail in presence of traps.

Impact of Interface Trap Charges on the Electrical Characteristics of Back-Gated 2D Negative Capacitance (NC) FET

In this letter, a fully analytical compact drain current model of back-gated two-dimensional (2D) negative capacitance (NC) FET including interface trap charges has been developed by solving Poisson's, drift-diffusion and 1-D Landau-Khalatnikov equations, and it is validated against the experimental data. In addition, the impact of interface trap charges on the electrical characteristics of the back-gated 2D NC-FET is investigated systematically based on the model. It is found that the subthreshold swing (SS) and on-off current ratio ( I on/ I off) are seriously degraded because of the presence of interface traps at 2D channel/oxide interface and 2D NC-FET with a big tf is more immune to the degradation induced by the interface traps. In addition, the underlying physics are elucidated by the capacitance matching of 2D NC-FET.

Effect of Gate-Oxide Degradation on Electrical Parameters of Power MOSFETs

Gate oxide in power metal–oxide–semiconductor field effect transistors (MOSFETs) degrades over time. The degradation leads to an accumulation of oxide-trapped charges within the gate oxide and an accumulation of interface-trapped charges at the oxide–semiconductor surface of power MOSFETs. Overtime, such charges significantly alter the electrical parameters of power MOSFETs; to observe this, the electrical parameters are utilized as precursors of gate-oxide degradation. The purpose of this paper is threefold: 1) to propose a new online precursor of gate-oxide degradation—the gate plateau time; 2) to demonstrate a simultaneous dip-and-rebound variation pattern of four precursors of gate-oxide degradation: threshold voltage, gate plateau voltage, gate plateau time, and on-resistance; and 3) to compare the shift tendencies of each precursor over the course of gate-oxide degradation. The existing studies of gate-oxide degradation mechanisms and their effects on threshold voltage and mobility reduction were extended to correlate a variation of all four precursors using analytical expressions. The variation patterns were experimentally verified using high-electric field stressing in two different commercial power MOSFETs. The new precursor, the gate plateau time, was found to be a competitive gate-oxide degradation precursor, as it had a higher positive shift than threshold voltage and gate plateau voltage. In addition, the threshold voltage was found to be the most sensitive indicator of the negative shift (dip), while the on-resistance and gate plateau time were found to be the most sensitive indicators of the positive shift (rebound).

In situ dry cleaning of Si wafer using OF2/NH3 remote plasma with low global warming potential

Dry cleaning technology is an essential technique that can be applied to remove native oxide and various contaminants during the semiconductor manufacturing for nanoscale electronic devices. In this study, the in situ dry cleaning of silicon dioxide (SiO2) with low global warming potential (GWP) gas mixtures has been investigated by sequential process steps composed of the reaction of SiO2 surface by oxygen difluoride (OF2) (GWP: <1)/ammonia (NH3) remote plasma and the removal of the reacted compound layer by lamp heating. By using the optimized OF2/NH3 (2:1) mixture for the surface reaction followed by the lamp heating at 200 °C to remove the reacted compound layer, a high-SiO2 cleaning rate and etch selectivity over silicon nitride (>30:1) could be obtained due to the formation of the highest HF concentration on the SiO2 surface at the OF2/NH3 (2:1) gas ratio. The compound layer formed during the reaction was (NH4)2SiF6 observed for a previously investigated NF3 (GWP: 17 200)/NH3 plasma, but the dry SiO2 cleaning rate and the etch selectivity over Si3N4 obtained by the OF2/NH3 plasma were higher than those by the optimized NF3/NH3 plasma. The effects of OF2/NH3 mixture dry cleaning on the electrical characteristics of metal-oxide-semiconductor (MOS) devices fabricated on the nano-scale trench patterned Si substrate with high aspect ratio were studied and compared with conventional wet and NF3/NH3 mixture dry cleaning-based devices. Compared with other cleaning methods, OF2/NH3 dry-cleaning shows the improved and reliable electrical characteristics such as sharper capacitance-voltage behavior, lower hysteresis, less interface trap charge and smaller contact resistivity. Therefore, it is believed that the in situ sequential dry SiO2 cleaning with the OF2/NH3 remote plasma can be applied as an essential cleaning method with extremely low GWP for fabricating next generation nano-scale devices.

Impact of interfacial layer using ultra-thin SiO2 on electrical and structural characteristics of Gd2O3 MOS capacitor

The aim of present study is to improve the quality of Gd2O3/p-Si MOS structure by reducing interface trap charge density. Therefore, the ultra-thin SiO2 layer was grown to high-k/Si interface. The effect of the post deposition annealing on the structural properties of the Gd2O3/SiO2 films and electrical characteristics of the Al/Gd2O3/SiO2/p-Si/Al were investigated for three different temperature. Besides, the effect of the series resistance and measurement frequency on the electrical characteristics of the p-MOS capacitors was examined in detail. 118 nm-thick Gd2O3 films were grown by RF magnetron sputtering following the 5 nm-thick SiO2 deposition on p type Si wafer by dry oxidation method. While the Gd2O3 monoclinic characteristic peaks were observed in the Gd2O3/SiO2/Si structures annealed at 600 °C and 800 °C, the XRD spectra of as-deposited and annealed at 400 °C sample pointed out Gd silicate formation. –Si, –O, –Gd, and –H bonds were defined in the FTIR spectra of all samples. The frequency dependent capacitance–voltage (C–V) and conductance–voltage (G/ω–V) characteristics of Gd2O3/SiO2 MOS capacitor were measured. Strong accumulation capacitance values in these devices did not change significantly depending on frequency. Unlike from the MOS capacitor with as-deposited and annealed Gd2O3/SiO2 at 400 °C, the interface trap charge density $$({N_{it}})$$ increased with increasing voltage frequency for the samples annealed at 600 °C and 800 °C. No significant change in the border trap density $$({N_{bt}})$$ with increasing frequency was observed in the MOS capacitor except for as-deposited device. The barrier height $$({\Phi _B})$$ increased with increasing frequency for all Gd2O3/SiO2 MOS capacitors.

Examination of the impingement of interface trap charges on heterogeneous gate dielectric dual material control gate tunnel field effect transistor for the refinement of device reliability

In this work, the authors have reported the reliability issues of dual material control gate tunnel field effect transistor (DMCG-TFET) and proposed heterogeneous gate dielectric dual metal control gate tunnel field effect transistors (HD DMCG-TFETs) in terms of interface trap charges (ITCs). The positive and negative types of localised charges at the semiconductor/insulator interface cause degradation in the device performance (DC/RF). In this regard, the proposed structure which includes combination of low-K and high-K dielectric improves the immunity towards the ITCs at the interface of semiconductor/insulator with better performance. In this concern, the study has analysed the impact of ITCs on DC and analogue/RF performances of the DMCG-TFET and HD DMCG-TFET in terms of various parameters like electric field, energy band diagram, carrier concentration, transfer characteristics, transconductance ( g m ), cutoff frequency ( f T ) and gain bandwidth product. Further to this, impact on device linearity parameters is also analysed through higher order of transconductance coefficients ( g m 3 ), VIP2, VIP3 and IIP3.

A comprehensive study on usage of Gd2O3 dielectric in MOS based radiation sensors considering frequency dependent radiation response

The purpose of this study is to investigate the Gadolinium Oxide (Gd2O3) as a gate dielectric/sensitive region in MOS based radiation sensors and to provide a detailed description of the frequency-dependent gamma irradiation response of a Gd2O3 MOS capacitor. The 254 nm thick-Gd2O3 films were deposited on p-type Si wafers by using RF magnetron sputtering. The radiation response of the Gd2O3 MOS capacitors was investigated by 60Co irradiation in the range of 0.5–70 Gy. The capacitance-voltage (C-V) curves shifted to a more positive potential with increasing radiation dose due to there being more trapped electrons than holes. The variation in the oxide trap charge density was found to be in the range of − 3.21 × 1011 ± 1.57 × 1010 cm−2 – − 1.70 × 1012 ± 8.33 × 1010 cm−2 at 100 kHz and − 2.26 × 1011 ± 1.02 × 1010 cm−2 – − 1.30 × 1012 ± 6.02 × 1010 cm−2 (70 Gy) at 1 MHz. The maximum variation in the interface trap charge density was in order of 1011 cm−2 at 1 MHz. The results indicate that the contribution of the oxide trap charge to radiation response of the Gd2O3 MOS capacitor is higher than that of the interface trap charges. The radiation sensitivities of the Gd2O3 MOS capacitor for 100 kHz and 1 MHz were determined as 59.2 ± 2.9 mV/Gy and 62.7 ± 2.9 mV/Gy, respectively. The percentage fading values (dose storage capability) measured in the time range of 25–145 min for 100 kHz varied from 2.2% to 11.4%.

Comparative study on slow-state near interface hole traps in NO and Ar annealed N-type 4H-SiC MOS capacitors by ultraviolet light

The characteristics of near interface charge trapping and releasing on n-type 4H-SiC MOS capacitors with NO and Ar passivation have been systematically investigated through time-dependent bias stress with ultraviolet light irradiation. Flat band voltage instability of the Ar annealed samples mainly results from electrons directly tunneling in and out of the near interface electron traps. However, hole trapping by the near interface hole traps (NIHTs) also need to be concerned for the NO annealed samples. It is found that part of the trapped holes cannot be easily released from the slow-state NIHTs, which may act as the positive fixed charge and induce the unrecoverable negative shift of threshold voltage. The results from XPS show that after the NO annealing, some of the intermediate oxidation states are converted to the strong Si≡N and Si–Ox–Ny bonds located in the transition layer, which may act as NIHTs and even suppress hydrofluoric acid etching. Thus, it is important to optimize nitrogen treatment in order to reduce the density of NIHTs induced in the 4H-SiC MOS devices.

Large photoelectric-gating effect of two-dimensional van-der-Waals organic/tungsten diselenide heterointerface

Photo- or photoelectric-gating modulation is a promising strategy for high-performance photodetectors, which amplifies photoresponsivity by long-lived trapped charges at the interface. However, the performance is normally limited by the uncontrollable trapping process. Here, we develop a large photoelectric-gating, which enhances interfacial charge trapping process by a van-der-Waals interface with an electric-gating tunable energy barrier in the band alignment. By synergy of photo-gating and electric-gating effects, responsivity and detectivity of 1,4-bis(4-methylstyryl)benzene/tungsten diselenide (WSe2) increase by 25-fold and 3-fold to 3.6 × 106 A/W and 8.6 × 1014 Jones. High-quality two-dimensional van-der-Waals interface is of great importance. Sufficient supply of gas-phase molecules in physical vapor deposition is pivotal to obtain such interface between organic crystal and WSe2. As an application, an electric-gating switchable photodetector has been developed, showing great potential of this strategy not only in high-performance photodetectors but also in new photoelectrical devices.