Interface Trap Annealing Research Articles

Mechanisms and models of interface trap annealing in positively-biased MOS devices

Abstract We propose a hydrogen anion (H$^-$) passivation mechanism of the interface trap annealing (ITA) in positively-biased metal-oxide-semiconductor (MOS) devices. It is demonstrated that, the protons (H$^+$) released in SiO$_2$ due to H$_2$ cracking on oxide traps can migrate into Si at relatively high temperature, therefore passivating the interfacial $P_b$ centers by capturing two electrons provided by the positive bias. This new mechanism explains the elimination temperature of about 100$^\circ$C in experiments, which is much lower than temperature above 220$^\circ$C predicted by the traditional H$_2$ passivation mechanism. We also derive analytic models of the ITA, based on the coupling transformation dynamics of oxide and interface traps, as well as the concept of hierarchically constrained dynamics in glassy materials. These models can universally describe a generation-to-elimination transition of $P_b$, and predict the enhanced elimination of $E'_\gamma$ as the annealing temperature is elevated. Moreover, we demonstrate that, the defect annealing models can be applied to analysis the nonmonotonic temperature dependence of the annealing of threshold voltage shift in nMOS devices. Our findings provide a theoretical basis for achieving the low temperature elimination of interface traps, and for setting the high temperature stages of accelerated aging and damage evaluations of MOS devices.

Effects of Bias and Temperature on Interface-Trap Annealing in MOS and Linear Bipolar Devices

This article reviews the effects of applied bias and temperature on Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface-trap buildup and annealing rates. Electrical and spectroscopic methods are described to estimate interface-trap densities at oxidized Si surfaces, in MOS capacitors and transistors, and in linear bipolar devices. Illustrative results provide insights into the kinetics and energetics of interface-trap annealing. Interface traps in MOS and linear bipolar devices anneal much more easily at 0 V bias than at positive or negative applied bias. Hydrogen transport and reactions play critical roles in interface-trap buildup and annealing processes. The complex interplay between H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> diffusion and H <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> drift is illustrated via coupled experimental and theoretical studies. Interface-trap annealing imposes significant constraints on hardness-assurance techniques. Current MOS standard tests that incorporate accelerated aging at elevated temperature at worst case, static, positive bias enable successful assessment of MOS devices in low-dose-rate environments. However, it is not similarly possible to use elevated-temperature irradiation and/or annealing at worst case, 0 V bias to predict low-dose-rate response for linear bipolar devices and ICs. Temperature-switching during irradiation appears to be a promising approach to address this issue.

Estimation of low-dose-rate degradation on bipolar linear circuits using different accelerated evaluation methods

The linear bipolar devices and integrated circuits (ICs) which are subjected to ionizing radiation exhibit parametric degradations due to current-gain decrease, and the amount of degradation on various types of bipolar devices is much more significant at low-dose-rate than at high-dose-rate. Such an enhanced low-dose-rate sensitivity (ELDRS) is considered to be one of the major challenges for radiation-tolerance testing intended for space systems. Therefore, it is of great significance to explore an efficient and practical test for the ELDRS in the linear bipolar devices and ICs. The different experiments have been implemented on four types of bipolar ICs for evaluating their responses to low-dose-rate irradiation. The experiments involve the dose rate switching approach performed under high to low-dose-rate irradiation and temperature switching approach performed under high to low temperature irradiation. Good agreement is observed between predictive curves obtained at dose rate switching irradiation and the low-dose-rate results, and the irradiation time for the dose rate switching approach is reduced from 4 months to a week. Further, the results also suggest that the device degradation rate can affect the prediction of the total dose. This is because the curves examined at different doses have a lot of overlap when the devices with fast degradation rates are performed. In addition to temperature switching irradiation, the radiation response of the same type of device is much more significant than that obtained in low-dose rate irradiation, and this method will shorten the irradiation time to 12 h. Based on the analysis of mechanisms behind the switched dose rate and temperature irradiation, switching temperature irradiation can accelerate the release of protons and buildup of interface traps, which is the key physical mechanism for ELDRS. Firstly, a higher irradiation temperature can enhance the transport of holes and release of protons to form interface traps, resulting in the enhanced degradation occurring at first dose examined. Further, the reducing temperature sequence suppresses the hydrogen dimerization process during the irradiation that follows, which is strongly temperature dependent and contributes to interface trap annealing. Moreover, further decrease in temperature can restrict the interface trap annealing because the barrier for this process is higher and it has less opportunity to take place at lower temperature. Additionally, the hydrogen molecules converted from hydrogen dimerization may extend the liberation of protons, by the hydrogen molecules cracking mechanisms, leading to the additional degradation. Therefore, the temperature switching irradiation is shown to be a conservative and efficient method for ELDRS in bipolar devices, and this provides an insight into hardness assurance testing.

Mechanism of the Saturation of the Radiation Induced Interface Trap Buildup

Ionizing radiation impact leads to degradation of electrical parameters of microelectronic devices. It is necessary to take this fact to account when dealing with microcircuits for space applications and high energy physics. Main physical reason of radiation-induced failures of spaceship and front end electronic equipment is buidup of interface traps at Si-SiO2 interface in semiconductor transistor structures. The original mechanism of interface trap annealing based on radiation induced charge neutralization (RICN) effect is presented. It is supposed that the positive charge of trapped holes in oxide is transformed through electron capture into a new defect (the AD center). The AD centers act as interface traps. The appearance of the A–D+ state leads to the annihilation of the AD center or annealing of interface trap. The annihilation process can be stimulated by radiation induced or substrate electrons. The competitive between accumulation and annihilation processes leads to saturation of the interface trap buildup. The value of density of interface trap in saturation depends on product of interface trap accumulation rate (Kacc)it and constant KAD which is function of thermal velocity, capture cross-section of AD center, generation rate and electron yield of radiation induced electrons. The extraction of these parameters allows explaining a known experimental data. The alternative mechanism of the interface trap saturation connected with the exhaustion of initial interface trap precursors is considered.

Mechanisms of Interface Trap Buildup and Annealing During Elevated Temperature Irradiation

Both enhanced interface trap buildup and interface trap annealing can occur during elevated temperature irradiation (ETI), depending on the temperature, total dose, and dose rate. In this paper we describe mechanisms that govern the rate-limiting processes of interface trap buildup and annealing during ETI. Hydrogenated oxygen vacancies can facilitate hydrogen dimerization at elevated temperatures. This results in the removal of protons that can create interface traps, so degradation is suppressed. Hydrogen dimerization becomes more competitive with degradation mechanisms as the concentration of protons near the interface increases and/or as temperature increases.

Root Cause of Charge Loss in a Nitride-Based Localized Trapping Memory Cell

Data retention loss mechanisms in nitride-based localized trapping memory devices are investigated with various electrical measurements and Medici simulations. First, the effect of program and erase cycles on device behavior is determined in terms of bottom oxide degradation and nitride charge profile evolution. Even if a strong degradation of the interface is observed, there is no important impact of this degradation on the cell behavior. However, the nitride charge profile evolves with cycling and leads to a three-pole electron-hole-electron profile over the channel region. Second, the interface trap annealing, the tunneling through the bottom oxide, and the lateral redistribution are studied in order to determine which mechanism plays the main role in the threshold voltage shift after cycling. The retention performance is dominated by a lateral redistribution of charges in the nitride layer.

Hot carrier induced interface trap annealing in silicon field effect transistors

Interface traps are created in metal-oxide-semiconductor field-effect transistors when hot carrier stressing is done with the maximum substrate current biasing condition (Vd=6.0 V and Vg=2.9 V). Unlike trapped oxide charge, the interface traps are not annealed by keeping the device at room temperature for 24 h. However, by applying reverse bias with high positive drain voltage Vd and negative gate voltage Vg, the hot carrier induced interface traps can be completely annealed out. This is confirmed by both transconductance and charge pumping measurements. There is a direct relationship between the substrate current and annealing of interface states by reverse stressing. The possible mechanism of interface state annealing is discussed.

Models of Si-SiO2 interface reactions

Si-SiO2 interface traps are typically annealed at a low temperature (300-450 degrees C) in the presence of hydrogen. Despite the widespread acceptance and importance of this technique, the rates and mechanisms of trap annealing are not well understood. Several recent papers have presented kinetic descriptions of Si-SiO2 interface trap annealing. The author investigates the application of these kinetic results to models of Si-SiO2 interface chemical reactions. Directions for further inquiries are described.

Chemistry of Si-SiO2 interface trap annealing

The kinetics and chemistry of Si-SiO2 interface trap annealing are examined in detail. Measurements of interface trap density Dit as a function of anneal time were performed with several process variables as parameters: oxide thickness, anneal ambient, temperature, bulk carrier type, metallization damage, and orientation. Experiments were carried out using rapid thermal processing and capacitance-voltage measurements of aluminum gate metal-oxide-semiconductor capacitors. Anneal temperature and crystal orientation have the strongest effect on the kinetics. 〈100〉 interfaces can be described by a power-law temporal variation; 〈111〉 kinetics are slightly more complicated. In both cases the experimentally observed anneal behavior is in conflict with the commonly used second-order surface recombination model. We propose a two-reaction model involving atomic hydrogen dimerization and hydrogen/interface trap reactions. This model sucessfully predicts anneal kinetics over a temperature range of 170–500 °C, representing a 106 dynamic range in anneal rates. The difference in anneal behavior between 〈111〉 and 〈100〉 interfaces is explained by postulating different trap anneal mechanisms for the Pb0 and Pb1 defect centers. This hypothesis is supported by trap production kinetics induced by extended anneals.