Effects of Bias and Temperature on Interface-Trap Annealing in MOS and Linear Bipolar Devices

Abstract

This article reviews the effects of applied bias and temperature on Si/SiO <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> interface-trap buildup and annealing rates. Electrical and spectroscopic methods are described to estimate interface-trap densities at oxidized Si surfaces, in MOS capacitors and transistors, and in linear bipolar devices. Illustrative results provide insights into the kinetics and energetics of interface-trap annealing. Interface traps in MOS and linear bipolar devices anneal much more easily at 0 V bias than at positive or negative applied bias. Hydrogen transport and reactions play critical roles in interface-trap buildup and annealing processes. The complex interplay between H <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sub> diffusion and H <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">+</sup> drift is illustrated via coupled experimental and theoretical studies. Interface-trap annealing imposes significant constraints on hardness-assurance techniques. Current MOS standard tests that incorporate accelerated aging at elevated temperature at worst case, static, positive bias enable successful assessment of MOS devices in low-dose-rate environments. However, it is not similarly possible to use elevated-temperature irradiation and/or annealing at worst case, 0 V bias to predict low-dose-rate response for linear bipolar devices and ICs. Temperature-switching during irradiation appears to be a promising approach to address this issue.