Density Of Interface Trap States Research Articles

Enhanced device performance of GaN high electron mobility transistors with in situ crystalline SiN cap layer

In this paper, a ∼2 nm in situ SiN cap layer on AlGaN barrier layer is grown, which is revealed to be crystalline using high-resolution cross-sectional transmission electron microscopy. Benefitting from superior interface quality of epitaxial crystalline SiN/AlGaN interface, the gate diodes with in situ SiN cap layer feature lower interface trap state density than that with GaN cap layer. By comparing the GaN high electron mobility transistors (HEMTs) with the conventional GaN cap layer, the GaN HEMTs with in situ SiN cap layer exhibit improved device performance, showing higher electron mobility, higher drain current, larger on/off current ratio, and higher transconductance. For breakdown characteristics, the devices with in situ crystalline SiN cap layer show prominent advantages over the GaN cap layer with a 30% breakdown voltage increase to 810 V.

Reduced trap state density in AlGaN/GaN HEMTs with low-temperature CVD-grown BN gate dielectric

In this Letter, low-temperature (400 °C) chemical vapor deposition-grown boron nitride (BN) was investigated as the gate dielectric for AlGaN/GaN metal–insulator–semiconductor high electron mobility transistors (MISHEMTs) on a Si substrate. Comprehensive characterizations using x-ray photoelectron spectroscopy, reflection electron energy loss spectroscopy, atomic force microscope, high-resolution transmission electron microscopy, and time-of-flight secondary ion mass spectrometry were conducted to analyze the deposited BN dielectric. Compared with conventional Schottky-gate HEMTs, the MISHEMTs exhibited significantly enhanced performance with 3 orders of magnitude lower reverse gate leakage current, a lower off-state current of 1 × 10−7 mA/mm, a higher on/off current ratio of 108, and lower on-resistance of 5.40 Ω mm. The frequency-dependent conductance measurement was performed to analyze the BN/HEMT interface, unveiling a low interface trap state density (Dit) on the order of 5 × 1011–6 × 1011 cm−2 eV−1. This work shows the effectiveness of low-temperature BN dielectrics and their potential for advancing GaN MISHEMTs toward high-performance power and RF electronics applications.

Influence of post fabrication annealing on device performance of InAlN/GaN high electron mobility transistors

In this study, effect of post-fabrication annealing (PFA) on the electrical performance of the InAlN/GaN high electron mobility transistors (HEMTs) has been investigated. With PFA, the gate Schottky barrier height increases by 94 % (from 1.03 eV to 2.00 eV) and the interface trap state density (Dit) is reduced by 27 %. Compared with the device without PFA, a higher on-current (11 %), a larger on/off current ratio (∼1 order), a higher transconductance (3 %), a reduced gate leakage current (84 %) and a lower subthreshold swing (10 %) are recorded in device with PFA. In addition, the improved electron mobility is observed and the reduction of polarization Coulomb field (PCF) scattering is proven in device with PFA due to the enhancement of polarization electrical field in InAlN/GaN heterostructure.

Investigating the effect of aluminum oxide fixed charge on Schottky barrier height in molybdenum oxide-based selective contacts

A tunneling atomic layer deposited (ALD) AlOx layer was inserted in a Si|SiOx|AlOx|MoOx|metal tunnel diode structure to investigate the impact of fixed interface charge on Schottky barrier height. ALD AlOx provides a synthesis-tunable fixed charge and can provide excellent field effect passivation at the SiOx|AlOx interface. A large (>1 × 1012 q.cm−2) negative fixed charge density was expected to decrease Schottky barrier height on p-type silicon and increase Schottky barrier height on n-type silicon by up to 0.4 eV based on an electrostatic model. Fixed charge density and interface trap state density were measured using a thick layer of AlOx in metal oxide semiconductor capacitor structures (MOSCAPs); Schottky barrier height and specific contact resistivity were measured using a tunneling-active layer of AlOx in contacted structures with MoOx. In some samples, HfOx interface layers were inserted between AlOx and silicon to quench the fixed negative charge. The Schottky barrier height was found to vary with processing conditions but did not have a strong correlation with expected fixed charge density. Thus, while fixed charge may play a role in determining the Schottky barrier height, other parameters also have significant affect. Further work is needed to minimize contact resistivity and elucidate other factors impacting the Schottky barrier height.

Analysis and Classification of Charge Trapping States in β-Ga2O3 Mosfets Using I-V and C-V in Dark and Illumination Conditions

Beta-gallium oxide (β-Ga2O3) is a promising ultra-wide bandgap semiconductor for high power applications. Its breakdown electric field of 8 MV cm-1, a Baliga figure of merit 3-10 times larger than that of SiC and GaN, and the ability to be grown from the melt make it highly attractive for the semiconductor industry. Significant improvements have been made in β-Ga2O3 device performance for both high power and high frequency operation. Currently, aluminum oxide (Al2O3) is the preferred gate dielectric for β-Ga2O3 transistors due to its electron and hole barriers, and similar atomic structure. Process optimizations to improve the interface quality has been explored by chemical treatments1 to the β-Ga2O3 surface before dielectric deposition, during the deposition of Al2O3, and with post-deposition annealing. Therefore, there is a desire to understand and classify defects at and near the Al2O3/β-Ga2O3 interface. Here, we report on a study of the Al2O3/β-Ga2O3 interface and border traps in planar depletion-mode β-Ga2O3 MOSFETs using DC I-V and C-V measurements in dark and under illumination with wavelengths from 730 nm (1.7 eV) to 230 nm (5.4 eV). The MOSFETs are fabricated on a 50 nm Si-doped epitaxial layer with a target doping concentration of 2.4 x 1018 cm-3 grown on a (010) semi-insulating β-Ga2O3 substrate. A Ti/Al/Ni/Au metal stack is deposited and annealed to form the Ohmic contacts. Plasma-assisted atomic layer deposition (PE-ALD) is used to deposit the 20 nm Al2O3 gate dielectric. The fabricated transistor structures have a LG of 1.94 µm, LS of 0.5 µm, and LD varying from 0.5 µm, 5.5 µm, and 10.5 µm. Measurements were performed at room temperature. Most FETs exhibited a threshold voltage of approximately -4 V, high linearity, and ION/IOFF ratios between 107 – 109. Using the conductance method, we extract an interface trap state density, Dit, of 3 x 1011 eV-1 cm-2 up to 0.44 eV below the conduction band. Illumination is used to obtain deep trap concentration and behavior. We observe little to no change in IV and CV curves for wavelengths above 365 nm but see a significant voltage shift in the CV curves for illumination wavelengths between 365 nm (3.4 eV) to 230 nm (5.4 eV), indicating significant activated traps from 3.4 eV below the conduction band. We will present the analysis of photo-assisted CV and stress-CV curves at various wavelengths to obtain densities of fixed, fast, and slow trap states and discuss their impact on device performance.

Effect of Biaxial Bending Strains on the Electrical Characteristics of Flexible Low-Temperature Polysilicon Thin-Film Transistors

The change of electrical properties of flexible low-temperature polysilicon (LTPS) thin-film transistors (TFTs) under biaxial bending strains was studied. Biaxial strains were applied using a ring-on-ring bending test rig. The magnitude of the strain was determined by theoretical calculations and finite-element simulations. With an increase in strain, the transfer curve shifted to a negative bias. At a biaxial strain level of 12%, the threshold voltage decreased by 27%, the field-effect mobility decreased by 13%, and the subthreshold slope increased by 25%. It had a more significant effect on the property changes than the uniaxial strain; this difference may be attributed to additional trap states generated by the biaxial strain. The analysis showed that the trap density increased when the strain level increased. The contributions of the increases in the grain-boundary trap state density and the interface trap state density to the degradation in the electrical properties were derived to be 10% and 90%, respectively. After removal of the biaxial bending strains, the electrical performance showed recovery behavior, but the performance could not return fully to its original state.

Low density of interface trap states and temperature dependence study of Ga2O3 Schottky barrier diode with p-NiOx termination

This work acquires a vertical β-Ga2O3 Schottky barrier diode (SBD) with the advanced termination structure of p-type NiOx and n-type β-Ga2O3 heterojunctions and coupled field plate structures to alleviate the crowding electric field. A Ga2O3 SBD delivers an average breakdown voltage of 1860 V and a specific on-resistance of 3.12 mΩ cm2, yielding a state-of-the-art direct-current Baliga's power figure of merit of 1.11 GW/cm2 at an anode area of 2.83 × 10−5 cm2. In addition, the Ga2O3 SBD with the same fabrication process at a large area of 1.21 × 10−2 cm2 also presents a high forward current of 7.13 A, a breakdown voltage of 1260 V, and a power figure-of-merit of 235 MW/cm2. According to dynamic pulse switching and capacitance-frequency characteristics, an optimized p-NiOx/Ga2O3 interface with a maximum trap density of 4.13 × 1010 eV−1 cm−2 is delivered. Moreover, based on the forward current-voltage measurement at various temperatures, the physics behind a forward conduction mechanism is illustrated. Ga2O3 SBDs with p-NiOx/n-Ga2O3 heterojunction termination, field plate, high power figure of merit, and high quality interface as well as suppressed resistance increase after dynamic pulse switching, verifying their great promise for future high power applications.

Effective suppression of nanotextured black silicon surface recombination channels by aluminum oxide: comparison from sputtered and ALD grown films

Effective surface passivation of nano-textured silicon (NT-Si) using sputtered aluminum oxide (AlO x ) films is demonstrated and compared with the atomic layer deposition (ALD) grown AlO x films. Silver-assisted wet chemical etching is used to obtain sub-wavelength size features of black NT-Si, and then the NT-Si surface is chemically polished to minimize the surface defect states that act as trap centres for charge carriers. The NT-Si surface passivation is characterized by the density of interface trap states (D it) and the fixed charge density (Q f), which also correlate with the surface recombination rate (S eff). For the sputtered AlO x films, the estimated D it and Q f are ∼4 × 1011 eV−1 cm−2 and ∼7 × 1012 cm−2, respectively, yielding the S eff of ∼34 cm s−1. Whereas, for the ALD AlO x films the estimated D it, Q f, and S eff are ∼1.6 × 1011 eV−1 cm−2, ∼7.4 × 1012 cm−2, and ∼20 cm s−1, respectively. The chemical and field-effect passivation are evident for the ALD AlO x films with the reduced S eff. However, the sputtered AlO x films have shown only an indication of field-effect passivation with a small variation in the Q f. Still, the observed larger D it is due to the sputtering damage on the NT-Si surface compared to ALD AlO x films.

Comparative Study on the Separate Extraction of Interface and Bulk Trap Densities in Indium Gallium Zinc Oxide Thin-Film Transistors Using Capacitance–Voltage and Current–Voltage Characteristics

The interface and bulk trap densities were separately extracted from self-aligned top-gate (SA-TG) coplanar indium gallium zinc oxide (IGZO) thin-film transistors (TFTs) using the low-frequency capacitance–voltage (C–V) characteristics and space-charge-limited current (SCLC) under the flat-band condition. In the method based on the C–V curve, the energy distribution of the interface trap density was extracted using the low-frequency C–V characteristics, and that of the bulk trap density was obtained by subtracting the density of interface trap states from the total subgap density of states (DOS) at each energy level. In the SCLC-based method, the energy distribution of the bulk trap density was extracted using the SCLC under the flat-band condition at high drain-to-source voltages, and that of the interface trap density was obtained by subtracting the density of bulk trap components from the total subgap DOS at each energy level. In our experiments, the two characterization techniques provided very similar interface and bulk trap densities and showed that approximately 60% of the subgap states originate from the IGZO/SiO2 interface at the conduction band edge in the fabricated IGZO TFTs, although the two characterization techniques are based on different measurement data. The results of this study confirm the validity of the characterization techniques proposed to separately extract the interface and bulk trap densities in IGZO TFTs. Furthermore, these results show that it is important to reduce the density of interface trap states to improve the electrical performance and stability of fabricated SA-TG coplanar IGZO TFTs.

Investigation of charge trapping mechanism in MoS2 field effect transistor by incorporating Al into host La2O3 as gate dielectric

The charge trapping effect plays a key role in multi-bit memory devices and brain-like neuron devices. Herein, MoS2 field effect transistors are fabricated, incorporating Al into host La2O3 as the gate dielectric, which exhibit excellent electrical properties with an on–off ratio in the memory window of ∼106 and a memory window ratio of ∼40%. Furthermore, the charge trapping and de-trapping processes were systematically studied, and the time constants are obtained from time-domain characteristics. Making use of the charge trapping effect, the threshold voltage of the device can be continuously adjusted. The oxide layer trap density and the interface state trap density are extracted using the charge separation method. These theoretical studies provide a deeper understanding of ways to control the charge trapping process, benefitting the commercialization of two-dimensional electronic devices and the development of new charge trapping devices.

First Demonstration of the Improvement of Metal/High-K Interface Roughness Utilizing in-Situ NH3/N2 Remote Plasma Preferred: Poster

In this work, we demonstrate a high-k/III-V gate stack interface treatment utilizing NH3/N2 in-situ remote plasma (RP). Through such treatment, the density of interface trap states (Dit) is dramatically reduced and the surface morphology of the Al2O3 is modified. Aside from the sharp decline in the Dit, the Al2O3 layer becomes smoother and thus results in a significant enhancement in the surface roughness mobility combining the observations from experiment as well as simulation results. From the Atomic Force Microscope (AFM) we observe an improvement of surface roughness from 0.332 nm to 0.252 nm. Also, we found a considerable enhancement in the surface roughness mobility from 7 x 1024 to 1.5 x 1026 cm2/Vs. Moreover, the mid-gap trap decreases from 5.7 x 1012 to 1.8 x 1012 cm-2/eV-1, which once again emphasis the achievements of this work.

Effective suppression of nano-textured black silicon surface recombination channels through sputtered aluminum oxide: A comparison study with ALD grown films.

This accepted manuscript was withdrawn on 2 November 2020 on the author's request.In this work, the effective surface passivation of nano-textured silicon (NT-Si) using sputtered aluminum oxide (AlOx) films has been demonstrated and established a comparison with atomic layer deposition (ALD) grown AlOx films. Silver assisted wet chemical etching (SAWCE) is used to prepare optically black NT-Si. Sub-wavelength size features of NT-Si surface optimized to control the surface defect states which act as trap centres for charge carriers and proportional to the surface area. Sputtered and ALD grown AlOx films used to passivate the NT-Si surfaces are analyzed primarily in context of available trap centres. The AlOx/NT-Si interface is quantified by the density of interface trap states (Dit) and the total fixed charge (Qf) that correlated with effective surface recombination velocity (Seff) of carriers. The estimated Dit and Qf of sputtered AlOx films are ~4 x 1011 eV-1cm-2 and ~7 x 1012 cm-2, respectively which results in the Seff of ~37 cm/s due to the field-effect passivation. While the Dit and Qf of ALD grown AlOx films are 1.1 x 1011 eV-1cm-2 and ~7.8 x 1012 cm-2 results in the Seff of ~22 cm/s owing to both the chemical and field-effect passivation.

(Invited) Quantum Multi-Body Interactions in Semiconducting WSe2 and C60-Graphene Hybrids for High-Performance Photodetectors

In this work we will discuss the use of halide-assisted low-pressure chemical vapour deposition (HA-LPCVD) with NaCl to help facilitate the growth of monolayer WSe2 at low growth temperatures of ~ 750oC, which is lower than the typical temperatures needed with conventional CVD for realizing 1L WSe2. Moreover, we experimentally probed the quantum multi-body interactions in 1L WSe2 ascribed to excitons, trions and other localized states by analyzing the temperature-dependent photoluminescence spectra. A 1L WSe2 based photodetector was fabricated using Al contacts, which shows a high photoresponsivity, and the interface state trap density of the Al/WSe2 junction was computed to be extremely low. Hybrids of two-dimensional (2D) graphene with fullerene (C60) molecules were also fabricated using electrophoretic deposition, where the C60 clusters are electrically charged upon the application of an external bias in a polar solvent. A low energy shift in the Fermi level EF ~ 140 meV was calculated for the hybrids. When the hybrid devices were irradiated with a broadband white light source and a tunable laser source (with wavelength λ ranging from ~ 400-1100 nm), a strong photoresponse was evident, in contrast to the bare graphene devices which appeared unresponsive. We will discuss the strong photo-response of the C60-graphene hybrids reported here which we attribute to the doping enhancement arising in the graphene upon the adsorption of C60.

(Invited) Quantum Multi-Body Interactions in Semiconducting WSe2 and C60-Graphene Hybrids for High-Performance Photodetectors

In this work we will discuss the use of a halide-assisted low-pressure chemical vapor deposition (HA-LPCVD) with NaCl to help facilitate the growth of monolayer WSe2 at low growth temperatures of ~ 750oC, which is lower than the typical temperatures needed with conventional CVD for realizing monolayer (1L) WSe2. Moreover, we experimentally probed the quantum multi-body interactions in 1L WSe2 ascribed to excitons, trions and other localized states by analyzing the temperature-dependent photoluminescence spectra. A 1L WSe2 based photodetector was fabricated using Al contacts, which shows a high photoresponsivity, and the interface state trap density (Dit) of the Al/WSe2 junction was computed to be extremely low. Hybrids of two-dimensional (2D) graphene with fullerene (C60) molecules were also fabricated using electrophoretic deposition, where the C60 clusters are electrically charged upon the application of an external bias in a polar solvent. A low energy shift in the Fermi level EF ~ 140 meV was calculated for the hybrids. When the hybrid devices were irradiated with a broadband white light source and a tunable laser source (with wavelength λ ranging from ~ 400-1100 nm), a strong photoresponse was evident, in contrast to the bare graphene devices which appeared unresponsive. We will discuss the strong photo-response of the C60-graphene hybrids reported here which we attribute to the doping enhancement arising in the graphene upon the adsorption of C60.

Measurements and simulations of surface radiation damage effects on IFX and HPK test structures

Radiation damage effects at High Luminosity LHC (HL-LHC) expected fluences and total ionizing doses (TID) will impose very stringent constraints in terms of radiation resistance of silicon detectors. In this work, we address the effects of surface damage on detectors fabricated on p-type substrates by two different foundries. Starting from standard test structure measurements, the interface trap state density and the oxide charge can be extracted for each specific foundry before and after irradiation with X-rays with doses ranging from 0.05 to 100 Mrad(SiO2). These parameters are then used as inputs to the Technology-CAD simulation tools, aiming at evaluating the effects of oxide charge density and interface trap density variation with the dose on MOS capacitor capacitances and interstrip resistances. The good agreement between simulation results and measurements would support the use of the model as a predictive tool to optimize the design and the operation of novel silicon detectors in the HL-LHC scenario.

Investigation of annealed, thin(∼2.6 nm)-Al2O3/AlGaN/GaN metal-insulator-semiconductor heterostructures on Si(111) via capacitance-voltage and current-voltage studies

Annealed, thin(∼2.6 nm)-Al2O3/AlGaN/GaN metal-insulator-semiconductor (MIS) heterostructures on Si(111) are fabricated and studied via capacitance–voltage (C–V) measurements to quantify densities of fast and slow interface trap states and via current–voltage (I–V) measurements to investigate dominant gate current leakage mechanisms. Dual-sweep C–V measurements reveal small voltage hysteresis (∼1 mV) around threshold voltage, indicating a low density of slow interface trap states of ∼109 cm−2. Frequency-dependent conductance measurements show fast interface trap state density ranging from 8 × 1012 to 5 × 1011 eV−1 cm−2 at energies from 0.275 to 0.408 eV below the GaN conduction band edge. Temperature-dependent I–V characterizations reveal that trap-assistant tunneling (TAT) dominates the reverse-bias carrier transport while the electric field across the Al2O3 ranges from 3.69 to 4.34 MV cm−1, and the dominant Al2O3 trap state energy responsible for such carrier transport is identified as 2.13 ± 0.02 eV below the Al2O3 conduction band edge. X-ray photoelectron spectroscopy measurements on Al2O3 before and after annealing suggest an annealing-enabled reaction between Al-O bonds and inherent H atoms. Overall, we report that annealed, thin-Al2O3 dielectric is an effective (Al)GaN surface passivation alternative when minimizing passivation-associated parasitic capacitance is required, yet non-ideal for significantly suppressing gate leakage current in MIS structures due to the governing TAT carrier transport mechanism.

Combustion synthesis of electrospun LaInO nanofiber for high-performance field-effect transistors

One-dimensional semiconductor nanofibers are regarded as ideal materials for electronics due to their distinctive morphology and characteristics. In this work, La-doped indium oxide (LaInO) nanofibers are fabricated as the channel layer to reduce O vacancies and the density of interface trap states; this is clearly confirmed by investigating the stability under positive bias stress and the capacitance–voltage for field-effect transistors (FETs). The In2O3 nanofiber FETs optimized by doping with 5 mol% La exhibit excellent electrical performance with a mobility of 4.95 cm2 V–1 s–1 and an on/off current ratio of 1.1 × 108. In order to further enhance the electrical performance of LaInO nanofiber FETs, ZrAlOx film, which has a high dielectric constant, is employed as the insulator for the LaInO nanofiber FETs. The LaInO nanofiber FETs with ZrAlOx insulator have a high mobility of 13.5 cm2 V–1 s–1. These findings clearly indicate the great promise of La-doped In2O3 nanofibers in future one-dimensional nanoelectronics.

Measurement of the Variable Surface Charge Concentration in Gallium Nitride and Implications on Device Modeling and Physics

We have evaluated the density of interface trap states (Dit) at the surface of a GaN/AlGaN/GaN heterojunction by the previously described gated van der Pauw experiments, as well as by a UV assisted gated van der Pauw method, described in this article. The obtained Dit values are about two orders of magnitude lower than assumed by the surface-donor theory and three orders of magnitude lower than required to compensate the polarization surface charge in GaN. Previous experimental studies using a variety of other techniques reported similarly low Dit values. We hence conclude that variable midgap surface-charge is not responsible for the formation of the two-dimensional electron gas, and cannot compensate for the large surface polarization charge in GaN. A yet unexplained polarization self-compensating (PSC) surface charge must be invoked to account for experiments. A few comments about the physical nature of the proposed PSC charge are provided.

Al2O3/Si0.7Ge0.3(001) & HfO2/Si0.7Ge0.3(001) interface trap state reduction via in-situ N2/H2 RF downstream plasma passivation

A novel method for passivating the interface between Si0.7Ge0.3 using an in-situ downstream RF plasma consisting of a nitrogen-rich mixture of H2 and N2 gases at 250 °C prior to atomic layer deposition (ALD) of Al2O3 and HfO2 was demonstrated. XPS spectra of the interface with Al2O3 indicated the presence of a nitride layer enriched in SiONx and depleted in Ge relative to the substrate. The electrical properties of this interface were characterized using I-V and variable frequency C-V measurements of MOS capacitors. The N2/H2 plasma passivation process produced a reduced density of interface trap states (Dit) and lower gate leakage compared with ex-situ HF clean and sulfur passivation for Al2O3 gate oxides. The lowered leakage current and Dit observed compared with HF(aq) or sulfur-passivated surfaces were consistent with enhanced oxide nucleation due to N2/H2 plasma passivation lowering carbon surface contamination and dangling bonds. TEM/EELS analysis of the interface was consistent with the presence of a thin interfacial nitride layer suppressing the formation of GeO bonds at the interface to form an SiOx-rich interlayer (IL).

Surface Treatments on the Characteristics of Metal–Oxide Semiconductor Capacitors

The properties of metal-oxide semiconductor (MOS) capacitors with different chemical treatments have been examined in this study. A MOS capacitor consists of an Al2O3/n-GaN/AlN buffer/Si substrate. Four chemical treatments, containing organic solvents, oxygen plasma and BCl3 plasma, dilute acidic and alkali solvents, and hydrofluoric acid, were used to reduce the metal ions, native oxides, and organic contaminants. The n-GaN surface was treated with these chemical treatments before Al2O3 was grown on the treated n-GaN surface to reduce the interface state trap density (Dit). The value of Dit was calculated using the capacitance–voltage curve at 1 MHz. The Dit of a u-GaN surface was modified using various solutions, which further influenced the contact properties of GaN.