Interface State Density Dit Research Articles

Inversion channel mobility and interface state density of diamond MOSFET using N-type body with various phosphorus concentrations

We investigated the phosphorus concentration (NP) dependence of the field-effect mobility μFE and interface state density Dit in inversion channel diamond metal-oxide-semiconductor field-effect transistors (MOSFETs). The inversion channel diamond MOSFETs are potentially applicable in high-frequency, high-current, and high-voltage devices because of the material's excellent properties such as a wide bandgap, high breakdown electric field, high carrier mobility, and high thermal conductivity. However, the influences of device design parameters, such as NP in an n-type body and the oxide layer material, on the electrical characteristics of inversion channel diamond MOSFETs have not yet been reported. In this study, we fabricated inversion channel diamond MOSFETs using n-type bodies with various NP values. For decreased NP in the n-type body, μFE was increased, while Dit was decreased. Using the n-type body with the lowest NP of 2 × 1015 cm−3, the maximum μFE of 20 cm2/V·s and the minimum Dit of 1 × 1013 cm−2·eV−1 were obtained. In addition, an inverse correlation was found between μFE and Dit. Specifically, in the low-gate-voltage region of the drain current–gate voltage characteristics, μFE and Dit were strongly inversely correlated. The high Dit suggests that most holes are trapped in the interface state as strong scattering factors in the low-gate-voltage region. Lower Dit values are therefore important for obtaining higher μFE values, the same as in Si and SiC.

Exploration of the impact of interface states density on the specific contact resistivity in TiSix/n+-Si Ohmic contacts through high-low frequency method

In our previous work, a reduction of specific contact resistivity (ρc) in TiSix/n+-Si Ohmic contacts by ∼21% has been achieved with proper Ge Pre-amorphization Implantation (PAI). In this work, the mechanism behind such an improvement using Ge PAI is explored experimentally. Versatile characterizations including current–voltage (I–V), capacitance–voltage (C–V) measurements and cross-sectional transmission electron microscopy (XTEM) are performed and analyzed. High-low frequency method is used to extract the responsive interface states density (Dit) of TiSix/n-Si Schottky diodes with and without Ge PAI. It is demonstrated that in TiSix/n+-Si Ohmic contacts, the ρc reduction by ∼21% with Ge PAI should be ascribed to the reduction of Dit at TiSix/n-Si interface. From the distribution of Dit, it can be inferred that a part of shallow level defects can be annihilated after annealing for TiSix/n-Si with Ge PAI, but deep level traps still exist. A further discussion about the relationship between Dit and ρc is tentatively provided.

Influence of vacuum annealing on interface properties of SiC (0001) MOS structures

We investigated the influence of vacuum annealing on the interface properties of silicon carbide (SiC) metal–oxide–semiconductor (MOS) structures. For as-oxidized and nitric oxide (NO)-annealed samples, the interface state density (Dit) near the conduction band edge (EC) of SiC did not increase by subsequent vacuum annealing. For phosphoryl chloride (POCl3)-annealed samples, in contrast, Dit at EC − 0.2 eV increased from 1.3 × 1010 to 2.2 × 1012 cm−2 eV−1 by vacuum annealing, and the channel mobility of MOS field effect transistors (MOSFETs) decreased from 109 to 44 cm2 V−1 s−1. The mechanism of the observed increase in Dit was discussed based on the results of the secondary ion mass spectrometry measurement.

Control of plasma-CVD SiO2/InAlN interface by ultrathin atomic-layer-deposited Al2O3 interlayer

To control a plasma-CVD SiO2/InAlN interface, the insertion of an ultrathin Al2O3 interlayer deposited by atomic layer deposition was investigated. The thickness of the Al2O3 interlayer was varied between 0.5 and 2 nm. Compared with the direct deposition of SiO2, the insertion of a 2 or 1 nm thick Al2O3 interlayer resulted in the similar interface state density Dit distribution. However, a significant reduction in Dit was achieved by using a 0.5 nm thick Al2O3 interlayer. Slight oxidation of the InAlN surface under the 0.5 nm thick Al2O3 interlayer was observed by X-ray photoelectron spectroscopy (XPS). This result indicated that a native oxide/InAlN interface was formed without disorder beneath the 0.5 nm thick Al2O3 interlayer, while plasma damage was prevented at the interface. On the other hand, the density of positive charges at the interface increased with the Al2O3 interlayer thickness. The generation process of the interface charge is discussed on the basis of XPS data.

Influence of post-deposition annealing on characteristics of Pt/Al2O3/β-Ga2O3 MOS capacitors

We investigated the influence of post-deposition annealing (PDA) temperature on the characteristics of Pt/Al2O3/n-β-Ga2O3 MOS capacitors. Electrical properties such as the flatband voltage (Vfb) shift, Vfb hysteresis, fixed charge (QIL), interface state density (Dit) and leakage current could be divided into two groups such as a low PDA temperature range below 600 °C and a high temperature range above 700 °C. The capacitors with a low PDA temperature exhibited superior electrical properties compared to the capacitors with a high PDA temperature, excluding leakage current property. We found that 700 °C is a critical PDA temperature because Al2O3 film starts to crystallize and solid-solution reaction of Al2O3 gate insulator and β-Ga2O3 substrate also occurs, resulting in Ga diffusion into the Al2O3 film and large roughness at Al2O3/β-Ga2O3 interface. These lead to a large Dit and positive Vfb shift at 700 °C. Even in a low PDA temperature range, it is clear that capacitor at 300 °C exhibited superior electrical properties of Vfb shift of −0.23 V, QIL of 4.1 × 1011 cm−2, and Dit (1.6 × 1012 eV−1 cm−2 at Ec-E = 0.4 eV). Based on these experimental data, lower PDA temperature of 300 °C is suitable.

Wet chemical surface smoothing method for improving surface passivation on monocrystalline silicon

We have adopted an appropriate HNO3-HF-H2O mixed solution to smooth the surface of the silicon wafer. The solution evidently reduces the surface roughness of double-side chemical polished c-Si, and the interface state density (Dit) decreases from 1011 cm−2 eV−1 to 1010 cm−2 eV−1 at the mid-gap energy level. Therefore the effective minority carrier lifetime (τeff) of silicon wafer increases from 259 us to 273 us. Replace it with textured c-Si, the weighted reflectance of silicon increases to 15.9% from 11.97%; and τeff is also up to the highest value of 437 us at 1000 s from 221 us of as-prepared textured silicon.

Effect of Grinding-Induced Stress on Interface State Density of SiC/SiO2

Back-grinding process was applied to the 4H-SiC (0001) epitaxial wafers. We found that the parameters about stress increased after back-grinding process. In our work, the characterization of stress on interface state density (Dit) of SiC/SiO2 was investigated. Furthermore, the absorption of peak frequencies was also observed by fourier transform infrared spectroscopy attenuated total reflection (ATR-FTIR) analysis, and the Dit of SiC/SiO2 was obtained by quasi-static capacitance voltage (QSCV) measurement as well as C-φs method. The above results suggested that the Dit increased with the increasing grinding-induced stress.

Stress-induced charge trapping and electrical properties of atomic-layer-deposited HfAlO/Ga2O3 metal–oxide–semiconductor capacitors

Electrical properties and trapping characteristics of an atomic layer deposited Al-rich HfAlO/β-Ga2O3 capacitor were evaluated via constant-voltage stress (CVS), capacitance–voltage (C–V), and current–voltage (I–V) measurements. The magnitude of the stress-induced charge trapping increases with increasing voltage and time. The effective charges (Neff) including the ‘border’ traps located in near-interface oxide, interface traps (Dit) of HfAlO/β-Ga2O3 interface, and fixed charges contribute significantly to the observed charge trapping, and it is found that interface traps contribute more under a large stress bias, compared with ‘border’ traps. In addition, the effective charge density is increased with stress time, implying that the contribution of negative sheet charges during the CVS process might not be negligible. Measurements of oxide permittivity (10.74), interface state density (Dit ~ 1 × 1012 eV−1 cm−2), and gate leakage current (1.18 × 10−5 A cm−2 at +10 V) have been extracted, suggesting the great electrical properties of Al-rich HfAlO/β-Ga2O3 MOSCAP. According to the above analysis, Al-rich HfAlO is an attractive candidate for normally off Ga2O3 transistors.

Demonstration and analysis of channel mobility, trapped electron density and Hall effect at SiO2/SiC (03) interfaces

Low interface state density (Dit) and high field-effect mobility (μfe) at SiO2/4H-SiC (03) Metal-oxide-semiconductor (MOS) interfaces are known. In order to understand the behavior and the scattering mechanisms induced electrons in more detail, we fabricated the Hall-bar lateral MOSFETs on the 4H-SiC (03) substrate with various channel doping concentrations and evaluated the trapped electron densities and the Hall mobilities by split capacitance–voltage and Hall-effect measurements. Our results demonstrated that more than 80% of the induced electrons at the SiO2/4H-SiC MOS (03) interfaces contribute to the current conduction as the free electrons. The majority of the electron traps seemed to be located mainly at the edge of the conduction band because the trapped electron density increased around the threshold voltage and was saturated in the high gate voltage region.

Characteristics of Al2O3/native oxide/n-GaN capacitors by post-metallization annealing

This work investigated characteristics of Al2O3/native oxide/n-GaN MOS capacitors by post-metallization annealing (PMA). A native oxide interlayer which composed of ε- and γ-Ga2O3 phases (Native oxide) and the reduced amount of one (Reduced) on n-GaN were prepared by cleaning only a sulfuric acid peroxide mixture (SPM) and both SPM and buffered hydrofluoric acid, respectively. The effect of trimethylaluminum precursor on removal of a native oxide layer was not observed during Al2O3 deposition using atomic layer deposition. An as-grown capacitor (Native oxide) exhibited a small flatband voltage (Vfb) hysteresis of ∼30 mV and a large frequency dispersion, suggesting that the initial growth of the Al2O3 resulted in the formation of electrical defects on the GaN surface. Both the Vfb hysteresis and frequency dispersion were drastically improved by PMA of the device at 300 °C. The positive fixed charge values (QIL) estimated from the relationships between capacitance equivalent thickness and Vfb were +6.1 × 1012 and +0.4–1.0 × 1012 cm−2 for as-grown and PMA-processed capacitors in the PMA temperature range of 300 °C–600 °C, respectively. The interface state density (Dit) determined using a conductance method was also significantly reduced (by an order of magnitude) after PMA processing at 300 °C. These trends in the QIL and Dit data were observed in both the Native oxide and Reduced capacitors, indicating that this interlayer does not greatly affect fixed charge generation at the Al2O3/native oxide and Al2O3/modified native oxide interfaces. As a result, two types of treatments result in insignificant difference in the electrical properties of the capacitors.

Improved Interface and Electrical Properties by Inserting an Ultrathin SiO2 Buffer Layer in the Al2O3/Si Heterojunction

AbstractAn ultrathin SiO2 interfacial buffer layer is formed using the nitric acid oxidation of Si (NAOS) method to improve the interface and electrical properties of Al2O3/Si, and its effect on the leakage current and interfacial states is analyzed. The leakage current density of the Al2O3/Si sample (8.1 × 10−9 A cm−2) due to the formation of low‐density SiOx layer during the atomic layer deposition (ALD) process, decreases by approximately two orders of magnitude when SiO2 buffer layer is inserted using the NAOS method (1.1 × 10−11 A cm−2), and further decreases after post‐metallization annealing (PMA) (1.4 × 10−12 A cm−2). Based on these results, the influence of interfacial defect states is analyzed. The equilibrium density of defect sites (Nd) and fixed charge density (Nf) are both reduced after NAOS and then further decreased by PMA treatment. The interface state density (Dit) at 0.11 eV decreases about one order of magnitude from 2.5 × 1012 to 7.3 × 1011 atoms eV−1 cm−2 after NAOS, and to 3.0 × 1010 atoms eV−1 cm−2 after PMA. Consequently, it is demonstrated that the high defect density of the Al2O3/Si interface is drastically reduced by fabricating ultrathin high density SiO2 buffer layer, and the insulating properties are improved.

Comprehensive Study and Design of High-k/SiGe Gate Stacks with Interface-Engineering by Ozone Oxidation

The influence of the ozone oxidation conditions on the interfacial and electrical properties of high-k/SiGe gate stacks was investigated by using a step-by-step fabrication procedure. The relationship between the electrical characteristics and the corresponding interfacial chemical structures revealed that a long oxidation time was necessary to obtain a high-quality interlayer (IL), whereas adverse in terms of interface state density (Dit) and equivalent oxide thickness (EOT) scaling. This conclusion suggested us to employ a post-high-k-deposition oxidation (post-O) method to fabricate high-k/IL/SiGe gate stacks, in which the ozone oxidation was carried out after the deposition of the high-k layer. Compared with the step-by-step method, the post-O method could realize an ultrathin IL over a long oxidation time, owing to the reduced oxidation rate. Consequently, a well-balanced high-k/IL/SiGe gate stack with an ultrathin Ge-free IL of 0.26 nm, low gate leakage at VFB-1 of 6 × 10−4 A/cm2, and Dit as low as 2.2 × 1012 eV−1cm−2 was obtained.

Gd-Doped HfO2 Memristor Device, Evaluation Robustness by Image Noise Cancellation and Edge Detection Filter for Neuromorphic Computing

This paper estimates the robustness of non-volatile device (NVM) Gadolinium (Gd) doped Hafnium oxide (HfO2) nanoparticles (NPs) based memristor which was constructed using as-formed and annealed nanoparticles in 600 °C and 800 °C temperature, based on their performance in various basic image processing applications (i.e. edge detection filter and noise-canceling filter). A catalytic free glancing angle deposition technique (GLAD) is employed to grow Gd doped HfO2 nanoparticles (NPs) of 8 nm range on the thin film of Silicon oxide SiOx in 30 nm dimension. Annealing process is performed on Gd-doped HfO2 NPs and and the changes were demonstrated in its surface morphology. The elemental composition of the device was analyzed by Energy Dispersive X-ray (EDX). Photoluminescence (PL) analysis revealed that the topography and electrical characteristics of Gd-doped HfO2 alter swiftly after annealing process. A leakage current, interface state density (Dit) factor emphasizes that the device annealed at 600 °C portrayed significant improvement in the non-volatile characteristics in comparison with other devices. Additionally, the endurance of the device annealed at 600 °C was seen to possess more than decades of memory potential. The C-V and hysteresis curve measurement demonstrated maximal charge accumulation relative to other devices. Crossbar array is designed from both as-formed and annealed memristor devices.

Heterointerface properties of diamond MOS structures studied using capacitance–voltage and conductance–frequency measurements

The interface properties of Al2O3/hydrogen-terminated diamond (H-diamond) metal-oxide-semiconductor (MOS) structures both with and without NO2 p-type doping were studied by measuring the capacitance–voltage (C-V) and conductance–frequency (G–f) characteristics to investigate the effect of NO2 p-type doping at the Al2O3/H-diamond interface. The interface state density was studied by measuring the conductance as a function of frequency and applied voltage. Interface state density (Dit) values are for NO2 p-doped MOS structure varied from ~5.7 × 1012 cm−2 eV−1 at 0.27 eV above the valence band maximum (VBM) to 1.75 × 1012 cm−2 eV−1 at 0.36 eV above VBM. Conversely, MOS structure without NO2 p-type doping exhibits a Dit value of approximately 4.2 × 1012 cm−2 eV−1 within an energy range of 0.27 to 0.39 eV. In addition, border trap density in the Al2O3 layer near the interface is also discussed.

Electrical characteristics analyses of zinc-oxide based MIS structure grown by atomic layer deposition

The ZnO films are grown on the p-type Si for metal-insulator-semiconductor (MIS) type Schottky barrier diode (SBHS) fabrication by atomic layer deposition (ALD) method. The electrical characteristics of the three diodes called as D1, D2 and D3 have been investigated. The surface characteristics and thin film in structure were detected by secondary ion mass spectrometry (SIMS) and atomic force microscopy (AFM). The current-voltage (I–V) properties of Al/ZnO/p-Si structures were analyzed in the dark at room temperature. The electrical specifications such as, barrier height (ϕb) ideality factor (n) and series resistance (Rs) of these structures were examined by Norde’s function, Cheung method and thermionic emission (TE) theory. Barrier height values computed from Cheung and I–V method was found to be different from each other. Interface state density (Dit) of these structures was studied using the I–V properties. The non-ideal behavior of measured characteristics advised the presence of interface conditions. The acquired results imply that the fabricated diodes can be used for NIR Schottky photo detector applications.

Study of gamma-ray radiation effects on the passivation properties of atomic layer deposited Al2O3 on silicon using deep-level transient spectroscopy

Aluminum oxide (Al2O3) has emerged as a potential dielectric material and exhibited an excellent passivation property on silicon surface. However, such oxide layer is extremely sensitive to γ-ray irradiation. In this work, deep-level transient spectroscopy has been applied to study the influence of γ-ray irradiation on the passivation properties of atomic layer deposited Al2O3 on silicon. It is shown that γ-ray irradiation leads to a significant increase of interface state density (Dit). Meanwhile, its energy distribution is broadened and shifts deeper with respect to the top of valence band, and therefore evolves into more efficient recombination centers for carriers. Besides, capacitance–voltage (C–V) curves shows a progressive shift toward the negative voltages with increased radiation doses. This indicates the hole trapping in Al2O3, which can neutralize the negatively charged defects and therefore degrade its field-effect passivation. Hence, the passivation quality of Al2O3 on silicon deteriorates significantly after γ-ray radiation.

The current–voltage and capacitance–voltage characterization of the Au/Methylene Blue/n-GaAs organic-modified Schottky diodes

We report the electrical properties of the Au/n–GaAs devices with and without thin organic interface layer. Methylene blue (MB) is a heterocyclic aromatic chemical compound with the molecular formula C16H18N3SCl. The MB layer was formed by spin coating technique on chemically cleaned gallium arsenide (GaAs) substrate. The current–voltage (I–V) and the frequency dependent capacitance–voltage (C–V) characteristics of the Au/MB/n–GaAs metal-insulator-semiconductor (MIS) and Au/n–GaAs metal-semiconductor (MS) devices have been investigated at room temperature. The MS and MIS devices I–V characteristics the showed a good rectification, and they were analyzed based on the thermionic emission (TE) theory. The ideality factor (n) and the barrier height (Φb(IV)) from the I–V characteristics was determined as 1.131±0.006 and 0.782±0.005 eV for MS device and 1.336±0.057 and 0.950±0.008 eV for MIS device, respectively. A Cheung’s method and modified Norde's function has been used to extract the parameters including the (Φb) and the series resistance (RS). Also the values of the barrier height obtained from the C–V measurements (Φb(CV)) of the MS and MIS was 0.863±0.034 eV and 1.187±0.093 eV, at 1 MHz, respectively.Distributions of the interface state density (Dit) of the MS and MIS devices were derivate from I–V and C–V measurements. Our results indicates that the Au/MB/n–GaAs device had lower interface state density values than the Au/GaAs device. Also non-saturated reverse bias current investigated by the using a Pole-Frenkel emission model. Furthermore, the optical and morphological properties of MB layer were investigated by the Atomic Force Microscopy (AFM), Scanning Electron Microscopy (SEM) and UV-vis Spectrophotometer (UV-vis).Finally, we showed that, increasing Φb and decreasing Dit and improving electrical parameters of MIS devices indicates that, thin MB interface layer could prefer for modification of Au/n–GaAs devices.

Field-effect passivation of Si by ALD-Al2O3: Second harmonic generation monitoring and simulation

This paper investigates the ability of second harmonic generation (SHG) to probe the passivation quality of atomic layer deposited Al2O3 on Si by estimating the induced interface electric field due to fixed charges in the oxide. Samples with various oxide charges (Qox) and interface state densities (Dit) were fabricated, using different deposition parameters. The samples were characterized by capacitance-voltage (C-V) and microwave photoconductance decay measurements in order to evaluate Qox and Dit, as well as the effective minority carrier lifetime τeff. The SHG results were consistent with Qox, Dit, and τeff values, proving the ability of the technique to monitor the interfacial quality in a contactless and non-destructive way. Optical simulations which use the electric field values obtained from the C-V measurements could reproduce the measured SHG signal. This demonstrates that SHG coupled with optical simulation can give access to the electric field magnitude and thus characterize the electrical properties of oxide/Si interfaces.

Influence of in-situ NH3 plasma passivation on the electrical characteristics of Ga-face n-GaN MOS capacitor with atomic layer deposited HfO2

The effects of in-situ NH3 plasma passivation on the interface between atomic layer deposited HfO2 and Ga-face n-GaN substrate in metal-oxidesemiconductor (MOS) devices were investigated by varying plasma power and exposure time and compared with GaN MOS device without plasma passivation. ALD HfO2-GaN device with in-situ NH3 plasma treatment shows improved electrical characteristics including negligible frequency dispersion at the near flat-band voltage region, lower hysteresis (∼10 mV), suppressed oxide capacitance dispersion in the accumulation (2.2%), lower leakage current density (5.21 × 10−2 A/cm2 at 1 V), and low interface state density (Dit) of ∼6.77 × 1011 eV−1 cm−2 at Ec-Et = 0.3 eV using an optimized plasma passivation exposure time of 10 min and power of 50 W. These results are attributed that NH3 plasma treatment could eliminate carbon species and detrimental sub-GaOx as well as passivate the surface and bulk defects on GaN caused by Ga-N dissociation.

Investigation of Tm2O3 As a Gate Dielectric for Ge MOS Devices

Germanium (Ge) has been intensively investigated as a high-mobility channel material alternative to silicon (Si). A high quality Ge/dielectric interface with interface state density Dit compared to Si is required for competitive device performance. GeO2 has been identified as potential candidate for an interfacial layer (IL) due to effective Ge surface passivation with Dit in the range of 1011 cm-2eV-1 [1]. However, in order to achieve scaled effective oxide thickness (EOT) a combination of GeO2 IL and a high-k dielectric is needed. Low interface state density in the range of 1011 cm-2eV-1 has been achieved while employing Al2O3 barrier [2] as well as rare earth oxides such as Y2O3 [3]. Rare-earth thulium oxide (Tm2O3) provides high dielectric constant k~16 [4] and sufficient valence (3.05 eV) and conduction (2.05 eV) band offsets [5] for a high-k dielectric layer on Ge. In this work Ge/GeOx/Tm2O3 interface quality and the impact of post deposition anneal ambient are investigated. Metal oxide semiconductor (MOS) capacitors were fabricated to evaluate Ge/GeOx/Tm2O3 gate stacks. After n-Ge substrate clean (acetone, propanol and O2 plasma) and native germanium oxide removal with aqueous HF and HCl solutions the samples were immediately loaded into the rapid thermal anneal (RTA) chamber where oxidation was carried out at 550 °C for 5 s to 5 min. The temperature in the chamber is controlled by a pyrometer which is calibrated to a Si wafer, and oxidation is performed by placing a Ge substrate piece on a Si carrier wafer. The temperature of the Ge sample is thus lower than that of the Si wafer. After oxidation the samples were loaded to atomic layer deposition (ALD) chamber where 40 cycles (~7 nm) of Tm2O3 were deposited using TmCp3 and H2O as precursors. Then Ge/GeO2/Tm2O3 gate stacks were annealed in different ambient (O2, O3, N2 and H2/N2) and temperatures (400 - 550 °C). Reference samples without Tm2O3 deposition or without post deposition anneal (PDA) were also fabricated. Al gate metal was deposited by physical vapor deposition and patterned. MOS capacitors were electrically characterized with capacitance-voltage (CV) measurements. Interface state density in the midgap was evaluated from CV curves using a method described in [6]. X-ray photoelectron spectroscopy (XPS) was performed on some samples using Al Kα X-ray (1486.6 eV) source and PSP Vacuum Technology electron energy analyser. Electrical properties of thermally grown Ge/GeO2 interfaces were evaluated and low interface state density Dit < 5·1011 cm-2eV-1 in the midgap was extracted from CV measurements. The influence of Tm2O3 deposition on high-quality Ge/GeO2 interfaces was then determined. A degradation of the interface quality after the deposition was observed as displayed in Fig. 1. Dit is higher for thinner underlying GeOx layer and seems to saturate to ~9·1011 cm-2eV-1 for thick layers. A series of post deposition anneals in different ambient and temperatures were performed on Ge/GeOx/Tm2O3 gate stacks in order to investigate the influence on the interface state density and capacitance equivalent thickness (CET). The results are shown in Fig. 2. It can be seen that a temperature of 500 °C or higher and O2 ambient is needed to sufficiently reduce Dit, when values as low as 2·1011 cm-2eV-1 can be reached. XPS measurement was performed on Ge/GeOx/Tm2O3 gate stack with O2 PDA at 500 °C and the obtained spectrum is shown in Fig. 3. The difference between the GeOx 3d5/2 peak and Ge0 3d5/2 peak is 2.7 eV which corresponds to Ge3+ oxidation state. This result is consistent with previously reported XPS results on Ge/GeOx/Al2O3 stacks [7] and suggests that Ge3+ oxidation state provides the low Dit values of Ge/GeOx/Tm2O3 gate stacks. Tm2O3 integrated with GeO2 and O2 PDA is a viable candidate for Ge MOS devices due to low interface state density of ~2·1011 cm-2eV-1 which is correlated to Ge3+ oxidation state. A further investigation of O2 PDA time in terms of the trade-off between Dit and CET will be reported.