Interface State Density Distribution Research Articles

Observation of Space Charge Limited Current in Schottky Diodes with V2O5 Interfacial Layer Prepared by Radio Frequency Magnetron Sputtering

Electrical properties of V2O5/n-Si Schottky barrier diodes prepared by rf magnetron sputtering of vanadium pentoxide (V2O5) on n-Si wafer have been investigated. The current-voltage (I–V) and capacitance-voltage (C-V) measurements of the diode have been performed in the dark at the room temperature. The saturation current (I0), ideality factor (n), barrier height (ΦB) values of the diode have been determined as 6.68x10-8 A, 1.35, and 0.755 eV, respectively. The series resistance (RS) values from Norde, Cheung and Nicollian & Brews methods have been determined as 199 Ω, 251 Ω, and 144 Ω, respectively. The energy distribution of interface state density (NSS) was determined, and the values of against the energy values of NSS in the vary between EC-0.462 eV and EC-0.713 eV were obtained 4.343x1016 eV-1 cm-2 and 3.282x1015 eV-1 cm-2, respectively. The barrier height and metal oxide thickness (ẟ) values using capacitance-voltage (C-V) measurements in the frequency of 1 MHz has also been calculated as 0.949 eV and 37.4 nm, respectively. The prepared diode showed abnormal diode characteristics, indicating the existence of a space-charge limited (SCL) current. From forward bias I-V characteristics, the ohmic, trapped filled space charge limited current (TFSCLC) and SCLC conduction behaviors were observed at low, middle, and high voltages, respectively. Experimental results indicated that the prepared V2O5 film on n-Si can be utilized in electronic applications.

Interface state density distribution near conduction band edge at Al2O3/Mg-ion-implanted GaN interface formed after activation annealing using AlN cap layer

An interface state density (Dit) distribution near the conduction band edge (EC) at the Al2O3/Mg-ion-implanted GaN interface was measured after ion implantation, annealing with an AlN protective cap, and cap layer removal. Mg ions were implanted into n-GaN with a Si concentration of 6 × 1017 cm−3 at a maximum Mg concentration of 2 × 1017 cm−3, resulting in the maintenance of the n-type conduction in GaN even after the activation of Mg dopants. Activation annealing was carried out at 1250 °C for 1 min using an AlN cap layer. The complete removal of the AlN cap layer was accomplished by wet etching, which was confirmed by x-ray photoelectron spectroscopy. The photoluminescence spectrum showed donor–acceptor-pair emission after annealing, indicating the activation of Mg acceptors. By applying the capacitance–voltage method to a completed metal–oxide–semiconductor diode, we derived a continuous distribution of relatively low Dit below 5 × 1012 cm−2 eV−1, which increased monotonically toward EC in the range from EC − 0.15 to EC − 0.45 eV. Compared with the Dit distribution of the as-implanted sample, the density of the discrete level at EC − 0.25 eV generated by divacancies markedly decreased upon 1250 °C annealing.

Density Functional Theory Calculations of Pinus brutia Derivatives and Its Response to Light in a Au/n-Si Device

In this study, the performance of an organic dye obtained from the bark of the red pine (Pinus brutia) tree growing in Muğla/Turkey as an interface layer in the Au/n-Si Schottky diode (SD) structure was evaluated. For this purpose, at first, the optimized molecular structure, the highest occupied molecular orbital (HOMO), and the lowest unoccupied molecular orbital (LUMO) simulations of the organic dye were calculated by the Gauss program and it was theoretically proven that the dye exhibits semiconducting properties. Then, the electrical and photodiode variables such as ideality factor, effective barrier height, series resistance, interface states density distribution, photosensitivity, and photo responsivity were evaluated employing current-voltage measurements under dark and different illumination densities. Additionally, C-V measurements were used to demonstrate that the fabricated device has capacitive features and this capability varies as a function of the frequency. Under these measurements, the possible conduction mechanism for the organic dye-based Au/n-Si device was investigated and the results showed that Au/Pinus brutia/n-Si may be a good candidate for optoelectronic applications.

Detailed Insight into the CZTS/CdS Interface Modification by Air Annealing in Monograin Layer Solar Cells

Relatively fast achievements in the kesterite solar cell technology have been made over the last decade, but the experimental efficiency is still ∼13%. One proposed reason is an inappropriate band alignment with Cu2ZnSnS4 (CZTS) and CdS that results in strong interface recombination losses. Results of this work show that the temperature and duration of air annealing of the CZTS/CdS heterojunction are essential for device performance. Soft annealing slightly improved the device efficiency due to the elemental intermixing at the interface. On the other hand, extended annealing increased absorber band gap energy, resulting in higher VOC values, indicating the improved Cu–Zn ordering in the CZTS structure, which also could be expected to have a beneficial influence on the device performance. However, interface analysis revealed that the CZTS absorber surface layer was Cu-rich, providing the reason for the reduction in CZTS solar cell performance. The effect of annealing on the interface defects was analyzed by the capacitance–frequency–voltage (C–V–f) analysis combined with SCAPS simulations. C–V–f-based loss maps showed that air annealing modifies the density distribution of asymmetrical interface states at the CZTS/CdS interface, which becomes fully symmetrical for longer annealing times at 200 °C.

Comparative study of C–V-based extraction methods of interface state density for a low-temperature polysilicon thin film

To extract comprehensive and accurate interface state density (D it) distribution for a low-temperature polysilicon (LTPS) thin film, three well-established methods based on capacitance–voltage (C–V) measurements were compared: high–low frequency capacitance, conductance, and quasi-static (QS) capacitance methods. Because of the strong frequency-dependent response of grain boundary traps within the LTPS, C–V measurements are necessary on p- as well as n-type LTPS films, as they provide D it distribution across the entire LTPS band gap. The QS capacitance method, which uses an optimal high-frequency C–V curve with a minimal grain boundary trap response, provided the best and most comprehensive estimate of D it distribution across the LTPS band gap, even at room temperature (25 °C). Although the narrow extraction ranges of D it were extended toward the mid-gap region by increasing the measurement temperature in both high–low frequency capacitance and conductance methods, the responses of the grain boundary traps still overestimated the D it values near the band edges.

Ultrashallow defects in SiC MOS capacitors

Capacitance-voltage measurements performed at cryogenic temperatures (14 – 500 K) have been used to determine the ultrashallow interface states in SiC MOS capacitors. These states occupies energy levels in SiC band gap on different energy levels up to 27 meV below the conduction band. Moreover, the capacitance-voltage characteristics are moving to lower voltages with temperature increasing, indicating a reduction in flat band voltage from 14.65 (14 K) to 2.77 V (500 K). It was demonstrated that a complete ionization of the nitrogen donors from the epitaxial layer occurs at 420 K. From these analysis, an activation energy of around 26.79 meV was determined. In order to determine the energy levels distribution of the interface states in SiC band gap, the Fermi level variation with temperature was calculated, starting from a value of around 27.1 meV at 14 K and reaching a value of 321 meV at 500 K under SiC conduction band. Six peaks (D1 – D6) have been identified in interface states density distribution at different levels of energy in SiC band gap, which could correspond to different defects at the SiO2/SiC interface.

(G03 Best Paper Award Winner) Si-Passivated Ge Gate Sacks with Low Interface State and Oxide Trap Densities Using Thulium Silicate

Germanium is considered as a high mobility channel material for its potential to be introduced in future CMOS technology nodes. Ge surface passivation with a thin silicon layer (Si-cap) has been shown to be efficient for pFETs because of a sufficient valence band offset between Ge and Si-cap, which confines the holes in the Ge layer. Strained Ge pFinFETs outperforming Si pFinFETs due to four times higher mobility have been demonstrated using Si-cap process [1]. Interfacial defects can be further passivated with a high-pressure anneal in H2 resulting in reduced sub-threshold swing and increased mobility in Ge nanowires [2]. Moreover, by using a Si-cap, Negative-bias temperature instability reliability is improved compared to GeOx passivation because of the energy decoupling between holes and defects in SiO2/HfO2 gate stack [3]. However, a Si-cap process poses gate stack scalability issues because in order to achieve sufficient surface passivation, the Si-cap thickness cannot be scaled. An introduction of a high-k interfacial layer instead of a chemical oxide SiO2 could potentially help to scale down equivalent oxide thickness. Integrating thulium silicate (TmSiO) as a replacement of the SiO2 interfacial layer has been demonstrated on silicon, and a hole and electron mobility enhancement compared to SiO2/HfO2 gate stacks has been achieved for an equivalent oxide thickness (EOT) < 1 nm [4]. Moreover, we have previously displayed the compatibility of Tm2O3 with Ge by demonstrating GeOx/Tm2O3 gate stacks with interface state density Dit < 5·1011 eV-1cm-2 [5]. In this work, we integrate TmSiO with a Si-cap process to achieve Dit comparable to GeO2 passivation.In order to evaluate Ge/Si/TmSiO interfaces, MOS capacitors (MOSCAPs) were fabricated on n-type Ge strain relaxed buffers epitaxially grown on n-type Si wafers in a two-step process using GeH4 precursor [6]. Si-caps of different thicknesses were grown at 400 °C using Si2H6. Si growth was confirmed by ellipsometry spectroscopy and testing that the surface is hydrophobic. While trying to keep the Si-cap exposure to air to a minimum, 400 nm PECVD SiO2 was deposited and active areas were defined. After removing the remaining SiO2 from the active areas with 1 % HF, Tm2O3 was deposited by atomic layer deposition (ALD) at 225 °C. Rapid thermal anneal at 550 °C for 60 s in N2 was then employed to form TmSiO layer. High-k HfO2 was deposited by ALD at 350 °C followed by a post deposition anneal in O3 for 10 min. TiN gate metal was deposited at 425 °C by ALD and 500 nm Al was deposited by sputtering for probing purposes. After patterning, the samples were subjected to a forming gas anneal of 10% H2 in N2 at 400 °C for 30 min. Reference MOSCAPs with Ge/GeOx/Tm2O3/HfO2 gate stacks were also fabricated as described in [5] with addition of ALD HfO2.Interface state density in the midgap of Ge/Si/TmSiO/Tm2O3/HfO2 gate stacks was evaluated by CV measurements where measured CV characteristics where compared to calculated ones assuming a parabolic Dit distribution. Dit highly depends on Si-cap thickness, as displayed in Fig. 1. An optimal Si-cap thickness corresponding to 40-50 min deposition time provides Dit at midgap ~5·1011 cm-2eV-1 at CET of 4 nm. Reference MOSCAPs with Ge/GeOx/Tm2O3/HfO2 gates exhibit similar Dit of 4-5·1011 cm-2eV-1. Interface state density distribution within the band gap of Ge/Si/TmSiO interface with 40 min Si-cap deposition time was evaluated using the conductance method at different temperatures and is displayed in Fig. 2. Dit in the midgap is in agreement with the results obtained from CV measurements, and increases towards the valence and conduction band edges. The oxide trapped charge Qox of 2.5·1010 cm-2 (40 times lower than in the Ge reference devices without Si-cap) was determined from CV measurements and corresponds to only 5 mV hysteresis showing the potential of superior reliability.A Si-cap process with high-k TmSiO interface has been demonstrated on Ge MOS devices. A low Dit comparable to GeOx passivation has been shown. In addition, devices with TmSiO potentially have a superior reliability vs GeOx devices due to low oxide trapped charge density.

Temperature dependence of interface state density distribution determined from conductance–frequency measurements in Ni/n-GaP/Al diode

The conductance measurements of the non-annealed (D1) and 400 °C annealed (D2) Ni/n-GaP/Al diodes were made over a wide frequency range of (10 kHz to 5 MHz) and temperature of (100–320 K with steps of 20 K) with bias voltage as a parameter. The capacitance and conductance measurement method is one of the most popular non-destructive methods to obtain information about metal–semiconductor (MS) diode interfaces. The interface state density distribution curves were determined over the band-gap energy near the semiconductor energy midgap. The interface state density (Dit) has been seen to be of the order of ∼1012 eV−1 cm−2. The Dit∼T curves have been plotted for different values of bias voltage. The value of Dit increased with increasing measurement temperature, and with increasing voltage from negative bias to positive bias voltage for both diodes. It was seen that the Dit value for D2 diode was greater than that for the D1 diode at each measurement temperature and bias voltage. It was seen in the interface state energy distribution or density distribution curves that the value of Dit has increased from the valence band maximum (Ev) towards conduction band minimum (Ec) at each measurement temperature.

Insight into Al2O3/B-doped diamond interface states with high-temperature conductance method

We employed a high temperature conductance method to investigate the interface state properties of the Al2O3/B-doped diamond MOS structure by considering the surface potential fluctuation. Based on Gaussian approximation of Nicollian's model and Brew's graphical approach, we analyzed the frequency dependent characteristics of parallel conductance (Gp/ω–f) at various gate voltages and extracted the energy distribution of interface state density (Dit), capture cross section (σp), time constant (τit), and the standard deviation of surface potential fluctuation (σs). The Dit extracted by the conductance method exhibited good agreement with that by the high-low method, whereas there exist large errors when surface potential fluctuation was not considered by using the conductance method. The capture cross section extracted by the conductance method was on the order of 10−17 cm2. From the energy dependence of the interface state time constant, the hole capture and emission follow the Shockley–Read–Hall statistics. σs decreases with the energy position away from the valence band edge (Ev) of diamond, indicating that donor-like traps are distributed in the Ev side of diamond.

Negative resistance, capacitance in Mn/SiO2/p-Si MOS structure

In this work is that we have manufactured a new structure that had not been studied by researchers before. This structure is Mn/SiO2/Si was synthesised by liquid phase epitaxy (LPE) as a metal-oxide- semiconductor (MOS) and can be used as a tunneling diode; demonstrated from I–V measurement and negative resistance. The structure and its characterization were examined by scanning electron microscope, XRD diffraction, C-V and I–V measurements. We studied the temperature, voltage dependence of dielectric and electrical parameters of the fabricated Mn/SiO2/P-Si MOS device. I–V measurements for this structure display diode tunnel behavior with negative resistance. Parameters such as series resistance (Rs), permittivity (ε′), dielectric loss (ε″), a tangent of the dielectric loss factor (tan δ), real and imaginary parts of electrical modulus (M′ and M″) and ac conductivity were examined in a temperature range of 303–393 K and frequency range (10 Hz–20 MHz) under 1 Vrms applied voltage along with dc bias range of (−2.0–2.0 V). We found that thermal reordering of the interface is a reason for a continuous density distribution of interface states with homogenous relaxation time, which in turn induced a higher sensitivity to both C and G/w response with electric field frequency. The device showed negative values for capacitance (C), dielectric loss (ε″), and dielectric loss tangent (tan δ) at all temperatures.

Electrical Characterization of Si/ZnO Nanorod PN Heterojunction Diode

The electrical characterization of p-Silicon (Si) and n-Zinc oxide (ZnO) nanorod heterojunction diode has been performed. ZnO nanorods were grown on p-Silicon substrate by the aqueous chemical growth (ACG) method. The SEM image revealed high density, vertically aligned hexagonal ZnO nanorods with an average height of about 1.2 μm. Electrical characterization of n-ZnO nanorods/p-Si heterojunction diode was done by current-voltage (I-V), capacitance-voltage (C-V), and conductance-voltage (G-V) measurements at room temperature. The heterojunction exhibited good electrical characteristics with diode-like rectifying behaviour with an ideality factor of 2.7, rectification factor of 52, and barrier height of 0.7 V. Energy band (EB) structure has been studied to investigate the factors responsible for small rectification factor. In order to investigate nonidealities, series resistance and distribution of interface state density (NSS) below the conduction band (CB) were extracted with the help of I-V and C-V and G-V measurements. The series resistances were found to be 0.70, 0.73, and 0.75 KΩ, and density distribution interface states from 8.38 × 1012 to 5.83 × 1011 eV−1 cm−2 were obtained from 0.01 eV to 0.55 eV below the conduction band.

Investigation of the electrical properties of diodes by crosschecking dependence on the presence of (nanocarbon-PVP) interface layer

The Al/p-Si (metal-semiconductor (MS)) and Al/nanocarbon-PVP/p-Si (metal-polymer-semiconductor) type Schottky barrier diodes (SBDs) were fabricated in same conditions to determine the existence of an increase in the performance of Al/p-Si diode and they were called as D1 and D2, respectively. For this purpose, the electrical properties of the diodes were investigated using the current–voltage and impedance–voltage measurements in wide bias voltage. The ideality factor, reverse-saturation current and zero-bias barrier height values were calculated from the linear part of the forward bias lnI–V plot as 6.23, 2.35 ✕ 10–8A, 0.68 eV for D1 and 2.86, 4.27 ✕ 10–9A, 0.73 eV for D2, respectively. It is seen from results that the value of rectifier rate for D2 is about 8 times higher than for D1. The values of barrier height, Fermi energy level, the number of doped acceptor atoms and depletion layer width were obtained. The values of series resistance and special density distribution of interface states’ values also considerably decrease using (nanocarbon Polyvinylpyrrolidone (PVP)) interlayer. All these results confirmed that the nanocarbon-PVP polymer interlayer leads to a seriously increase in the performance of the MS diodes and hence it can be successfully used as an insulator in view of low cost, grown by simple methods.

Effect of measurement frequency on admittance characteristics in Al/p-Si structures with interfacial native oxide layer

Al/p-Si/Al diodes with interfacial native oxide layer were formed. Their frequency induced admittance-voltage measurements were made. The frequency-dependent density distribution of interface states has been determined from the corrected characteristics by considering the series resistance effect which masks the interface trap loss. The majority carrier density corresponding to the depletion and inversion parts of the C-2-V curve, was determined 1.82 x 1014 and 4.48 x 1014 cm-3 at 1000 kHz, respectively. The fact that the carrier density obtained from the inversion part of the plot is higher than that obtained from the depletion part can be related to the increase in the density of negative space charge in the depletion region.The value of was determined as 0.95 eV from the same plot. Interface state density decreased from 4.31 x 1012 eV-1cm-2 at 100 kHz to 7.30 x 1011 eV-1 cm-2 at 1000 kHz, because the interface charges do not follow the ac signal and do not contribute to capacitance values in high frequencies.

Fabrication of a New Hybrid Coronene/n-Si Structure by Using Spin Coating Technique and its Photoresponse and Admittance Spectroscopy Studies

Coronene/n-Si Schottky structure has been fabricated by Coronene thin film deposited on n-Si substrate using the spin coating technique. The current-voltage (I-V) characteristics of the diode have been evaluated under various illumination intensities to determine photodiode behavior. Photovoltaic parameters of the fabricated diode have been calculated at different illumination intensities. The Coronene/n-Si diode presents a photovoltaic status with a maximum short-circuit current (Isc) of 13.1 μA and open circuit voltage (Voc) of 0.16 V under 100 mW/cm2 illumination intensity. The recombination process of the Coronene/n-Si diode shows the existence of bimolecular recombination mechanism associated with the trap levels in the band gap. Also, the series resistance and interface state density distribution of the photodiode have been estimated by capacitance-voltage (C-V) and conductance-voltage (G-V) characteristics at various frequencies. The experimental results indicated that the Al/Coronene/n-Si diode can be used as a photodiode in optoelectronic and photovoltaic applications.

Thermally annealed gamma irradiated Ni/4H-SiC Schottky barrier diode characteristics

Thermal annealing effects on gamma irradiated Ni/4H-SiC Schottky barrier diode (SBD) characteristics are analyzed over a wide range of temperatures (400–1100 °C). The annealing induced variations in the concentration of deep level traps in the SBDs are identified by thermally stimulated capacitance (TSCAP). A little decrease in the trap density at EC – 0.63 eV and EC – 1.13 eV is observed up to the annealing temperature of 600 °C. Whereas, a gamma induced trap at EC – 0.89 eV disappeared after annealing at 500 °C, revealing that its concentration (< 1013 cm−3) is reduced below the detection limit of the TSCAP technique. The electrical characteristics of irradiated SBDs are considerably changed at each annealing temperature. To understand the anomalous variations in the post-annealing characteristics, the interface state density distribution in the annealed SBDs is extracted. The electrical properties are improved at 400 °C due to the reduction in the interface trap density. However, from 500 °C, the electrical parameters are found to degrade with the annealing temperature because of the increase in the interface trap density. From the results, it is noted that the rectifying nature of the SBDs vanishes at or above 800 °C.

High-quality SiNx/p-GaN metal-insulator-semiconductor interface with low-density trap states

We report on a high-quality p-GaN metal-insulator-semiconductor (MIS) capacitors with sharp interface morphology and the lowest interface trap density by using SiNx as the gate dielectric layer. Transmission electron microscopy and x-ray photoelectron spectroscopy (XPS) analysis revealed a high-quality interface morphology with the effective removal of carbon and oxygen impurities. Better than the interface properties of Al2O3, SiO2, and CaF2/p-GaN metal-oxide-semiconductor (MOS) or MIS capacitors, the capacitance-voltage measurements of SiNx/p-GaN showed negligible electrical hysteresis after a two-step surface pre-treatment, leading to the lowest trapped charge density of 5 × 1010 cm−2. The interface state density distribution was also reduced to be ~1–2 × 1012 cm−2 · eV−1 at Et–Ev = 0.2–0.45 eV and 3–5 × 1012 cm−2 · eV−1 near the valance-band edge after the treatments. The achievement of the high-quality MIS interface was attributed to the suppression of the Mg-Ga-O interfacial disordered layer by the effective surface treatments and oxygen-free deposition process, which was usually observed at Al2O3/p-GaN MOS interface.

Improvement of Local Deep Level Transient Spectroscopy for Microscopic Evaluation of SiO&lt;sub&gt;2&lt;/sub&gt;/4H-SiC Interfaces

We demonstrate our new local deep level spectroscopy system improved for more accurate analysis of trap states at SiO2/4H-SiC interfaces. Full waveforms of the local capacitance transient with the amplitude of attofarads and the time scale of microseconds were obtained and quantitatively analyzed. The local energy distribution of interface state density in the energy range of EC − Eit = 0.31–0.38 eV was obtained. Two-dimensional mapping of the interface states showed inhomogeneous contrasts with the lateral spatial scale of several hundreds of nanometers, suggesting that the physical origin of the trap states at SiO2/SiC interfaces is likely to be microscopically clustered.

The Effect of Thermal Annealing and Measurement Temperature on Interface State Density Distribution and Time Constant in Ni/n-GaP Rectifying Contacts

The capacitance–frequency (C–f) and conductance–frequency (G–f) characteristics of the as-deposited and 400°C annealed Ni/n-GaP/Al diode were measured in a temperature range of 100–320 K with steps of 20 K. The values of interface state density Nss and their time constant were obtained from the temperature-dependent C–f and G–f characteristics in the measurement frequency range of 5.0 kHz to 5 MHz. The effect of annealing and measurement temperature on Nss and time constant of a Ni/n-GaP Schottky diode were analyzed from the forward bias voltage to the reverse bias voltage − 0.60 with steps of 0.30 V. The Nss value ranges from 8.8 × 1011 cm−2eV−1 at 0.60 V to 5.71 × 1011 cm−2eV−1 at − 0.60 V for the as-deposited diode, and 1.3 × 1012 cm−2eV−1 at 0.60 V to 5.5 × 1011 cm−2eV−1 at − 0.60 V for the 400°C annealed diode at a measurement temperature of 300 K. The interface state density value increases with high measurement temperature for the as-deposited and annealed diode.

Electrical characterization of two analogous Schottky contacts produced from N-substituted 1,8-naphthalimide.

The aim of this study was to analyze the interface states (Nss) in pure Al//p-Si/Al, Al/N-F Nft/p-Si/Al and Al/N-T Nft/p-Si/Al Schottky barrier diodes (SBDs). N-Substituted 1,8-naphthalimide thin films were deposited on a p-Si substrate by spin coating and annealed at ∼200 °C for 60 s under an air atmosphere. Al contacts were obtained via reactive magnetron sputtering. The current voltage (I-V) characteristics of the SBDs were measured at room temperature. From the I-V characteristics, the SBDs ideality factor (n) and zero-bias barrier height values (Φb) of 1.27, 1.00, and 1.05 and 0.66 eV, 0.70 eV, and 0.64 eV were observed for the Al//p-Si/Al, Al/N-F Nft/p-Si/Al and Al/N-T Nft/p-Si/Al Schottky barrier diodes, respectively. The interface state density distribution profile (Nss) as a function of (Ess-Ev) was extracted from the forward-bias I-V measurements by considering the effective barrier height and (Φe) and series resistance (Rs) of the Schottky diode. The obtained Nss plot tendency showed that the existence of interface states has no significant effect on the rectifying and capacitance characteristics. The Nss values with the 1,8-naphthalimide layer were lower than that without it. This shows that naphthalimide exhibits a strong contribution by blocking the unwanted states and some traps in the conduction mechanism, which may cause possible cracks or deep paths for carriers to travel along the junction.

Analysis of photoconductive mechanisms of organic-on-inorganic photodiodes

In this work, it is shown that choosing an organic-on-inorganic Schottky diode for photoconductive sensing by a using a power law exponent (PLE or γ) determined at a single bias point is a limited approach. The standard literature approach does not highlight any bias voltage effects on the distribution of interface state density and other operationally important parameters. In this paper we suggest a new empirical method that holistically highlights the variation of γ with voltage, irradiance and temperature to reach a more informed choice of photosensor for real applications. We obtain a simple, plausible relation of the variation of barrier height, Φ, with voltage, irradiance and temperature. The method is evaluated with data collected previously for Schottky diodes of structure Al/p-Si/organic-semiconductor (OSC)/Au, where OSC is Coumarin-doped with graphene oxide (GO), Cobalt Phthacyanine (CoPC) doped with GO or PCBM doped with GO, respectively. The method reproduces published data for the three diodes reported at specific bias and provides for the first time some qualitative evidence of barrier height variation with light intensity, for which a possible physical basis is also given. Typically, Schottky barrier height is characterized using dark current leading to an under reporting of the effect of illumination on barrier height. Finally, since recombination mechanisms are gauged on the basis of the magnitude of PLE, the method facilitates the identification of the recombination mechanism at a given bias.