Interface Protocol Research Articles

WP6.6 - Sentiment Analysis of Social Media Posts by Medical Professional in the UK

Abstract Aims Notoriously described as being controversial in nature, we aim to objectively assess the language used amongst medical professionals in social media (SM). Methods Data was extracted from the Reddit SM website under the sub-page "r/DoctorsUK" forum, through a data-extraction code written in the python language. This was then analysed through a Natural Language Toolkit algorithm to classify language used into positive, negative and neutral sentiments with an overall polarity score ranging from -1 noting most negative to 1 being most positive. Results A total of 992 articles were examined over a 24-day period, as limited by Reddit data application programme interface (API) protocols. A total of 210 positive, 218 negative and 564 neutral articles were noted with an average of 43 articles posted per day. Headlines sentiment on average was overall marginally positive at 0.0154. Comment tree within each headline was also examined, noting a more positive 0.173. Through regression analysis, it was noted that headline and comment sentiments was directly correlated, and this was statistically significant(P=1.24*10-10). It was also noted that more negative headlines had higher “likes” and were therefore featured more prominently within the forum. Conclusions Although SM posts are overall positive in sentiment, it is noted that more negative sentiments are often up-voted and therefore featured more prominently due to their more provocative nature and emotions incited amongst readers. As SM posts elicits strong psychological and psychosocial reactions from a community, there is an urgency to more accurate data driven models in developing future policies to maintain an effective professional morale within the NHS.

Automatic Parallel Tempering Markov Chain Monte Carlo with Nii-C

Due to the high dimensionality or multimodality that is common in modern astronomy, sampling Bayesian posteriors can be challenging. Several publicly available codes based on different sampling algorithms can solve these complex models, but the execution of the code is not always efficient or fast enough. The article introduces a C language general-purpose code, Nii-C, that implements a framework of automatic parallel tempering Markov Chain Monte Carlo. Automatic in this context means that the parameters that ensure an efficient parallel tempering process can be set by a control system during the inital stages of a sampling process. The autotuned parameters consist of two parts, the temperature ladders of all parallel tempering Markov Chains and the proposal distributions for all model parameters across all parallel tempering chains. In order to reduce dependencies in the compilation process and increase the code’s execution speed, Nii-C code is constructed entirely in the C language and parallelized using the message-passing interface protocol to optimize the efficiency of parallel sampling. These implementations facilitate rapid convergence in the sampling of high-dimensional and multimodal distributions, as well as the expeditious code execution time. The Nii-C code can be used in various research areas to trace complex distributions due to its high sampling efficiency and quick execution speed. This article presents a few applications of the Nii-C code.

Direct Memory Access-Based Data Storage for Long-Term Acquisition Using Wearables in an Energy-Efficient Manner.

This study introduces a lightweight storage system for wearable devices, aiming to optimize energy efficiency in long-term and continuous monitoring applications. Utilizing Direct Memory Access and the Serial Peripheral Interface protocol, the system ensures efficient data transfer, significantly reduces energy consumption, and enhances the device autonomy. Data organization into Time Block Data (TBD) units, rather than files, significantly diminishes control overhead, facilitating the streamlined management of periodic data recordings in wearable devices. A comparative analysis revealed marked improvements in energy efficiency and write speed over existing file systems, validating the proposed system as an effective solution for boosting wearable device performance in health monitoring and various long-term data acquisition scenarios.

Design of an RFID-Based Self-Jamming Identification and Sensing Platform

Commodity RFID tags backscatter stored electronic product code (EPC) to the reader, but do not have sensing capability. Existing works have made much effort on designing RFID-based sensing platform. But most of them either need intricate hardware design or rely on modification of the tag, which increases the cost or constrains the sensing capability. In this paper, we design a self-jamming identification and sensing platform (SJISP) consisting of SJISP nodes and a commodity RFID reader. A subtle design of the SJISP node is the adoption of a jammer radio module with the same frequency as the reader, controlled by the micro control unit (MCU) to decide whether to interfere with the query process of the RFID reader. The RFID tag is not readable if the jammer is turned on to generate interference signals. Otherwise, it is readable when the jammer is turned off. The sensing data is thus modulated by switching the jammer on and off for transmitting bit 0 and bit 1, respectively. The reader demodulates the data through the compatible EPC UHF Gen2 air interface protocol. To further save the energy of the SJISP node, we propose a prefix codebook based data delivery scheme, which leverages the difference of energy consumption (DEC) between transmitting bit 0 and bit 1. Our proposed scheme can save more than 50 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> of the energy than common communication without codebook. Experimental results based on our prototyped system show that the designed SJISP can achieve an average packet reception rate (PRR) of over 99 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"><tex-math notation="LaTeX">$\%$</tex-math></inline-formula> and is quite robust to environmental disturbance. Our designed platform provides a low-cost and compatible solution to extend the sensing capability of RFID system. A demo application with a temperature sensor and a light sensor embedded in two SJISP nodes respectively are developed to demonstrate how SJISP applies in real world scenario.

Data Communication Algorithm of HPDB Parallel Database System Based on Computer Network

High-Performance Database (HPDB) is designed to meet the demands of today’s modern data-driven world, as massive volumes of information need to be accessed and analyzed with minimal latency. A pivotal aspect of their operation lies in efficient data communication among nodes in a computer network, which is essential for parallel database systems. HPDBs may involve distributed architectures and parallel database systems to store and process data across multiple nodes or servers in a network. Hence, an algorithm called Hybridized Partitioning Strategy (HPS)-based Communication (C) for achieving HPDB has been proposed to facilitate data transmission and coordination across a computer network using the Message Passing Interface (MPI) protocol. The proposed HPS-C-HPDB technique includes partitioning and distributing data, query routing, and load balancing strategies to achieve high-performance levels. The (HPS) combines hash and range partitioning methods for effective processing and retrieval to balance data distribution, reduce communication overhead in parallel databases, and improve the system’s performance. In parallel database systems, query routing effectively routes requests into the optimal nodes or partitions based on the query’s conditions and the data’s placement and guarantees efficient data processing and retrieval. The proposed scheme is evaluated using various performance metrics like throughput, response time, speedup, and communication overhead analysis.

Probing an Easy-to-Deploy Multi-Agent Manufacturing System Based on Agent Computing Node: Architecture, Implementation, and Case Study

Abstract Due to the widespread adoption of personalized customization services, the application contexts within discrete manufacturing workshops have become increasingly intricate, necessitating the modern industry to evolve toward a more adaptable production trajectory. The pre-established production rules in a traditional centralized control manufacturing system present difficulties in accommodating dynamic situations. Although a multi-agent manufacturing system (MAMS) yields natural advantages in handling dynamic emergencies, the current research is limited to the computer simulation level and lacks integration with the underlying physical devices. In order to mitigate said challenges, the standardization modeling approach for the agent computing node (ACN) to facilitate the implementation of a readily deployable MAMS was proposed in the present study. Initially, adapters encompassing communication, decision, and control modules were developed within the industrial personnel computer-based computing node to accommodate the heterogeneous interface protocols of diverse machines. These adapters enable communication and interaction among machines while laying the computational foundation for the ACN. Accordingly, the models of the machine agent, the part agent, and the monitoring agent were constructed based on ACNs and could perceive the dynamic production information and support the enabling application. Subsequently, to guide ACNs in making scheduling decisions beneficial to global performance, an improved negotiation mechanism in MAMS was achieved in real-time. Finally, the proposed MAMS based on the ACN was deployed in an actual flexible machining workshop. Comparative experiments were implemented and, as exhibited from the experimental results, the proposed ACNs possessed the capabilities of achieving optimal global decision-making and facilitating straightforward deployment.

FPGA Implementation of SPI Protocol

Field Programmable Gate Array (FPGA) are versatile devices that can be programmed to implement various digital circuits, including communication protocols like Serial Peripheral Interface (SPI). The Serial peripheral interface protocol is a synchronous serial communication interface that allows for full duplex communication between a master device and a multiple slave MOSI, MISO, SCLK, and SS. MOSI and MISO are data lines, while SCLK is the clock signal generated by the master to synchronize transfers. SS is used by the master to select individual slave devices. By implementing the SPI protocol in FPGA, to gain flexibility and customization, as FPGAs can be reprogrammed for different applications without the need for dedicated hardware changes. The FPGA implementation of the Serial Peripheral Interface (SPI) protocol involves a structured methodology. With the help of pipeline buffer and DAM technique power dissipation is performed effectively. Finally, integrate the FPGA SPI module into the larger system, ensuring seamless communication with other components or microcontrollers. This systematic approach ensures a reliable and tailored FPGA based SPI implementation.

Computer Vision-Assisted Object Detection and Handling Framework for Robotic Arm Design Using YOLOV5

In recent years, there has been a surge in scientific research using computer vision and robots for precision agriculture. Productivity has increased significantly, and the need for human labor in agriculture has been dramatically reduced owing to technological and mechanical advancements. However, most current apple identification algorithms cannot distinguish between green and red apples on a diverse agricultural field, obscured by tree branches and other apples. A novel and practical target detection approach for robots, using the YOLOV5 framework is presented, in line with the need to recognize apples automatically. Robotic end effectors have been integrated into a Raspberry Pi 4B computer, where the YOLOV5 model has been trained, tested, and deployed. The image was taken with an 8-megapixel camera that uses the camera serial interface (CSI) protocol. To speed up the model creation process, researchers use a graphical processing computer to label and preprocess test images before utilizing them. Using YOLOV5, a computer vision system-assisted framework aids in the design of robotic arms capable of detecting and manipulating objects. The deployed model has performed very well on both red and green apples, with ROC values of 0.98 and 0.9488, respectively. The developed model has achieved a high F1 score with 91.43 for green apples and 89.95 for red apples. The experimental findings showed that robotics are at the forefront of technological advancement because of the rising need for productivity, eliminating monotonous work, and protecting the operator and the environment. The same discerning can be applied to agricultural robots, which have the potential to improve productivity, safety, and profit margins for farmers while reducing their impact on the environment. The system’s potential could be seen in an assortment of fields, including sophisticated object detection, nuanced manipulation, multi-robot collaboration, and field deployment.

SPI Master Slave Communication

The serial-peripheral interface (SPI) protocol also called asynchronous serial interface specification is used for communication between single master and single/multiple slaves. With the increase in number of slaves causing high complexity of circuit creates a demand in self-test ability feature for SPI module in order to test for fault free circuits. Built-In-Self-Test (BIST) in the answer for self-test in circuits as well as it helps in reduction of maintenance and testing cost. Design of BIST embedded SPI module with single master and single slave configuration has been introduced in these paper, Here 8-bit is transferred across the module, Where the Circuit under Test (CUT) is being Self-Tested with BIST feature for its correctness. This SPI module is designed using Verilog hardware description language(HDL) using EDA playground platform for application like applications specific integrated circuit (ASIC) or system on chip (SOC). SPI stands for the Serial Peripheral Interface. It is a serial communication protocol that is used to connect low-speed devices. It was developed by Motorola in the mid-1980 for inter-chip communication. It is commonly used for communication with flash memory, sensors, real-time clock (RTC), analog-to-digital converters, and more. It is a full-duplex synchronous serial communication, which means that data can be simultaneously transmitted from both directions. The main advantage of the SPI is to transfer the data without any interruption. Many bits can be sent or received at a time in this protocol. In this protocol, devices are communicated in the master-slave relationship. The master device controls the slave device, and the slave device takes the instruction from the master device. The simplest configuration of the Serial Peripheral Interface (SPI) is a combination of a single slave and a single master. But, one master device can control multiple slave devices

Heterogeneous Integration of Chiplets, Lego-like IP for More than Moore

The semiconductor industry is facing an inflection point as higher cost, lower yield, and reticle size limitations drive the need for viable alternatives to traditional monolithic solutions, which are hitting or coming close to the limits of manufacturing and physics. This is driving an emerging trend to disaggregate what typically would be implemented as an SoC into solid, fabricated IP blocks, otherwise known as chiplets. These chiplets typically provide a specific function implemented in an optimal chip process node. Several chiplets and an optional, custom SOC device mounted and interconnected in a single packing using high speed/bandwidth interfaces that will then deliver monolithic or greater performance at a reduced cost, higher yield, and with only a slightly larger area as a heterogeneous integrated advanced package. As fabless semiconductor companies begin to bring these disaggregated chiplets to market, their successful adoption requires the fabless semiconductor industry to standardize on a set of interface protocols that will offer Lego-like plug and play compatibility between different suppliers chiplets creating a truly open ecosystem and supply chain. When it comes to the physical heterogeneous integration of these chiplets it is typically achieved using a high-performance silicon-like interposer substrate. Such substrates typically require silicon-like design rules and design techniques along with their own specific analysis and verification requirements. The supply chain for these substrates does not change significantly, it is still typically the leading semiconductor foundries and OSATs however the level of interaction, requirements, and signoff approvals does change bringing often new demands and challenges. Is this a revolution or an evolution, it depends on your starting point? Does it need an entirely new set of workflows and design tools? Can we evolve in some stepwise linear process from where we are today with monolithic or traditional system-in-package type designs into this next-generation design environment? This paper will explore these new challenges and outline 5 key workflows that address and manage them. These 5 workflows span interlinked domain areas starting with architecture definition before progressing to design that incorporates planning, prototyping, and technology co-optimization of the chosen architecture as well as the detailed physical implementation of substrates before moving to multi-physics analysis, device-level test, and then manufacturing. This paper will then recommend workflow adoption focus areas that we have seen provide immediate heterogeneous integration capability benefits while providing a managed methodology adoption and migration process that minimizes disruption, risk, and of course cost that can bring heterogeneous integration based chiplet design within reach of the mainstream instead of only being accessible to the mega iDMs and fabless semi’s.

Design and Implementation of Multiple Signal Demodulation Device Based on FPGA

To meet the requirements of other aircraft flight test tasks for multiple types of engines and achieve a device matching multiple engine flight test tasks, a design scheme of a multi-signal demodulation device based on FPGA is proposed. This demodulation device collects and demodulates data such as throttle lever position signal, altitude speed, and switch value. It converts and analyzes the data in series and parallel through FPGA and forwards it to various interfaces such as the EEC interface and airborne testing system. According to the interface protocol requirements, it is converted into signals of types such as RS422, ARINC429, and Ethernet. This multi-signal demodulation device has broad application prospects.

Comparison of edge computing methods in Internet of Things architectures for efficient estimation of indoor environmental parameters with Machine Learning

The large increase in the number of Internet of Things (IoT) devices have revolutionised the way data is processed, which added to the current trend from cloud to edge computing has resulted in the need for efficient and reliable data processing near the data sources using energy-efficient devices. Two methods based on low-cost edge-IoT architectures are proposed to implement lightweight Machine Learning (ML) models that estimate indoor environmental quality (IEQ) parameters, such as Artificial Neural Networks of Multilayer Perceptron type. Their implementation is based on centralised and distributed parallel IoT architectures, connected via wireless, which share commercial off-the-self modules for data acquisition and sensing, such as sensors for temperature, humidity, illuminance, CO2, and other gases. The centralised method uses a Graphics Processing Unit and the Message Queuing Telemetry Transport protocol, but the distributed method utilises low-performance ARM-based devices and the Message Passing Interface protocol. Although multiple IEQ parameters are measured, the training and testing of ML models is accomplished with experiments focused on small temperature and illuminance datasets to reduce data processing load, obtained from sudden spikes, square profiles and sawteeth test cases. The results show a high estimation performance with F-score and Accuracy values close to 0.95, and an almost theorical Speedup with a reduction in power consumption close to 37% in the distributed parallel approach. In addition, similar or slightly better performance is achieved compared to equivalent IoT architectures from related research, but error reduction of 35–76% is accomplished with an adequate balance between performance and energy efficiency.

SDN-Based Reconfigurable Edge Network Architecture for Industrial Internet of Things

Internet of Things (IoT) with edge computing capability enhances efficiency, availability and improves latency of an industrial automation system. However, to provide dynamic services at the resource-constrained edge device, reconfiguration of services is necessary. This paper proposes a programmable edge network to (re)configure different services of industrial IoT, that employs programmable layers at the edge for reconfiguring the sensor/actuator network and application services. The lowermost layer allows reconfiguring the communication-related parameters and the middle layer consists of an SDN controller that can dynamically program different modules and handles actuation decisions from the edge. An interfacing protocol between the layers is proposed to provide reliability by considering the required configuration parameters among layers. At the top-layer, a priority forwarding mechanism is designed for SDN core (control-loop) communication when sensor and actuator are on different edges. The proposed architecture significantly improves the actuation-latency and is highly energy efficient compared to the existing state-of-the-art.

Detection of Bad Data and Estimation of Missing Parameter Values Using System Synergism

Communication infrastructure is paramount for the optimal control and protection of modern-day distribution systems. However, inherent problems associated with the communication systems such as loss of data packets due to excessive latency and erroneous signal induction result in impairment of the network control and relaying signals. In the present article, a method based on Data Mining is proposed for the detection of Bad/Noisy data. Furthermore, the concept of system synergism is utilized to estimate the value of the signal in which Bad Data is detected. In case of Bad measurements during faults/ transients or load switching, the estimates are observed using Machine Learning (ML) based regression model. XGboost has been found to have the best performance among the ML models. Modbus is considered the communication protocol for the power distribution system under the consideration. Test results are demonstrated using a standard IEEE 33 bus test system. The feasibility of the proposed algorithm in real-time is confirmed using the raspberry pi 3B+ controller using Serial Peripheral Interface (SPI) protocol.

Design and Implementation of Advanced Extensible Interface using Verilog

Abstract: Advanced eXtensible Interface, is an interface protocol defined by ARM as part of the AMBA standard. They comprise of AXI4, AXI4 Lite, AXI4 Stream. The AXI specification describes a point-to-point protocol between two interfaces, a master and a slave. The AXI protocol uses 5 channels, 2 for read transactions and 3 for write transactions. One of the key features of AXI4 is its support for burst transactions, which allows for efficient transfer of multiple data items in a single transaction, enhancing data throughput. AXI4-Lite is designed to provide a lightweight and efficient interface for communication between a master device and simpler peripheral devices or memory-mapped registers in a digital system. AXI4-Stream is developed for highthroughput, unidirectional data transfer between different components in a digital system. The design is done in Verilog.

Reduction of lighting power consumption through lighting control using the KNX/digital addressable lighting interface protocol in liquefied natural gas carrier accommodation mock-up

Lighting in ships is the main energy consumer in the overall power system and is closely associated with the creation of visual comfort and a safe work environment for the crew. A convergence point between the energy efficiency of ship lighting and a safe work environment for the crew can be achieved in various ways. This study applied the KNX and Digital Addressable Lighting Interface (DALI) systems to a mega-ship. A mock-up identical to an accommodation unit in an actual Liquefied Natural Gas Carrier in construction was developed, where the lighting for ships was installed and the KNX/DALI protocol, and occupancy sensors were applied as the lighting control system. The measurement of the 24 h power consumption with a conventional lighting arrangement design and the KNX/DALI system indicated that the lighting power consumption decreased from 12,935.2 to 2830.3 W h, implying a ≥80% reduction. This lighting solution involves control based on the traffic line of the crew at work, which plays a key role in enhancing the energy efficiency of the ship, promoting a safe work environment and visual comfort for the crew, and maximizing integration with other digital systems of the ship.

Reflective Fiber Temperature Probe Based on Localized Surface Plasmon Resonance towards Low-Cost and Wireless Interrogation.

Reflection fiber temperature sensors functionalized with plasmonic nanocomposite material using intensity-based modulation are demonstrated for the first time. Characteristic temperature optical response of the reflective fiber sensor is experimentally tested using Au-incorporated nanocomposite thin films deposited on the fiber tip, and theoretically validated using a thin-film-optic-based optical waveguide model. By optimizing the Au concentration in a dielectric matrix, Au nanoparticles (NP) exhibit a localized surface plasmon resonance (LSPR) absorption band in a visible wavelength that shows a temperature sensitivity ~0.025%/°C as a result of electron-electron and electron-phonon scattering of Au NP and the surrounding matrix. Detailed optical material properties of the on-fiber sensor film are characterized using scanning electron microscopy (SEM) and focused-ion beam (FIB)-assisted transmission electron microscopy (TEM). Airy's expression of transmission and reflection using complex optical constants of layered media is used to model the reflective optical waveguide. A low-cost wireless interrogator based on a photodiode transimpedance-amplifier (TIA) circuit with a low-pass filter is designed to integrate with the sensor. The converted analog voltage is wirelessly transmitted via 2.4 GHz Serial Peripheral Interface (SPI) protocols. Feasibility is demonstrated for portable, remotely interrogated next-generation fiber optic temperature sensors with future capability for monitoring additional parameters of interest.

Peer-to-peer media streaming with HTML5

&lt;p class="Affiliation"&gt;&lt;span lang="EN-US"&gt;The knowledge of web real-time communication (WebRTC) and how its customers and server operations are defined in this study. However, the world wide web consortium (W3C) and the internet engineering task force (IETF) have not yet approved an absolute signaling protocol or a complete application programming interface (API) protocol to implement WebRTC and control communication planning. WebRTC requires some type of signaling mechanism. With Chrome, Firefox, and Opera, the primary objective is to create and implement a WebRTC video call across two clients (peers) in the real world while employing local area network (LAN) and wide area network (WAN). This study also demonstrated the design of the server (as an intermediary) and graphical user interface (GUI). Additionally, a signaling method for the peer-to-peer browser connection on the Node.js platform has been developed and successfully put into use. This paper will provide an understanding of web development and an ability to understand WebRTC technology. It will also discuss how to create WebRTC signaling mechanisms and build video conferencing, as well as how to increase design quality using quality of experience (QoE) techniques.&lt;/span&gt;&lt;/p&gt;

Distributing and Synchronizing Signals Between the Worlds of SDI and IP

Moving signals between the worlds of serial digital interface (SDI) and Internet Protocol (IP) is not exactly rocket science, but synchronizing these signals may prove to be a challenge. It is these cases that we will discuss in this article and these challenges to which we seek to identify and present a viable and cost-effective solution. We will consider a recent Riedel project with a major U.S. broadcaster. Following the decision to move its operations to ST 2110, this broadcast network experienced synchronization problems between its IP-based flagship station and more than 200 affiliate stations throughout North America relying on SDI. The fact that the remote feed needed to be compressed posed yet another challenge, as it required the decompressed signal to be decoded to ST 2110 before it could be converted to SDI. The Riedel team managed to solve the synchronization issue with a single, powerful device smaller than the size of your thumb: A software-defined processing small form-factor pluggable (SFP) device that enabled the conversion of UHD-1 and ST 2110 signals for bidirectional distribution between the headquarters and the affiliate stations while generating a Precision Time Protocol (PTP) Grand Master clock from the affiliate’s synchronized signal. This greatly reduced both system complexity and the cost of replacing the entire affiliate synchronization system. After a general description of the specific use-case setup, we will present an overview of the various possible solutions and weigh the pros and cons before focusing on the most viable solution. After short explanations of the demarcation switch configuration and the Epoch reference generation at the affiliate sites, we conclude with an outlook on other potential use cases.

A Composite Pipeline for Forwarding Low-Latency Traffic in SDN Programmable Data Planes

With the rapid evolution of network technologies over recent years, emerging network services, especially industrial control networks, video conferencing, intelligent driving, and other scenarios, have put forward higher demand for the low-latency forwarding of network traffic. The existing flow caching and hardware acceleration methods only improve the overall forwarding performance of data-plane devices but cannot separate the forwarding process of low-latency traffic from others to reflect the priority of these flows. In this paper, we extend the POF southbound interface protocol and propose a marking method for low-latency flows, based on which we design a composite pipeline to achieve fast processing for low-latency traffic by introducing a fast-forwarding path. The experiments show that the fast path has a higher forwarding capability than the MAT pipeline in the POF Switch and can reduce the forwarding delay of low-latency flows by 62–68%. In a real network environment with a mixed traffic simulation, the reduction reaches 17–20% with no delay increment for the non-low-latency part.