Design and Implementation of Advanced Extensible Interface using Verilog

Abstract

Abstract: Advanced eXtensible Interface, is an interface protocol defined by ARM as part of the AMBA standard. They comprise of AXI4, AXI4 Lite, AXI4 Stream. The AXI specification describes a point-to-point protocol between two interfaces, a master and a slave. The AXI protocol uses 5 channels, 2 for read transactions and 3 for write transactions. One of the key features of AXI4 is its support for burst transactions, which allows for efficient transfer of multiple data items in a single transaction, enhancing data throughput. AXI4-Lite is designed to provide a lightweight and efficient interface for communication between a master device and simpler peripheral devices or memory-mapped registers in a digital system. AXI4-Stream is developed for highthroughput, unidirectional data transfer between different components in a digital system. The design is done in Verilog.