Oxide Charge Interface Research Articles

Negative-to-Positive Differential Resistance Transition in Ferroelectric FET: Physical Insight and Utilization in Analog Circuits.

In this article, for the first time, we explained a detailed physical insight for negative differential resistance (NDR) to positive differential resistance (PDR) transition in a ferroelectric (FE)-based negative capacitance (NC) FET and also its dependence on the device terminal voltages. Using extensive well-calibrated TCAD simulations, we have investigated this phenomenon on fully depleted silicon on insulator (FDSOI)-NCFET. The NDR-to-PDR transition occurs due to FE layer capacitance changes from a negative to positive state during channel pinchoff. This, in turn, results in a valley point in the output characteristic ( IDS - VDS ) at which the output resistance is infinite. We also found that we could alter the valley point location by modulating the vertical electric field through the FE layer in the channel pinchoff region using body bias ( VBB ). The interface oxide charges also impacted the NDR to PDR transition, and a positive interface charge results in faster NDR to PDR transition. Furthermore, we have utilized the modulation in the NDR-to-PDR transition due to VBB for designing a current mirror. Results show that the output current ( IOUT ) variation due to VDS reduces from ~8% to ~2% with VBB . We have also designed a single-stage common source (CS) amplifier and provided design guidelines to achieve a higher gain in the NDR region. The results obtained using a small-signal model of the FDSOI-NCFET demonstrate that ~25% higher gain can be achieved with the discussed design guidelines in the NDR region compared to the transition region of IDS - VDS . We have also explored the device scaling effect on the amplifier gain and found that ~ 2.23× gain can be increased with smaller channel length and higher device width.

Modeling of Semiconductor Substrates for RF Applications: Part II—Parameter Impact on Harmonic Distortion

This article presents the accurate modeling results of the nonlinear behavior of a wide range of silicon-based substrates at RF. The TCAD-based model includes carrier inertia effects and captures the transient nonequilibrium phenomena in the semiconductor substrate regions in response to a large-amplitude RF signal. The model is applied to coplanar waveguide (CPW) lines measured on 19 different silicon-based samples that have key differences in their material and interface parameters, such as different values for nominal doping, interface oxide charge, the presence or not of a trap-rich passivation layer, and characteristic dimensions. Furthermore, the CPW line's distortion levels are measured from 25 °C up to 175 °C and at five fundamental frequencies under large-signal excitation from 50 MHz to 5.4 GHz. An excellent model to experiment correlation is achieved under all of these conditions, and the impact of the material and excitation parameters are discussed with strong physical insight provided by the simulation tool.

Analytical modeling of subthreshold current and swing of strained‐Si graded channel dual material double gate MOSFET with interface charges and analysis of circuit performance

AbstractIn this paper, a two‐dimensional (2‐D) center channel potential based subthreshold current (SC) and subthreshold swing (SS) are developed analytically for strained‐Si (s‐Si) graded‐channel dual‐material double gate (GC‐DMDG) MOSFET with interface charges. The proposed analytical model is extracted by solving 2‐D Poisson equation in s‐Si graded‐channel using appropriate boundary conditions. The analytical 2‐D model includes effects of various MOSFET parameters such as s‐Si channel length, strain in the silicon substrate, and oxide interface charge density with damaged length by extensively analyzing channel potential, SC, and SS. Also, the subthreshold characteristics of the proposed s‐Si GC‐DMDG MOSFET demonstrate superior performance over s‐Si graded channel double gate MOSFET. The numerical results obtained using TCAD of the proposed DG MOSFET are validated with the results attained from proposed analytical model. Moreover, the performance of CMOS inverter using s‐Si GC‐DMDG MOSFET is evaluated for different device parameters. It is investigated that the proposed s‐Si GC‐DMDG MOSFET has better noise margin than s‐Si GC‐DG MOSFET.

Analytical drain current model of stacked oxide SiO2/HfO2 cylindrical gate tunnel FETs with oxide interface charge

In this paper, we have developed an analytical drain current model of stacked oxide SiO2/HfO2 cylindrical gate tunnel field-effect transistor (CG TFET) by considering the effect of interface trap charge at Si–SiO2 interface nearby the source–channel junction. To model the channel potential, Poisson’s equation has been solved by using the parabolic approximation method in a cylindrical coordinate system with appropriate boundary conditions. The potential model has then been utilized for developing some expressions for minimum tunneling length, lateral electric field, and the drain current of stacked oxide SiO2/HfO2 CG TFET. The impact of the source/drain depletion region has been considered for improving the accuracy of the proposed model. The commercially available ATLAS™ 3D-based TCAD simulation data have been used to validate the proposed model results.

Modeling and TCAD Assessment for Gate Material and Gate Dielectric Engineered TFET Architectures: Circuit-Level Investigation for Digital Applications

This paper deals with the development of a generalized model describing the device electrostatic behavior of three different double gate n-type tunnel FET (TFET) architectures, i.e., dual material gate (DMG) TFET, heterodielectric (H-D) TFET, and dual material gate heterodielectric (DMG H-D). The model is advantageous in capturing the impact of dielectric and the metal gate length variation where a comparative study among these three aforementioned device architectures has been made in terms of various electrostatic parameters, such as surface potential, energy-band profile, and electric field, incorporating the impact of interface oxide charges. Subsequently, TCAD-based digital performance investigation for all these architectures has been performed where their capacitive behavior and the transient performance has been carefully analyzed and optimized by varying the metal work function (M <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> ) and length (L <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> ) value for both, i.e., the dielectric material and the metal gate. Both the modeling and simulation results reveal that the proposed architecture, i.e., DMG H-D TFET, outperforms the other two architectures, i.e., DMG and H-D TFET.

Tunneling Contact Passivation Simulations using Silvaco Atlas

TCAD simulations of a p-Si/Al2O3/Al structured solar cell are done to improve the understanding of parameters important for tunneling contact passivation. High efficiencies are achieved for oxide thicknesses below 1.4nm and for an oxide interface charge concentration of -1×1013 cm-3. The dependence of the work function of Al is shown. The effective mass of bulk Al2O3 is found to be too large for tunneling to occur, so a smaller effective mass is likely for thin films. The simulations of charges, work function, band gap and dielectric constant can also be used as a basis for choosing new tunneling materials.

Analysis of the Electron Traps at the 4H-SiC/SiO&lt;sub&gt;2&lt;/sub&gt; Interface of a Gate Oxide Obtained by Wet Oxidation of a Nitrogen Pre-Implanted Layer

This work is focusing on the effect of a high concentration of nitrogen (N) introduced by ion implantation at the SiO2/4H-SiC interface in MOS capacitors. The N implanted sample (Ninterface ~1x1019cm-3) is compared with a non-implanted one (Ninterface ~1x1016cm-3) by means of the electron interface trap density (Dit). The Dit is determined via High-Low frequency C-V method and Thermal Dielectric Relaxation Current (TDRC) technique. It is shown that the TDRC method, mainly used so far for determination of near interface oxide charges, can be exploited to gain information about the Dit too. The determined value of Dit in the N-implanted sample is nearly one order of magnitude lower than that in the sample without N implantation. Good agreement between the TDRC results and those obtained from High-Low frequency C-V measurements is obtained. Furthermore, the TDRC method shows a high accuracy and resolution of Dit evaluation in the region close to the majority carrier band edge and gives information about the traps located into the oxide.

High-Voltage SOI SJ-LDMOS With a Nondepletion Compensation Layer

A new superjunction LDMOS on silicon-on-insulator (SOI) with a nondepletion compensation layer (NDCL) is proposed. The NDCL can be self-adaptive to provide additional charges for compensating the charge imbalance while eliminating the substrate-assisted depletion effect. In addition, the high-density oxide interface charges at the top surface of the buried oxide layer (BOX) enhance the electric field in the BOX and improve the vertical breakdown voltage (BV). Numerical simulation results indicate that a uniform surface electric field profile is obtained and that the vertical electric field in BOX is increased to 6 times10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">6</sup> V/cm, which results in a high BV of 300 V for the proposed device with the BOX thickness of 0.5 mum and drift length of 15 mum on a thin SOI substrate.

A novel area efficient floating field limiting ring edge termination technique

In this paper, a floating ring edge termination structure using minimally sized lightly doped p-rings is proposed. A novel embodiment of the structure involves placement of shallow p +-regions offset from the centre of each of the p-well rings to reduce peak electric field at the surface and to reduce sensitivity to oxide interface charges. The structures have been fabricated using an advanced, 2 kV MOS-bipolar process technology. A close match between the simulated and experimental results validates the proposed structure.

The effect of discharge conditions on the inductively coupled plasma oxidation of silicon

Plasma oxidation of silicon offers advantages over conventional thermal oxidation in that it is a low temperature (<500°C) method of thin film production which takes place in a clean vacuum environment. The growth rate and also the electrical properties of the oxides are a strong function of the plasma input power, pressure and system geometry. In this paper the effect of these discharge conditions on oxide growth rate, electrical breakdown strength and oxide interface charge levels is presented. By optimisation of the discharge conditions and by suitable temperature annealing, device quality oxides have been produced which have oxide interface charge levels in the range 10 10–10 11 cm 2 and electrical breakdown strengths in excess of 10 MV cm −1.

Low-energy ion bombardment of silicon dioxide films on silicon

Exposure of SiO2 layers on silicon to a plasma environment during sputtering or backsputtering leads to degradation of the electrical properties of the interface. In this paper the effects of the ion bombardment occurring during such exposure are detailed. A low-energy ion-bombardment apparatus, capable of giving ion beams ranging from 100 nA at 10 eV to 5 μA at 3.0 keV of mass-analyzed gas ions, constructed for this study, is described. Bombardment of SiO2 layers by Ar+, N+, or N2+ ions of any energy from 10 to 2800 eV leads to increase in interface state density and oxide interface charge. The oxide charge after bombardment is located both in the region of the Si/SiO2 interface and in the outside 50 Å of the SiO2. Both induced oxide interface charge and interface state density increase linearly with dose to a saturation value, typically to 8×1012 charges/cm2 and 1013 interface states/cm2 eV at midgap after a dose of 8×1013 ions/cm2 at 600 eV, on 1000Å of SiO2. At constant dose the induced charge and interface state density increase linearly with energy to approximately 500 eV, then are independent of energy to the maximum energy studied. After ion bombardment to a dose of ions of 5×1013/cm2 or greater, SiO2 films exhibit a significant reduction in dielectric strength. This reduction is not completely recoverable by annealing to temperatures up to 600°C. Annealing to 600°C does, however, remove all interface charge, interface states, and room-temperature trapping instabilities produced by the bombardment, as measured at room temperature after annealing. These experiments show that ion bombardment is capable of producing MOS degradation similar to some of the MOS degradation observed after sputter deposition of metals over oxide films. The increase in charge and interface states is a function of dose, so adjustment of plasma parameters during sputtering to give minimum ion bombardment should minimize this buildup of charge.