Abstract
This article presents the accurate modeling results of the nonlinear behavior of a wide range of silicon-based substrates at RF. The TCAD-based model includes carrier inertia effects and captures the transient nonequilibrium phenomena in the semiconductor substrate regions in response to a large-amplitude RF signal. The model is applied to coplanar waveguide (CPW) lines measured on 19 different silicon-based samples that have key differences in their material and interface parameters, such as different values for nominal doping, interface oxide charge, the presence or not of a trap-rich passivation layer, and characteristic dimensions. Furthermore, the CPW line's distortion levels are measured from 25 °C up to 175 °C and at five fundamental frequencies under large-signal excitation from 50 MHz to 5.4 GHz. An excellent model to experiment correlation is achieved under all of these conditions, and the impact of the material and excitation parameters are discussed with strong physical insight provided by the simulation tool.
Highlights
N OWADAYS, the most advanced CMOS nodes are boasting impressive high-frequency figures of merit (FoM), proposing an attractive path for cost-effective mass-market productions of RF and mm-wave applications [1].Circuit elements that behave in a nonlinear fashion are usually undesirable in a system chain, as they introduce signal distortion between the input and the output waveforms
The impact of coplanar waveguide (CPW) line geometry on the RF FoMs ρeff and H 2 is studied through simulations and validated against measurement data
Large-signal on-wafer RF measurements of CPW lines were performed on 19 different wafers under various conditions in order to validate the TCAD-based largesignal model and quantitatively evaluate parameter impact on substrate-induced harmonic distortion (HD)
Summary
N OWADAYS, the most advanced CMOS nodes are boasting impressive high-frequency figures of merit (FoM), proposing an attractive path for cost-effective mass-market productions of RF and mm-wave applications [1]. A breakthrough was made in the early 2000s by introducing a thin trap-rich (TR) polysilicon layer beneath the buried oxide in silicon-oninsulator (SOI) technology [3] This layer effectively mitigates the PSC effect by pinning the Fermi-level near mid-gap at the interface in a highly resistive state, enabling ρeff values of over 1 kcm, and is widespread in the radio-frequency integrated circuit (RFIC) industry today in the RF enhanced signal integrity (RFeSI) SOI substrates [4], [5]. These considerations motivate the development of both small- and large-signal RF models of silicon-based substrates. The approach’s validity is demonstrated over a wide range of parameters, including material properties (interface charge, trap density, and nominal doping), excitation parameters (frequency, dc bias, and temperature), and device under test (DUT) dimensions (CPW line length and width), and the impact of these on the overall induced HD is well quantified
Sign-in/Register to view highlights & summary Talk to us
Join us for a 30 min session where you can share your feedback and ask us any queries you have
Schedule a callDisclaimer: All third-party content on this website/platform is and will remain the property of their respective owners and is provided on "as is" basis without any warranties, express or implied. Use of third-party content does not indicate any affiliation, sponsorship with or endorsement by them. Any references to third-party content is to identify the corresponding services and shall be considered fair use under The CopyrightLaw.
