Effect Of Interface Charge Research Articles

Modeling of radiation-induced leakage currents in CMOS/SOI devices

A new approach to model the effect of radiation-induced interface charges on silicon-on-insulator (SOI) devices has been implemented in a three-dimensional device simulation code. The model is validated by comparison of simulated and measured postradiation device characteristics. The applicability of the model is illustrated by analysis of standard and fully-depleted silicon-on-sapphire (SOS) devices. The results demonstrate and clarify the role of various bias conditions on parasitics in SOI structures and offer an explanation of the observed absence of back-channel conduction in fully-depleted nMOS-SOS transistors.< <ETX xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">&gt;</ETX>

The fabrication of metal–oxide–semiconductor transistors using cerium dioxide as a gate oxide material

Cerium dioxide was employed as a gate insulator for an enhancement-type n-channel metal–oxide–semiconductor (MOS) transistor. Cerium was evaporated in a tungsten boat and immediately oxidized for oxide uniformity. The use of CeO2 as a gate oxide in MOS transistor yielded a low positive threshold voltage with negligible interface charge effects. This resulted in the transistor performing as an enhancement type device.

Interface and oxide charge effects on DMOS channel mobility

The channel mobility in n-channel DMOS power transistors was examined as a function of interface- and oxide-trappedcharge densities. Interface trapped charge was the primary contributor to mobility degradation. Any apparent dependence of mobility on oxide-trapped-charge density can be attributed to correlation between interface-and oxide-trapped-charge densities.

Characterization of the inverse-narrow-width effect

The inverse-narrow-width effect, the reduction in the threshold voltage with decreasing device width, is modeled and experimentally measured. A fringing gate capacitance model is extended to include the effects of the sidewall interface charge. Two- and three-dimensional simulations are used to illustrate the enhanced sidewall potential and current, and the effect of sidewall interface charge on the electrical behavior of MOSFET's with fully recessed isolation oxides. We compare the closed-form analytical threshold voltage expression developed with experimental data from small-geometry NMOS devices and find very good agreement.

Effects of interface charge on the quantum Hall effect.

The dependence of the quantum Hall effect on systematic changes in the electronic scattering has been studied in experiments on the inversion layer electrons in Si metal-oxide-semiconductor field-effect transistors which have driftable ${\mathrm{Na}}^{+}$ ions in the oxide. The widths and positions of the quantum Hall plateaus corresponding to filled valley levels, filled spin levels, and filled Landau levels were measured for oxide charges up to ${10}^{12}$ ${\mathrm{cm}}^{\mathrm{\ensuremath{-}}2}$ at a temperature of 1.35 K and a magnetic field of 13 T. The widths of the plateaus were observed to increase with increasing oxide charge, which is consistent with a picture in which the number of localized states at band edges increases with increased electronic scattering. With increasing interface charge, however, the positions of the plateaus corresponding to filled valley and filled spin levels exhibited systematic shifts with respect to those for filled Landau levels.

The effect of interface charge on the quantum Hall effect

The effect of interface charge on the quantum Hall effect

The effect of interface charge on the quantum hall effect

The effect of interface charge on the quantum hall effect

A Simple Model for Separating Interface and Oxide Charge Effects in MOS Device Characteristics

A simple model to describe radiation effects on MOSFET electrical characteristics is presented. The key assumption is that mobility degradation in an enhancement mode MOSFET is predominantly due to charged interface traps. Model predictions are compared with measured values of interface trap density and device I - V curves.

Potential Distribution of an Inhomogeneously Doped MIS Array

A numerical method is used to obtain the potential distribution of a two-dimensional, inhomogeneously doped MIS array under pulse voltage operation. The effects of interface charge and of impurity doping and its locations on the surface potential profile are presented. The technique is useful for designing an appropriate surface potential profile for ion-implanted charge-coupled devices.

Surface charges and surface potential in silicon surface inversion layers

The effect of interface charges on the channel conductance in MOS transistors has been investigated. It has been found that, by measuring the conductance as a function of temperature, it is possible to determine both the "fixed" interface charge which is independent of the surface potential and the charge trapped in surface states whose occupancy is a function of the surface potential. The characteristics of the two charge components are discussed. It appears that neither a continuous nor a delta-function energy distribution alone is adequate to describe the observed surface-state density.