Interconnection Techniques Research Articles

Testing station for fast screening of through silicon via-enabled application-specific integrated circuits for hard x-ray imaging detectors

Application-specific integrated circuits (ASICs) are used in space-borne instruments for signal processing and detector readout. The electrical interface of these ASICs to frontend printed circuit boards is commonly accomplished with wire bonds. Through silicon via (TSV) technology has been proposed as an alternative interconnect technique that will reduce assembly complexity of ASIC packaging by replacing wire bonding with flip-chip bonding. TSV technology is advantageous in large detector arrays where TSVs enable close detector tiling on all sides. Wafer-level probe card testing of TSV ASICs is frustrated by solder balls introduced onto the ASIC surface for flip-chip bonding that hamper alignment. Therefore, we developed the ASIC test stand (ATS) to enable rapid screening and characterization of individual ASIC die. We successfully demonstrated ATS operation on ASICs originally developed for CdZnTe detectors on the Nuclear Spectroscopic and Telescope Array (NuSTAR) mission that were later modified with TSVs in a via-last process. We tested both backside blind-TSVs and frontside through-TSVs, with results from internal test pulser measurements that demonstrate performance equal to or exceeding the probe card wafer-level testing data. The ATS can easily be expanded or duplicated to parallelize ASIC screening for large area imaging detectors of future space programs.

224-Gbit/s 4-PAM operation of a high-modulation-bandwidth high-output-power Hi-FIT AXEL transmitter.

We fabricated an optical transmitter with high frequency and integrated design based on the flip-chip interconnection technique (Hi-FIT) and assisted extended reach electroadsorption modulator integrated distributed feedback (EADFB) laser (AXEL) for 200-Gbit/s/λ application. The Hi-FIT makes it possible to increase modulation bandwidth thanks to wire-free interconnection and peaking control techniques while the AXEL can increase the optical modulation output power thanks to an integrated semiconductor optical amplifier (SOA). The fabricated Hi-FIT AXEL transmitter has a 3-dB bandwidth of more than 66 GHz. We obtained clear 224-Gbit/s 4-level pulse amplitude modulation (4-PAM) eye diagrams with a chip-output optical modulation amplitude (OMA) of more than +7.9 dBm at distributed feedback (DFB) laser and SOA currents of 70 and 30 mA, respectively.

Study of low-temperature interconnection techniques for instant assembly of electronics on stretchable e-textile ribbons

This article addresses the research and development of a reliable interconnection technique for mounting surface mounted device components onto newly developed conductive stretchable textile ribbons. The alternative nonconductive adhesive bonding in which electrical contact is realized only by mechanical pressure and fixed by an adhesive and the conventional soldering technique were selected for examination. Assessment of the performance of these techniques and their usability for interconnecting components on conductive textile ribbons was also our research goal. Reliability tests of the electrical and mechanical properties of realized interconnections (dry heat, damp heat, washing, electrical current load, jerk, and stretch tests) were realized. The results show that the nonconductive adhesive technique results in good mechanical properties and acceptable median electrical resistance of less than 2 Ω even after 90 washing cycles. It is also very gentle and fully compatible with textile production due to the maximal processing temperature lower than 70°C, without the risk of short circuit occurrence. This technique is suitable for sensors, illumination or data transfer applications. While soldering results in excellent median electrical resistance of less than 20 mΩ, it is more complex and costly. Moreover, there is a risk of short circuits as well as of textile damage by the high thermal load over 150°C. Soldering is more suitable for power supply applications or heating. The above-mentioned results were also confirmed in a decision analysis with pairwise comparisons, involving company representatives considering introducing the above-mentioned interconnection techniques into their production. The nonconductive adhesive technique was evaluated as 15% better in overall decision analysis than the low-temperature soldering.

In situ investigation on melting characteristics of 1D SnCu alloy nanosolder

Nanosoldering can bond various nanomaterials together or connect them with electrodes to form electrical contacts, thus assembling these nanomaterials into functional nanodevices; it is believed to be a promising interconnection technique due to its flexibility, controllability and crucial advantage of avoiding detrimental effects on the nano-objects. In this technique, molten solder as a filler material is introduced between the objects to be joined to form a reliable bond, in which the nanosolder reflow melting is a crucial prerequisite for successful nanosoldering. This work focuses on studying the melting characteristics of one-dimensional 97Sn3Cu nanosolder with low-cost, prominent electrical property and high mechanical reliability, aiming to promote its applications in nanosoldering. The reflow melting of an individual nanosolder has been dynamically observed by in situ heating holder in transmission electron microscopy, where the obtained reflow temperature (530 °C) is much higher than its melting temperature (220.4 °C) because of the external oxide layer confinement. Furthermore, the size-dependent melting temperature of nanosolders with various diameters (20–300 nm) has been investigated by both differential scanning calorimetry and theoretical calculation, revealing that the melting temperature decreases as the diameter goes down, especially for the nanosolders in the sub 80 nm range, where the value decreases significantly. The experimental results are in good agreement with the theoretical predictions. These results pointed out here can be readily extended to other nanosolders.

Design of a Graphene-Enabled Dual-Mode Kerr Frequency Comb

On-chip Kerr frequency combs open up unprecedented opportunities for developing compact, low-cost, and high-density wavelength-division multiplexing (WDM) techniques for optical communications and optical interconnects. However, to achieve high-density WDM channels, a large-radius microring could be used to develop a Kerr frequency comb with a small free spectral range (FSR), inevitably increasing the comb's footprint and threshold. Herein, we theoretically study a dual-mode Kerr frequency comb based on a graphene-on-silicon (GOS) microring to overcome the limitation. Theoretical results show that a TE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> -mode comb with a 50-dB bandwidth of 200 nm and FSR of 170 GHz, and a TE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> -mode comb with a 50-dB bandwidth of 130 nm and FSR of 212.4 GHz could be generated in the single GOS microring. Moreover, the TE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> -mode and TE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> -mode combs could be selectively activated via modulating the Fermi level of the graphene nanoribbons integrated on the silicon microring. The study is expected to provide a useful technique for developing on-chip coherent light sources for high-speed optical communications.

Analysis and Design of the Tank Feedline in Millimeter-Wave VCOs

This article presents a detailed analysis of the impact of the tank feedline on tuning range (TR) and phase noise (PN) in millimeter-wave <i>LC</i> voltage-controlled oscillators (VCOs). A robust extended TR design, with low PN and small die area, is later proposed, analyzed, and experimentally validated. A new interconnect approach for the coarse tuning capacitor bank is used to significantly reduce the <i>LC</i> tank routing capacitance and resistance, thus improving the TR and PN of the VCO. As a proof of concept, a 26.8-GHz VCO with a 5-bit digitally switched-capacitor bank [capacitor digital-to-analog converter (C-DAC)] is implemented using a folded feedline routing structure in a digital 45-nm CMOS silicon-on-insulator (SOI) technology. Compared to a conventional layout structure, the proposed interconnect technique yields a wider TR and lower losses while significantly improving the linearity of the C-DAC. The fabricated VCO yields a TR of 33&#x0025;, covering the extended 5G frequency band with a sufficient margin from 22.4 to 31.2 GHz, with a minimum overlap of 40&#x0025;. Moreover, it achieves a PN of &#x2212;105.5 and &#x2212;97.2 dBc/Hz at a 1-MHz offset at the low and high bands, respectively, while dissipating 6 mW from a 1.0-V supply, corresponding to an average FOM_T of &#x2212;192.6 dBc/Hz.

A Mini Review on the Microvia Filling Technology Based on Printed Metal Nano/Microparticles

Microvia filling is a core interconnection technique in electronic manufacturing. Electroplating is the primary method used in the industry for filling microvias but also has the drawbacks of cumbersome procedures and toxic by-products. New microvia filling technology through printing of metal particle–based conductive fillers was then developed, with the advantages of simpler process, higher efficiency, better compatibility, and eco-friendliness. Here, we review the up-to-date research findings on the microvia filling technology based on printed metal nano/microparticles from the perspectives of material development and filling performance. Some key questions about this technology are also discussed. We hope the outlook presented by this review could help the further studies on this topic. The review also identifies some key remaining issues to be resolved.

Influence of Sweat on Joint and Sensor Reliability of E-Textiles

This article addresses reliability under the sweat of interconnection techniques for the mounting surface mounted device (SMD) components and fully printed humidity sensors onto conductive stretchable textile ribbons. Samples underwent testing for the effect of ageing by artificial sweat on their electrical resistance using both alkaline and acidic artificial sweat. The best results in terms of electrical resistance change were obtained for samples soldered to the conductive fibers interwoven in the ribbon. However, this method can damage the ribbon due to the high temperature during soldering and significantly reduce the mechanical properties and flexibility of the ribbon, which can lead to a limited service life of samples. On the other hand, adhesive bonding is a very interesting alternative, where the above-mentioned properties are preserved, but there is a significant effect of sweat ageing on electrical resistance. The results of fully printed graphene-based humidity sensors show that, for the intended use of these sensors (i.e., detection of changes in moisture on the human body), usage of the samples is possible, and the samples are sufficiently reliable in the case of sweat degradation. In addition, the response of the sensor to humidity is quite high: 98% at a relative humidity of 98%.

Aggregated CDMA Crossbar With Hybrid ARQ for NoCs

Network-on-chips (NoCs) are the dominant interconnection technique in modern system-on-chips (SoCs). The medium access technique used in the physical layer of NoC routers profoundly impacts the performance and footprint of the router. Code division multiple access (CDMA) is a medium access technique widely deployed in various wireless communication systems, and it has recently been proposed as a prominent switching method for NoC routers. In a CDMA crossbar, several processing elements (PEs) can communicate simultaneously over a single communication channel by applying the direct-sequence spread spectrum technique to digital interconnects. However, existing CDMA switches are bit-wise architectures in which a binary data bit is spread and serially communicated on an exclusive digital channel while replicating this configuration to communicate multiple data bits, which increases the crossbar area and wiring density. In this work, we propose aggregated CDMA (ACDMA) to improve the area, throughput, and power consumption of existing CDMA NoC routers. ACDMA exploits the static nature and relative noise immunity of on-chip interconnects to aggregate transmission of multiple data bits into M-ary symbols on a single digital communication channel, which significantly reduces the wiring density and area overhead of the crossbar. Serial and parallel variants of the ACDMA crossbar offering a wide range of area-speed trade-offs are implemented in the ASIC <inline-formula> <tex-math notation="LaTeX">$65~nm$ </tex-math></inline-formula> standard cell technology. The implementation results show that the throughput-per-area (TPA) of the serial and parallel ACDMA crossbars is improved by 96.3&#x0025;, 18.2&#x0025;, and 118.6&#x0025;; and 400&#x0025;, 255.3&#x0025;, and 184.2&#x0025; compared to the serial and parallel counterparts of the Walsh Basis (WB), Standard Basis (SB), and Overloaded CDMA Interconnect (OCI) crossbars, respectively. A 65-node ACDMA NoC router is fully realized and compared to the state-of-the-art CDMA and CONNECT NoC routers under multiple synthetic workloads. Communication reliability of the ACDMA NoC router subject to noise is investigated and a hybrid ARQ approach is proposed to improve the interconnect reliability.

Experimental and Theoretical Investigation of the Copper (II)/Co Cementation Reaction

Cobalt is a potential candidate as an adhesion layer in the copper metallization for its low resistivity and high thermal stability.(1) The electrodeposition of copper onto the cobalt substrate is a promising technique for the next generation interconnects. However, the cementation reaction of copper (II)/Co creates an irregular interface, and it’s not possible to apply the mature copper damascene plating technique.(2) In this work, we studied the Copper (II)/Co cementation reaction using a rotating disk electrode (RDE) and developed a continuum model to gain insight into the copper (II)/Co cementation reaction.Experimental section: a thin film of cobalt is firstly plated on the Pt RDE in a three-chamber cell filled with the electrolyte containing 50 mM CoSO4 and 0.5M H3BO3 (pH =2.6). A constant current is applied for a certain period of time (0.7 mA, 20 s) while the electrode is rotating at 700 rpm. The electrode is designated as Co/Pt electrode. After the deposition, the Co/Pt electrode is washed by ultrapure water and dried by nitrogen before it’s moved to another three-chamber cell. The electrode is immersed into the electrolyte containing 10mM CuSO4 and 50mM Na2SO4 while rotating at 900 rpm. The open-circuit potential is recorded in the whole process to identify the species and possible relations on the electrode surface.Figure 1 is the chronopotentiogram of a cobalt film reacting with copper(II) solution. As shown, fresh cobalt is replaced by the Cu in stage a, and a temporary equilibrium is reached in stage b, where the surface is a layer of newly formed metallic copper. A phase transition between copper and copper oxide is observed in stage c, and stage d represents a layer of CuOx, which is a dark color. (3) The intercept between stage and stage b will be used to extract the rate constant of the cementation reaction for modeling study. H.-S. Lu, J.-X. Wang, X. Zeng, F. Chen, X.-M. Zhang, W.-J. Zhang and X.-P. Qu, Electrochemical and Solid-State Letters, 15, H97 (2012).W.-Z. Xu, J.-B. Xu, H.-S. Lu, J.-X. Wang, Z.-J. Hu and X.-P. Qu, J Electrochem Soc, 160, D3075 (2013).J. Xiong and I. M. Ritchie, Hydrometallurgy, 16, 301 (1986). Figure 1

T-Branch Waveguide Mirror for Multimode Optical Splitter With Arbitrary Power Ratios

Mode-division multiplexing is an enabling technique for large-capacity on-chip optical interconnects. Multimode power splitter becomes the subject of interests which is highly desirable. However, challenges still exist for multimode splitter with arbitrary power ratio. Inspired by geometric optics, we demonstrate a series of power splitters based on T-branch waveguide mirrors which consist of subwavelength nanoholes. Arbitrary split ratio can be achieved by modifying the transmittance and reflectance of the waveguide mirrors. The devices can support up to 9 modes from TE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> -TE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">8</sub> . For a proof-of-concept demonstration, we fabricate dual-mode splitters with power ratios of 40:60, 30:70 and 20:80. For both TE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">0</sub> and TE <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1</sub> modes, the measured excess losses are lower than 0.92 dB, and the crosstalk are all below -14.42 dB within the wavelength range from 1540 to 1580 nm.

Evaluation of detatchable board-to-board interconnects on screen printed electronic structures

Hybrid printed electronics (HPE) combines advantages of conventional electronics manufacturing technologies such as surface mount technology with those of printed electronics in order to realize more complex electronic systems. To realize the final product, such HPE subassemblies have to be connected to higher-level assemblies. So far interconnection techniques for the so-called level 3 interconnection between printed subsystems and standard electronics have not yet been considered adequately in scientific research. In this paper, alternative detachable level 3 interconnection technologies, i.e. spring loaded contact pins, zero insertion force (ZIF) as well as Non-ZIF connectors are investigated systematically regarding their electrical behaviour against the background of printed electronics. Screen-printed silver filled polymer thick film paste is used to realize printed conductor patterns on flexible polymer substrates, which are connected later on with the alternatives mentioned above. Transition resistance is measured using the four wire method as produced, after repeated mating cycles as well as after accelerated aging tests. The various electrical contacts are subjected to thermal stress in temperature cycling testing and during aging at a constant high temperature. As a result it can be stated, that the sping-loaded contact pins used in this investigation show superior behavior compared with the selected connectors in terms of resistance increase after mating cycles. Concerning long-term behavior after thermal cyling and high temperature storage, all investigated alternaives reveal convincing results.

A PSO based optimal repeater insertion technique for carbon nanotube interconnects

ABSTRACT Optimal repeater insertion is important in VLSI(very large scale integration) interconnects to reduce propagation delay and power dissipation. We propose a particle swarm optimisation (PSO)-based optimal repeater number for different lengths of carbon nanotube (CNT) interconnects at 20 nm and 14 nm technology nodes. First, numerical equations for optimal repeaters are modelled. Secondly, a PSO-based algorithm is developed and various input parameters are used to train the PSO. Optimal number of repeaters and the propagation delay for CNT interconnects for lengths ranging from 500 to 2000 µm are found out. Results are compared for both numerical and PSO methods, and it is found that they are within 2% deviation. Although earlier work shows similar findings, we have used CNTFET(carbon nanotube field effect transistor)-based inverters as repeaters in CNT interconnects for the first time. We have carried out the analysis for two values of repeater size, i.e. h = 50 and 75.

Expansion of the Beamforming Coverage Area in an Elevation Plane for 60 GHz Band 3-D Beamforming

This letter proposes a novel antenna structure for 60 GHz band 3-D coverage beamforming. By using the proposed antenna structure, the coverage area can be expanded in an elevation plane. Dipole and patch subarray antennas were packaged into one structure by using the copper balls interconnection technique. A simple idea to utilize dipole and patch elements enables endfire and broadside radiations resulting in the coverage area expansion in the elevation plane. Two 2 × 4 array antennas were made up of eight multilayered substrate. Six metal layers were used for each multilayered substrate.

Failure Analysis of Aluminum Wire Bonds in Automotive Pressure Sensors in Thermal Shock Environments

Wire bonding remains one of the most widely adopted interconnection techniques in the field of electronic packaging. At present, the most effective way to ensure a long life and high reliability of wire bonds is to improve the bonding quality. In this study, both experiments and finite element analysis (FEA) were employed to develop a fundamental understanding of wire bond degradation. Sensors with two protective silicone gels were loaded with the same thermal shock at a temperature ranging from $- 40^{\circ }\text{C}$ to 125°C, and the switching time was shorter than 10 s. The number of thermal shock cycles for the aluminum wire covered with transparent silicone reached 1200, but the maximum number of cycles for the other wire only reached 454. The experimental results indicated that the chosen transparent silicone performed better than did the black silicone originally selected, which was also verified by the simulation results. In addition, bond pull and shear tests were performed. The results revealed no degradation of either the Ag-Al or Ni-Al bonding joints under thermal loading. In summary, the root cause of failure was found to be improper protection silicone application, which, as often ignored in analysis, accelerated thermal fatigue of the aluminum wires. An explanation of the observed trend and a recommended aluminum wire bonding method were also provided.

Electronic module assembly

Electronics is the vital basis for innovations and the essential enabler for global trends like connectivity, electro mobility and renewable energies. These applications require high performance and reliability of the electronic modules. Their assembly combines very heterogeneous process chains like remarkable productive and diminutive surface mount technology (SMT), powerful and robust power electronic interconnection techniques, as well as pioneering reel-to-reel based organic electronic printing. After briefly outlining the enormous global economic impact of electronic modules, this paper presents the state of the art of electronic module assembly including substrate materials, electronic components, packaging and assembly processes as well as quality and reliability testing methods.

(Invited) Electrodeposition for Die-to-Wafer Very High-Density Interconnect

Due to an increasing demand for high performance electronics, e.g. mobile, wearable, artificial intelligence for self-driving, heterogeneous 3D integration chips are highly desired since the integration scheme can be significantly outperforming a 2D integration chip. There are several 3D stacking integration methods to connect different components, such as wafer to wafer (W2W) bonding and die to wafer (D2W) bonding. W2W hybrid bonding offers a massive connection in a bonding, which decrease the processing cost in particular for small chips. However, there is a limitation that the die must be equal size for the pair wafer. Furthermore, no Known Good Die (KGD) selection is possible in W2W bonding, which can give a negative impact on stacking yield. On the other hand, D2W is able to handle different die sizes, which allow great flexibility in 3D integration. In addition, the capability to select the KGD ensures the yield. The most commonly used interconnection technique for D2W is solder base thermal compression bonding (TCB). However, there are several challenges in the stacking to achieve below 10 μm pitch. In addition, there is a certain limitation for scaling down below 5 μm of the bump pitches. In order to overcome the issue, implementation of hybrid Cu-Cu bonding technology is desired. In this presentation, the alternative scheme for solder base thermal compression bonding will be introduced, which enables us to achieve below 10 μm pitch by TCB. In particular, the challenge and solution regarding electrodeposition will be discussed. In addition, our integration approach for hybrid Cu-Cu D2W bonding will also be introduced.

A Fixed interconnection technique of photovoltaic modules using a sensorless approach for maximum power enhancement in solar plants

ABSTRACT The effect of partial shading results in increased mismatch losses and decreased power output of the solar Photovoltaic (PV) array, requiring reconfiguration of the shading pattern of the panels. Hence, various interconnection schemes and shade dispersing techniques are used to increase the power harnessed from the PV array. This paper proposes a simple offline shade dispersion in the entire PV array using a fixed reconfigured interconnection scheme. MATLAB/Simulations are carried out on a 6 × 6 PV array with fairly larger rating with different shading patterns and an experimental set up has also been developed with a 3 × 3 PV array with a much smaller rating in the laboratory for validating the reduction in mismatch loss and increased fill factor for different shading patterns. This technique can be used for both square and rectangular PV arrays. The proposed interconnection scheme has been compared with the Total Cross Tied (TCT) connection and shown that there is an enhancement of power generation, for about 16.66% in short-narrow shading pattern and a reduction in power loss of 66.66% in a short-wide pattern.

AC-coupled n-in-p pixel detectors on MCz silicon with atomic layer deposition (ALD) grown thin film

We report initial characterization of our novel sensor process solutions with AC-coupled n+/p−/p+ pixel detectors made on 150 mm diameter p-type Magnetic Czochralski silicon (MCz-Si) wafers. The pixels were segmented in a 52 × 80 dual column array and designed to be AC capacitive coupled. The resistive coupling between pixels, allowing quality assurance probing prior the flip chip bonding, was realized with thin film metal-nitride resistors fabricated by sputtering deposition. This approach allows us to omit punch-through resistor structures, which reduces the overall process complexity. Moreover, our previous studies have emphasized that applying ALD Aluminum Oxide (Al2O3) field insulator and passivation layer results in negative net oxide charge and thus additional p-spray or p-stop surface current termination structures are not necessary. Our focused application is a radiation-hard ALD AC-coupled pixel detector to be used in future particle physics experiments, such as the High-Luminosity Large Hadron Collider (HL-LHC), as well as photon counting applications. The pixel detectors were tested at Helsinki Institute of Physics (HIP) Detector laboratory and Ruđer Bošković Institute (RBI). We show measurement data of pixel detectors and other test structures. For the TiN resistors surrounding pixels, the resistance values were measured to be about 15kΩ. Data of electrical properties, full depletion voltage and leakage current are shown as well. Our Transient Current Technique (TCT) measurements indicated clear pixel segmentation with excellent homogeneity. For further study, AC-coupled sensors were hybridized to PSI46dig read out chips (ROC) by flip-chip interconnection technique and tested with a radioactive source.

Silicon pixel sensor R&D for the CLIC tracking detector

The physics aims at the proposed high-energy e^+e^− collider CLIC pose challenging demands on the performance of the detector system. Precise hit-time tagging, an excellent spatial resolutions, and a low mass are required for the vertex and tracking detectors. To meet these requirements, an all-silicon vertex and tracking detector system is foreseen, for which a broad R&D programme on a variety of novel silicon detector technologies is being pursued. For the ultra-low mass vertex detector, different hybrid technologies with innovative sensor concepts and interconnection techniques are explored. For the large-scale tracking detector, the focus of the R&D lies on monolithic HV-MAPS and HR-CMOS technologies. This contribution gives an overview of the ongoing activities with a focus on monolithic technologies for the CLIC tracking detector. Recent results from laboratory and test-beam measurement campaigns of the ATLASpix\\_Simple and the CLICTD sensor prototypes are presented.