(Invited) Electrodeposition for Die-to-Wafer Very High-Density Interconnect

Abstract

Due to an increasing demand for high performance electronics, e.g. mobile, wearable, artificial intelligence for self-driving, heterogeneous 3D integration chips are highly desired since the integration scheme can be significantly outperforming a 2D integration chip. There are several 3D stacking integration methods to connect different components, such as wafer to wafer (W2W) bonding and die to wafer (D2W) bonding. W2W hybrid bonding offers a massive connection in a bonding, which decrease the processing cost in particular for small chips. However, there is a limitation that the die must be equal size for the pair wafer. Furthermore, no Known Good Die (KGD) selection is possible in W2W bonding, which can give a negative impact on stacking yield. On the other hand, D2W is able to handle different die sizes, which allow great flexibility in 3D integration. In addition, the capability to select the KGD ensures the yield. The most commonly used interconnection technique for D2W is solder base thermal compression bonding (TCB). However, there are several challenges in the stacking to achieve below 10 μm pitch. In addition, there is a certain limitation for scaling down below 5 μm of the bump pitches. In order to overcome the issue, implementation of hybrid Cu-Cu bonding technology is desired. In this presentation, the alternative scheme for solder base thermal compression bonding will be introduced, which enables us to achieve below 10 μm pitch by TCB. In particular, the challenge and solution regarding electrodeposition will be discussed. In addition, our integration approach for hybrid Cu-Cu D2W bonding will also be introduced.