Interconnects In Integrated Circuits Research Articles

Computation of capacitance matrix for integrated circuit interconnects using semi-analytic Green's function method

In this paper a method for computing the capacitance matrix of a multiconductor interconnect line in a multilayered dielectric region is presented. The number of conductors and dielectric layers are arbitrary. The conductors are infinitesimally thin, and can be placed anywhere in the structure. The formulation is obtained by using a semi-analytic Green's function for multilayer structures, which is integrated to a series expansion, valid for uniform charge distribution on the conductors. In addition, the quasi-analytical evaluation of the entries of the Galerkin matrix leads to a very efficient and accurate computer code. Computed results are given for some cases of the integrated circuit interconnects to show the advantages and simplicity of our procedure as compared to the methods available in the literature.

Modeling early failure in integrated circuit interconnect

A model based on the random electron–atom scattering is developed to characterize the effects of defects and grain sizes on electromigration caused failure in confined sub-micron metal interconnect lines. Our study shows that lines at sub-micron widths with a more uniform microstructure exhibit a greater consistency in time to failure. Taking mean time to failure and dispersion in time to failure as criteria, the simulator predicts that grain sizes in the 0.03–0.05 μm range are optimal for 0.125 μm wide Al alloy lines. We also argue that the early failure mechanism associated with the missing metal defects is eliminated by using a homogeneous, fine-grained material. The uniformity of the structure results in a mono-modal failure distribution and contributes to increasing the built-in reliability of the interconnect lines.

Tomography of integrated circuit interconnect with an electromigration void

An integrated circuit interconnect was subject to accelerated-life test conditions to induce an electromigration void. The silicon substrate was removed, leaving only the interconnect test structure encased in silica. We imaged the sample with 1750 eV photons using the 2-ID-B scanning transmission x-ray microscope at the Advanced Photon Source, a third-generation synchrotron facility. Fourteen views through the sample were obtained over a 170° range of angles (with a 40° gap) about a single rotation axis. Two sampled regions were selected for three-dimensional reconstruction: one of the ragged end of a wire depleted by the void, the other of the adjacent interlevel connection (or “via”). We applied two reconstruction techniques: the simultaneous iterative reconstruction technique and a Bayesian reconstruction technique, the generalized Gaussian Markov random field method. The stated uncertainties are total, with one standard deviation, which resolved the sample to 200±70 and 140±30 nm, respectively. The tungsten via is distinguished from the aluminum wire by higher absorption. Within the void, the aluminum is entirely depleted from under the tungsten via. The reconstructed data show the applicability of this technique to three-dimensional imaging of buried defects in submicrometer structures relevant to the microelectronics industry.

A new method for measuring signal integrity in CMOS ICs

The aim of this paper is to present a new and original method for on‐chip measurements of very high frequency parasitic signals where a sampling circuit is directly included in the test chip. The paper describes the usefulness of this sensor for measuring signal propagation and cross‐talk glitch on integrated circuit interconnects and also gives the results obtained experimentally.

Capacitance extraction of integrated-circuit interconnects by matrix decomposition based on MEI concept

Recently, fast computational methods based on directly thinning the matrix of Method of Moment (MoM), have been introduced. In this paper, we propose a simply technique, based on the concept of Measured Equation of Invariance (MEI), to thin the MoM matrix numerically. This technique is referred to as Matrix Decomposition by MEI (MDMEI). A little effort is required to add the MDMEI to any of the variety of MoM programs for electromagnetic problems, such as the electrostatic problems, wire antennas, and two-dimensional (2-D) conducting object scattering. However, in this paper we only demonstrate how MDMEI is used in the capacitance extraction in integrated-circuit interconnects. The approach is verified by 2-D and 3-D examples with computing errors within 2–4%. For the present achievement, the sparsity rates of the resultant matrices in MDMEI depend on the problem to be solved. Further research is required to keep the bandwidths unchanged with object size increasing so that the sparsity rates of the MDMEI matrices are expected to improve.

IC test structures for multilayer interconnect stress determination

A new method for measuring strain in multilayer integrated circuit (IC) interconnects is presented. This method utilizes process compatible MEMS-based test structures and is applied to the determination of longitudinal interconnect stress in a standard dual-metal-layer CMOS process. Strain measurements are shown to be consistent for an array of similar test structures. Stress values, calculated from constitutive relations, are in good agreement with published results.

S-parameter-measurement-based high-speed signal transient characterization of VLSI interconnects on SiO/sub 2/-Si substrate

A new S-parameter-based signal transient characterization method for very large scale integrated (VLSI) interconnects is presented. The technique can provide very accurate signal integrity verification of an integrated circuit (IC) interconnect line since its S-parameters are composed of all the frequency-variant transmission line characteristics over a broad frequency band. In order to demonstrate the technique, test patterns are designed and fabricated by using a 0.35 /spl mu/m complementary metal-oxide-semiconductor (CMOS) process. The time-domain signal transient characteristics for the test patterns are then examined by using the S-parameters over a 50 MHz to 20 GHz frequency range. The signal delay and the waveform distortion presented in the interconnect lines based on the proposed method are compared with the existing interconnect models. Using the experimental characterizations of the test patterns, it is shown that the silicon substrate effect and frequency-variant transmission line characteristics of IC interconnects can be very crucial.

The excess noise in integrated circuit interconnects before and after electromigration damage

A detailed investigation is reported into the low frequency excess noise observed in metal films subjected to high unidirectional current densities. The resistance fluctuations due to the electromigration process are studied using three different methods; direct and alternating current probes and Fast Fourier Transform analysis of measured resistance changes with time. The noise observed in damaged and undamaged samples at low and high temperature are compared. It is concluded that 1/ f noise is observed in samples with little electromigration activity and 1/ f 2 noise is observed when electromigration is proceeding strongly. This latter noise can be a small and well behaved quasi-equilibrium process but in damaged samples it can be large due to discontinuous resistance changes. No significant change has been observed in the white noise in such samples.

Advanced silicon IC interconnect technology and design: present trends and RF wireless implications

Back-end-of-the-line (BEOL) trends in silicon integrated circuits (ICs) include fully planarized interconnect structures with six levels of nonlocal wiring, copper metallization for improved resistance and electromigration, dual damascene patterning for improved line definition and lower BEOL manufacturing cost, and low dielectric constant interlevel dielectrics for reduced line and coupling capacitance. Advanced IC design complexity is being alleviated by the use of intellectual property (IP) cores or macrocells, particularly for advanced application-specific ICs and system-on-a-chip (SOC) implementations. Virtual Design Environment software, developed for distributed design of advanced printed circuit board, will expand to the chip level as SOC designs incorporate IP cores and involve increasingly complex interconnect wiring design. These trends are summarized and synergistic front-end developments discussed and implications for RF wireless technologies are presented. A timetable for such technology and design trends is projected based upon the 1997 National Technology Roadmap for Semiconductors.

Tomographic reconstruction of an integrated circuit interconnect

An Al–W-silica integrated circuit interconnect sample was thinned to several μm and scanned across a 200 nm focal spot of a Fresnel zone plate operating at photon energy of 1573 eV. The experiment was performed on beamline 2-ID-B of the Advanced Photon Source, a third-generation synchrotron facility. Thirteen scanned projections of the sample were acquired over the angular range ±69.2°. At least 301×301 pixels were acquired at each angle with a step size of 77×57 nm. A three-dimensional image with an approximate uncertainty of 400 nm was reconstructed from projection data using a standard algorithm. The two layers of the integrated circuit and the presence of the focused ion beam markers on the surface of the sample are clearly shown in the reconstruction.

Identification of materials in integrated circuit interconnects using x-ray absorption near-edge spectroscopy

Most integrated circuit interconnects are principally composed of a few metals, including aluminum alloyed with copper, tungsten, titanium, Al3Ti, and Al2Cu, in a silica matrix. Integrated circuit interconnects have recently been proposed as a candidate system for visualization by computerized microtomography using absorption in the soft x-ray region. In this work, we demonstrate the feasibility of materials identification using volume-resolved x-ray absorption near edge spectra (XANES) obtained by tomographic reconstruction. A similar experiment could be performed with an energy-resolved high-voltage transmission electron microscope. We calculate the XANES for interconnect materials near the Al K edge, the Cu LI, LII, and LIII edges, and the Ti LII and LIII, and compare them to experiment when possible. The signal-to-noise ratio required to distinguish among the aluminum compounds from their Al K edge spectra is shown to be about one order of magnitude higher than that needed to detect elemental aluminum.

Computation of capacitance matrix for integrated circuit interconnects using on-surface MEI method

In this letter the capacitance matrix of integrated circuit interconnects has been successfully calculated by using the on-surface MEI (OSMEI) method. The OSMEI method uses the same mesh as the method of moments (MoM), but generates highly sparse matrixes. Thus, computation memory can be greatly reduced. The reason the sparse matrixes can be generated is that the local relationship between the potentials and charge densities on the mesh nodes can be numerically found by the MEI method. This approach is verified by two-dimensional (2-D) and three-dimensional (3-D) examples of the integrated circuit interconnects with errors within 2%-4%.

Electromigration testing of integrated circuit interconnections

The electromigration phenomenon has been one of the most intriguing physical problems in the semiconductor device reliability. The models to explain the phenomenon are here revised, together with the influence of materials and their microstructure. The various measuring techniques are described, including the design of special test patterns, and statistical data analysis is briefly reviewed.

Ionized physical vapor deposition of integrated circuit interconnects

Interconnects, once the technological backwater of integrated circuit technology, now dominate integrated circuit cost and performance. As much as 90 percent of the signal delay time in future integrated circuit designs will be due to the interconnection of semiconductor devices while the remaining 10 percent is due to transistor-related delay. This shifts the thrust of critical research toward an improved understanding of interconnect science and technology. Shrinking circuit geometries will require high aspect ratio (AR) vias to interconnect adjacent metal layers. By the year 2007 it is predicted that logic circuits will use 6 to 7 interconnected metal layers with via ARs of 5.2:1. Memory will need fewer layers, but ARs as high as 9:1. In this paper, the demands of interconnect technology will be reviewed and the opportunities for plasma-based deposition of vias will be discussed. One promising new method of fabricating high-aspect ratio vias is ionized physical vapor deposition (I-PVD). The technique economically creates a unidirectional flux of metal which is uniform over 200–300 mm diameter wafers. Since metal ejected by conventional sputtering is primarily neutral and exhibits a cosine angular velocity distribution, sputtered metal atoms do not reach the bottom of high AR vias. By sputtering these atoms into a moderate pressure (4 Pa), high-density Ar plasma, however, the metal atoms are first thermalized and then ionized. The ions are then readily collimated by the plasma sheath and directionally deposited into narrow, deep via structures. Experiments have consistently shown that over 80% of the metal species are ionized using I-PVD. The physical mechanisms responsible for ionization will be discussed from both an experimental and modeling perspective and the spatial variation of metal ionization is experimentally determined.

Noninvasive probing of high frequency signal in integrated circuits using electrostatic force microscope

We report a noninvasive high speed voltage sampling technique by using atomic force microscope. This technique is based on the mixing of interaction forces between a conductive probe-tip and a device interconnect line. Mixing phenomena allow measurements of signals with frequencies far above the mechanical resonance frequency of the cantilever. To increase the sensitivity and stability of the signal detection in ambient environment, we employed a delayed pulse sampling and lock-in amplifier detection of the small electrostatic force resulting from a high frequency signal on integrated circuits. The probing pulse is first modulated by a low frequency sinusoidal voltage using a double-balanced diode mixer. The junction between probe-tip and integrated circuit interconnection line works as the second mixer which mixes the probing voltage with the high speed waveform in the interconnection line. This technique can sense voltage signals even through a passivation layer of a 0.5 μm in thickness. We sampled an 8-bit vector signal repeating at 50 MHz through a passivation layer by using this technique.

Characterization of Al-1 wt% Y thin films for VLSI interconnects

The microstructure of an integrated circuit interconnect material significantly affects the reliability of the device. Narrow lines with near bamboo structure exhibit an increased mean time to failure (MTF) and a concomitant increase in the dispersion ( σ). A critical stress concentration site forms at the boundary between a single crystal segment and a polycrystalline segment of the line which leads to early failure. Simulation results for a 1000 μm long aluminum line (a rigidly confined line with blocked ends is assumed) show that, if the grains are uniform in size and small relative to the line width, a missing metal defect located at the center does not produce a stress concentration site. This paper reports on properties of Al-1 wt% Y films deposited by DC magnetron sputtering. The addition of yttrium reduces both the mean grain size (299 nm) of aluminum films and the standard deviation of the grain sizes (89 nm). As-deposited films consist of α-aluminum supersaturated with yttrium and Al 4Y phase. After annealing at 450°C for 30 min, β-Al 3Y is precipitated, grain growth is not significant and the electrical resistance drops from 6.05 to 2.95 μΩcm.

High-current failure model for VLSI interconnects under short-pulse stress conditions

Short-time high joule heating causing thermal breakdown of metal interconnects in ESD/EOS protection circuits and I/O buffers has become a reliability concern. Such failures occur frequently during testing for latchup robustness and during ESD/EOS type events. In this work, heating and failure of passivated TiN/AlCu/TiN integrated circuit interconnects in a quadruple level metallization system of a sub-0.5 μm CMOS technology has been characterized under high-current pulse conditions. A model incorporating the heating of the layered metal system and the oxide surrounding it has been developed which relates the maximum allowable current density to the pulse width. The model is shown to be in excellent agreement with experimental results and is applied to generate design guidelines for ESD/EOS and I/O buffer interconnects.

Void Nucleation on a Contaminated Patch

The energetics of a simple model of void nucleation on a contaminated patch between the sidewall and metal in an integrated circuit interconnect are examined to determine void nucleation behavior. The conditions under which there is no void nucleation barrier are represented by a simple relationship between the volume driving force, the equilibrium contact angle, the surface energy of the metal, and the contaminated patch radius. The void nucleation barrier, when it exists, is a strong function of these same parameters, and increases sharply as the driving force decreases, and under some conditions, increases with increasing equilibrium contact angle.

Z-Contrast Imaging of Grain-Boundary Core Structures in Semiconductors

Interest in semiconductor grain boundaries relates to the development of polycrystalline materials for photovoltaics and integrated-circuit interconnects. Although these structures are responsible for deleterious electrical effects, there are few experimental techniques available to study them at the required atomic scale. Therefore models of the physical processes occurring at grain boundaries have necessarily taken a macroscopic approach. Fortunately recent developments have resulted in tools that provide unprecedented glimpses into these interfaces and that will allow us to address anew the connection between grain-boundary structure and properties.Z-Contrast ImagingWhen exploring the unknown, we rely heavily on our eyes (incoherent imaging) to provide a direct image of a new object. In order to explore the unforeseen atomic configurations present at extended defects in materials, it again would be desirable if one could obtain a directly interpretable image of the unfamiliar structures present in the defect cores. Z-contrast electron microscopy provides such a view with both atomic resolution and compositional sensitivity.This high-resolution imaging technique differs from conventional high-resolution phase-contrast imaging. The phase-contrast technique produces a coherent image, an interference pattern formed by recombining the waves diffracted by the specimen. In the Z-contrast technique, the image is incoherent; it is essentially a map of the scattering power of the specimen. Additionally as was first determined by Lord Rayleigh, the incoherent mode of image formation has double the resolving power of the coherent mode.

Millimeter-wave monolithic integrated circuit interconnects using electromagnetic field coupling : IEEE Transactions on Components, Packaging and Manufacturing Technology—Part B, 1996, 19(2), 278

Millimeter-wave monolithic integrated circuit interconnects using electromagnetic field coupling : IEEE Transactions on Components, Packaging and Manufacturing Technology—Part B, 1996, 19(2), 278