Fabrication Of Interconnects Research Articles

Revealing the complexation of 3-N,N-dimethylaminodithiocarbamoyl-1-propanesulfonic acid (DPS) with cuprous ion and its contribution to Cu electrodeposition

An accelerator is an organic additive used in Cu electrodeposition, crucial for achieving superfilling during the fabrication of Cu interconnects in microelectronics. 3-N,N-dimethylaminodithiocarbamoyl-1-propanesulfonic acid (DPS) has been proposed and investigated as a substitute for SPS. However, its acceleration mechanism associated with its interaction with Cu ions has not been intensively investigated. In this study, the interaction between DPS and Cu+ was investigated using various spectroscopic analyses, including ultraviolet–visible–near-infrared absorption (UV–VIS–NIR), electron paramagnetic resonance (EPR), and nuclear magnetic resonance (NMR) spectroscopy. UV–VIS–NIR and EPR spectroscopy revealed that DPS forms a complex with Cu+, namely Cu(I)(DPS)2. The kinetic study on the complexation of DPS with Cu+ indicated second-order reaction characteristics. The structure of the complex was suggested using 1H and 13C NMR spectroscopy. Furthermore, electrochemical analyses, including cyclic voltammetry (CV) and linear sweep voltammetry (LSV), were conducted to investigate the electrochemical behaviors of the Cu(I)(DPS)2 complex, demonstrating its acceleration effect on Cu electrodeposition. These results will provide valuable insights for understanding the acceleration mechanism of DPS in Cu electrodeposition.

Nanoscale Wet Etching of Molybdenum Interconnects with Organic Solutions.

Molybdenum (Mo) has emerged as a promising material for advanced semiconductor devices, especially in the design and fabrication of interconnects requiring sub-10nm metal nanostructures. However, current wet etching methods for Mo using aqueous solutions struggle to achieve smooth etching profiles at such scales. To address this problem, we explore wet chemical etching of patterned Mo nanowires (NWs) using an organic solution: ceric ammonium nitrate (CAN) dissolved in acetonitrile (ACN). In this study, we demonstrate two distinct etching pathways by controlling the reaction temperature: i) digital cyclic scheme at room temperature, with a self-limiting Mo recess per cycle of ≈1.6nm, and ii) direct etching at elevated temperature (60°C), with a time-controlled Mo recess of ≈2nm min-1. These methods not only offer a highly controllable nanoscale Mo etching but also ensure smooth and uniform etching profiles independent of the crystal grain orientation of the metal.

Alkyl-terminated PEG suppressors for copper electroplating and their hydrophilic and hydrophobic properties

This study explores the structure-activity relationship of copper electroplating suppressors, with a focus on alkyl-terminated polyethylene glycols (PEGs), to better understand their efficacy in electronic interconnect fabrication. Electrochemical analysis demonstrated that an increase in the molecular weight of PEG suppressors significantly raises the electrochemical polarization overpotential during copper electrodeposition. Additionally, alkyl terminal capping was observed to amplify this polarization effect, with the extent of overpotential increase directly correlating with the alkyl chain length. However, the advantageous impact of molecular weight on overpotential diminishes at higher molecular weights. In contrast to the electrochemical results, through-hole electroplating experiments revealed that a suppressor with a molecular weight of 1 k and butyl termination exhibits superior through-hole throwing power. Further analysis indicated that a greater proportion of alkyl functional groups within the suppressor's molecular chain enhances uniform electroplating capabilities. The study also suggests that measuring contact angles, as an expression of hydrophobicity, could provide a more efficient and precise method for evaluating suppressor performance.

Freeform direct-write and rewritable photonic integrated circuits in phase-change thin films.

Photonic integrated circuits (PICs) with rapid prototyping and reprogramming capabilities promise revolutionary impacts on a plethora of photonic technologies. We report direct-write and rewritable photonic circuits on a low-loss phase-change material (PCM) thin film. Complete end-to-end PICs are directly laser-written in one step without additional fabrication processes, and any part of the circuit can be erased and rewritten, facilitating rapid design modification. We demonstrate the versatility of this technique for diverse applications, including an optical interconnect fabric for reconfigurable networking, a photonic crossbar array for optical computing, and a tunable optical filter for optical signal processing. By combining the programmability of the direct laser writing technique with PCM, our technique unlocks opportunities for programmable photonic networking, computing, and signal processing. Moreover, the rewritable photonic circuits enable rapid prototyping and testing in a convenient and cost-efficient manner, eliminate the need for nanofabrication facilities, and thus promote the proliferation of photonics research and education to a broader community.

(Invited) Electrochemical Deposition for Applications in the Semiconductor Industry

This year (2023) marks the 25th anniversary of the “Damascene copper electroplating for chip interconnections” publication by P.C. Andricacos et al [1] detailing the dual-damascene process and Cu superfilling of complex structures. And even though this was neither the only electrochemistry contribution to the semiconductor industry nor the first time to report successful plating of Cu structures, it signaled that electrochemical deposition would play prominent role in downscaling race [2]. The authors described Cu superfilling of a feature having characteristic dimensions of about 1 micron. Since then, electrochemists have focused intensely on electrolyte development, optimization of deposition parameters, and improvements in plating tools and process chambers, which went hand in hand with downscaling of features to be filled. Cu was plated on resistive substrates and alternative seeds, various surface pretreatments were applied, and nucleation and growth phenomena studied [3-6], until the focus shifted to alternative metals, such as Co [7]. While Chemical vapor deposition (CVD) and Atomic layer deposition (ALD) offer viable alternatives to electrochemical deposition (ECD) in fabrication of interconnects having width of several nanometers, new challenges and opportunities in 3D packaging and stacking appeared on the horizon. This field resembles more a ‘landscape’ than a ‘one-way street’ that damascene nano-interconnects were. While on one hand downscaling is gaining momentum here, too, there is also upscaling. For example, electrochemically deposited mega-pillars have diameters and heights exceeding hundreds of microns. More than a decade ago, a competitive race started between chemistry suppliers, tool manufacturers and scientists in the field to achieve bottom-up Cu fill of through-Si-vias (TSV) [8], structures meant to provide interconnections between vertically stacked integrated circuits. These structures had characteristic sizes an order of magnitude larger than the ones described in [1]. After demonstrating that superfilling of TSV was indeed possible, it became imperative to satisfy a plethora of production-line requirements, such as optimization of plating time or control of the so-called Cu pumping, a plastic deformation of Cu upon annealing. Plastic deformation leads to an uneven top surface and challenges in stacking layers on top of each other and is, therefore, undesirable. Today, researchers are contemplating possible benefits of the plastic deformation in Cu structures to establish a more robust and reliable Cu-to-Cu bonding process. Achieving defect-free fill of features was never the only requirement to be satisfied, but the ability to control plastic deformation in Cu features, or fabricate structures with specific texture, grain size, crystal structure [9, 10] on sub-micron scale, might require more thorough modifications of the current Cu plating processes. We will review this and other current trends in electrochemical deposition for applications in ‘classical’ semiconductor industry. We will also consider possibilities in technologies for Quantum computing, where a new spectrum of non-traditional candidate elements for plating could emerge [11, 12]. There, lessons learned from the downscaling of traditional interconnects could prove very useful.

Controlled and Uniform Wet Etching of Molybdenum Nanowires

We achieved the controlled recess of molybdenum (Mo), which is alternative interconnect material for copper (Cu), by wet chemical etching. This wet etching process includes two main steps which are chemical oxidation of Mo and its subsequent dissolution, respectively. Firstly, Mo nanowires (NWs) are uniformly oxidized with potassium permanganate (KMnO4) solution in acetone. Secondly, the Mo oxide is dissolved using an aqueous solution of HCl. Mo NWs are characterized through transmission electron microscopy (TEM) imaging after each of the above steps. Cyclic etching experiments including oxidation and dissolution of Mo showed that Mo recess is linear and can be controlled for each cycle, where the etching produced the smooth Mo surface. This controlled Mo recess is crucial for the fabrication of next-generation metal interconnects.

Graphene-Based Wireless Agile Interconnects for Massive Heterogeneous Multi-Chip Processors

The main design principles in computer architecture have recently shifted from a monolithic scaling-driven approach to the development of heterogeneous architectures that tightly co-integrate multiple specialized processor and memory chiplets. In such data-hungry multi-chip architectures, current Networksin- Package (NiPs) may not be enough to cater to their heterogeneous and fast-changing communication demands. This position paper makes the case for wireless in-package networking as the enabler of efficient and versatile wired-wireless interconnect fabrics for massive heterogeneous processors. To that end, the use of graphene-based antennas and transceivers with unique frequency-beam reconfigurability in the terahertz band is proposed. The feasibility of such a wireless vision and the main research challenges towards its realization are analyzed from the technological, communications, and computer architecture perspectives.

Machine Learning Enabled Solutions for Design and Optimization Challenges in Networks-on-Chip based Multi/Many-Core Architectures

Due to the advancement of transistor technology, a single chip processor can now have hundreds of cores. Network-on-Chip (NoC) has been the superior interconnect fabric for multi/many-core on-chip systems because of its scalability and parallelism. Due to the rise of dark silicon with the end of Dennard Scaling, it becomes essential to design energy efficient and high performance heterogeneous NoC-based multi/many-core architectures. Because of the large and complex design space, the solution space becomes difficult to explore within a reasonable time for optimal trade-offs of energy-performance-reliability. Furthermore, reactive resource management is not effective in preventing problems from happening in adaptive systems. Therefore, in this work, we explore machine learning techniques to design and configure the NoC resources based on the learning of the system and applications workloads. Machine learning can automatically learn from past experiences and guide the NoC intelligently to achieve its objective on performance, power, and reliability. We present the challenges of NoC design and resource management and propose a generalized machine learning framework to uncover near-optimal solutions quickly. We propose and implement a NoC design and optimization solution enabled by neural networks, using the generalized machine learning framework. Simulation results demonstrated that the proposed neural networks-based design and optimization solution improves performance by 15% and reduces energy consumption by 6% compared to an existing non-machine learning-based solution while the proposed solution improves NoC latency and throughput compared to two existing machine learning-based NoC optimization solutions. The challenges of machine learning technique adaptation in multi/many-core NoC have been presented to guide future research.

Design and Fabrication of Metallic-Conductive Polymer-Based Hybrid Film Interconnections for Stretchable Electronic Devices

Stretchable circuit is a technological innovation that has transformed the microelectronic landscape due to its enormous applications in the field of medicine. The consistency or durability of health monitoring devices can increase the dependability with which non-invasive clinical measures are collected. Metal–conductive polymer (CP) hybrid interconnects and metal–polyimide dual-layered interconnects were all produced as stretchable interconnections. Stretchable substrate for all of the interconnects was selected as soft elastomer polydimethylsiloxane (PDMS). However, the PDMS substrate presents challenges because it is temperature sensitive, limiting the process temperature. The extreme hydrophobic nature of the PDMS surface makes it difficult to deposit components that contain water and results in poor adhesion with different metals. Following the development of processes for fabricating materials on the PDMS substrate, methods for resolving these issues were investigated.

Ultrahigh breakdown current density of van der Waals one dimensional PdBr2

One-dimensional (1D) van der Waals (vdW) materials offer nearly defect-free strands as channel materials in the field-effect transistor devices and probably, a better interconnect than conventional copper with higher current density and resistance to electro-migration with sustainable down-scaling. We report a theoretically predicted halide based 1D few-chain atomic thread, PdBr2, isolable from its bulk which crystallizes in a monoclinic space group C2/c. Liquid phase exfoliated nanowires with mean length (20 ± 1)μm transferred onto a SiO2/Si wafer with a maximum aspect ratio (length:width) of ≈5000 confirm the lower cleavage energy perpendicular to the chain direction. Moreover, an isolated nanowire can also sustain a current density of 200 MA/cm2, which is atleast one-order higher than typical copper interconnects. However, local transport measurement via the conducting atomic force microscopy (CAFM) tip along the cross direction of the single chain records a much lower current density due to the anisotropic electronic band structure. While 1D nature of the nanoobject can be linked with a non-trivial collective quantum behavior, vdW nature could be beneficial for possible pathways in an interconnect fabrication strategy with better control of placement in an integrated circuit.

Optimization of TaSi<sub>2</sub> Processing for 500 °C Durable SiC JFET-R Integrated Circuits

Experiments are described towards optimizing tantalum silicide (TaSi2) interconnect metal film sputter-deposition and annealing in a manner compatible with the NASA Glenn two-layer interconnect silicon carbide (SiC) JFET-R IC process flow. Films deposited on 100 mm diameter wafers were investigated over a range of film thickness, sputter deposition, and post-deposition anneal conditions. An optimized process that achieved TaSi2 films free of cracking and morphological defects while nearly halving post-anneal stress was developed and will be used for completing the interconnect fabrication of prototype IC Gen. 12 SiC JFET-R ICs.

Plant communication among the Ralámuli people: Dreams, songs, iconography, and the interconnected fabric

AbstractThe northern Mexican Ralámuli people consider plants to be their kin. First‐ and secondhand ethnographies bring forth fundamental issues that convey the possibility of communicating with plants. For example, the notion of an interconnected world has to do with roots, with threads, and with thought or nátali (consciousness, remembrance, ancestral memory), all of which embrace the life path. This path also refers to that used by healers, who in their dreams and through their chants communicate with sacred plants. This article also deepens the understanding of textiles—originally made from vegetal fibers and considering that in Ralámuli origin stories the Earth was woven—and their iconography, which also appears in healing contexts, to see if there is a relationship between specific motifs and the information that, via dreams and chants, the plants are delivering.

Monolithic silicon photonic 32x32 thin-CLOS AWGR for all-to-all interconnections.

This paper reports the design, fabrication, and experimental demonstration of a monolithic silicon photonic (SiPh) 32×32 Thin-CLOS arrayed waveguide grating router (AWGR) for scalable SiPh all-to-all interconnection fabrics. The 32×32 Thin-CLOS makes use of four 16-port silicon nitride AWGRs, which are compactly integrated and interconnected by a multi-layer waveguide routing method. The fabricated Thin-CLOS has 4 dB insertion loss, < -15 dB adjacent channel crosstalk, and < -20 dB non-adjacent channel crosstalk. System experiments operated on the 32×32 SiPh Thin-CLOS demonstrate error-free communication at 25 Gb/s.

Structure Performance Correlation of N-Heterocyclic Oligomer Leveler for Acid Copper Plating of Advanced Interconnects

Levelers, as an essential part of organic additives in copper electroplating, play a crucial role in the fabrication of sophisticated interconnects in integrated circuits, packaging substrates, and printed circuit boards. In this work, four N-heterocyclic oligomers were synthesized and characterized, along with investigations of their electrochemical behaviors and their synergism with other bath components. The corresponding effects of the oligomers on the deposited copper films were analyzed by morphological and compositional characterizations. The leveling mechanism of the oligomers was further discussed with the aid of quantum chemical calculations. The results exhibit that each of these N-heterocyclic oligomers holds a particular degree of leveling ability. The oligomer of 1,3-bis(1-imidazolyl)propane and 1,3-dichloro-2-propanol (IPIEP) is the best leveler for THs plating compared with the other three oligomers. It was found that the hydroxyl group in IPIEP enhances the hydrophilicity of the modified molecule and triggers a more stable complexation between IPIEP and H2O-Cu(I)-MPS. Moreover, imidazole demonstrates a better practicality than piperazine. This work recommends the combination of N-heterocycles in planar conformation with modification by the hydroxyl group to synthesize high-performance straight-chain levelers.

A 16-nm 784-Core Digital Signal Processor Array, Assembled as a 2 × 2 Dielet With 10-μm Pitch Interdielet I/O for Runtime Multiprogram Reconfiguration

Modern applications require hardware accelerators to maintain energy efficiency while satisfying the increasing computation requirements. However, with evolving standards and rapidly changing algorithmic complexity as well as rising design costs at advanced technology nodes, the iterative development of inflexible accelerators for such applications becomes ineffective. The reconfigurable architectures can provide a higher throughput and the required flexibility, but with substantial energy and area efficiency overhead relative to the accelerators. We develop a domain-specific, energy- and area-efficient (within 2× - 10× of accelerators) multiprogram runtime reconfigurable accelerator called the universal digital signal processor (UDSP). The design maximizes generality and resource utilization for signal processing and linear algebra with minimal area and energy penalty. The statistics-driven multilayer network minimizes the network delay and consists of an optimized switchbox design that maximizes the connectivity per hardware cost. The multilayered interconnect network is linearly scalable with the number of processing elements and allows for intradielet and multidielet scaling. The network features’ deterministic routing and timing for fast program compile and its translation and rotation symmetries allow for hardware resource reallocation. Multidielet scaling is enabled by energy-efficient, high-bandwidth, and high-density interdielet communication channels that seamlessly extend the intradielet routing network across the dielet boundaries using 10- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> fine-pitch silicon interconnect fabric (Si-IF) interposer. A 2 × 2 multidielet UDSP on Si-IF can achieve a peak energy efficiency of 785 GMACs/J at 0.42 V and 315 MHz. The interdielet communication channel, SNR-10, provides a shoreline bandwidth density of 297 Gb/s/mm at 1.1 Gb/s/pin at 0.8 V and nominal energy efficiency of 0.38 pJ/bit.

Combined fluid flow simulation with electrochemical measurement for mechanism investigation of high-rate Cu pattern electroplating

BackgroundCu pattern electroplating plays an essential role in the interconnection and microstructure fabrication of high-power device packaging. However, improving efficiency while ensuring the preparation quality is an urgent breakthrough direction. MethodsA new electrolyte formula suitable for the high-rate Cu pattern electroplating was put forward, including 300 mg/L polyethylene glycol (PEG, molecular weight=8000) and 6 mg/L thiazolinyl polydipropyl sulfonate (SH110). The mechanism of high-rate Cu pattern electroplating was investigated by the combination of fluid flow simulation and the electrochemical measurements including galvanostatic measurements (GMs) and cyclic voltametric (CV) tests. The Cu pattern was electroplated in the Haring-Cell with air bubble as the forced convection method. Significant findingsThe simulation results indicate that the flow rate on the ring-shaped cathodic pattern surface gradually increases with the Cu growing up, which also increase from the pattern surface to the bulk electrolyte. The GMs results suggest that the cathodic polarization of the convection-dependent additives raises with the current density, which is strengthened by strong convection with current density lower than 6 ASD but have the opposite effect with current density larger than 8 ASD. The CV tests indicating that the aggregation of weak convection and strong polarization promote the antagonistic effect between thiolate of SH110 and PEG, the nucleation and the electroplating rate. Nevertheless, the synergistic effect of thiazoline of SH110 and PEG are enhanced with strong convection and weak polarization. The adsorption model during the Cu pattern electroplating process is established and verified by electroplating experiment with the optimum current density of 8 ASD. The Cu pattern is mirror bright with the high electroplating rate of over 90 μm/h.

Simulation and Experimental Study on Metal Microstructure of Meniscus‐Confined Electrodeposition

Meniscus‐confined electrodeposition (MCED), as one of the multifunctional additive manufacturing methods for microsensor manufacturing and flexible electrical interconnection, has great potential in future miniaturized communication devices. At present, however, the understanding of the multiphysical field processes involved in this method, such as electrodeposition, fluid dynamics, and mass and heat transfer, is limited, and the deposition forming process has not yet been well explained. Herein, the manufacturing process of metal microstructure used by MCED is studied, and the contour features of the microstructure are characterized. Simultaneously, based on the law of liquid phase mass transfer in microzone, the theoretical model of MCED process is established, the important role of Marangoni effect in evaporation process is revealed, and the effect of evaporation process on MCED is analyzed and discussed. Besides, the effect of evaporation process on the dynamic process of deposition is further proved by simulation analysis. The additive manufacturing equipment based on MCED is built to manufacture metal microstructure. Furthermore, the effects of evaporation on the morphology, roundness, vertical angle, and chemical composition of deposited metal microstructure are analyzed experimentally. These results provide a promising platform for the direct fabrication of nanocircuit interconnections, microsensors, and microantennas.

Reconfigurable Network-on-Chip based Convolutional Neural Network Accelerator

Convolutional Neural Networks (CNNs) have a wide range of applications due to their superior performance in image and pattern classification. However, the performance of CNNs comes at the price of high computational load and memory bandwidth usage. Hardware acceleration has become the primary way to tackle this ever-increasing complexity of CNNs. Most of the recent accelerators arrange processing units (PEs) as a many-core accelerator architecture, with the inter-PE connections tailored to the specific dataflow of the CNN layers. The performance of such accelerators is maximized if the input feature map and filter size/dimension matches that of the underlying accelerator. However, current fixed-size accelerator structures lead to sever resource underutilization because the same structure is used to compute CNN layers of varying dimensions. In this paper, we tackle this problem by presenting RC-CNN, a reconfigurable accelerator architecture for CNNs that can adapt the structure of accelerator to the size and dataflow pattern of the running CNN layer. RC-CNN relies on a reconfigurable on-chip interconnection fabric that can organize a sub-set of accelerator’s PEs as a PE set with the same size/dimension of the target CNN layer and customize the inter-PE connections for the layer’s dataflow pattern. Since the area/energy overhead does not justify using a full-fledged packet-switched network in accelerators with fine-grained PEs, we use a reconfigurable network with very simple switches in order to efficiently implement the dynamic reconfiguration capability for many-core fine-grained CNN accelerators. Experimental results show that, based on the CNN size and accelerator structure, RC-CNN yields 37% higher PE utilization over a baseline design, on average. It also improves the PE utilization of the state-of-the-art CNN accelerators we selected for comparison purpose by 18%, on average. The results show that these improvements translate to 9%–41% increase in the accelerator’s throughput. Further, RC-CNN reduces the network latency and energy consumption by 28% and 22%, respectively, compared to the state-of-the-art utilization-aware methods that employ packet-switched networks-on-chip.

Rapid photolithographic fabrication of high density optical interconnects using refractive index contrast polymers

We have developed new polymer optical interconnect materials that we term refractive index contrast (RIC) polymers that are ideally suited to a wide variety of photonic interconnect applications as the refractive index can be tuned over the range of n = 1.42 to 1.56, while index contrast Δn can be precisely tuned through composition and ultraviolet exposure; the waveguides can be directly patterned in dry films with no wet or dry etching processes required. RIC polymer interconnects thus have the ability to access numerous photonic platforms, including silicon photonic chips, ion-exchange (IOX) glass optical substrates, and optical fiber arrays. We demonstrate for the first time efficient single-mode polymer interconnect fabrication via a maskless lithography approach that exhibits low loss adiabatic coupling (∼1.5dB at 1550nm) to IOX waveguides through the formation of grayscale tapers.

Novel Additive Manufacturing-Enabled RF Devices for 5G/mmWave, IoT, Smart Skins, and Wireless Sensing Applications

The recent developments in mmWave and Internet of Things (IoT) technologies have dramatically increased the interest and demand for radio frequency (RF) devices that can be used for applications such as smart cities, energy harvesting, and ubiquitous wireless sensor networks. Additive manufacturing technologies (AMT) plays an important role to support these applications, as they allows to significantly reduce fabrication costs and times while enabling the achievement of devices with more complex geometries and the possibility of using a wide variety of materials. This publication reviews recent developments of state-of-the-art wireless devices including reconfigurable antennas, frequency-selective surfaces and highly scalable phased arrays enabled by AMT capabilities. It also discusses the benefits of AMT in the fabrication of interconnects that are suitable for packaging of fully-integrated antennas.