Inter-chip Interconnects Research Articles

A TensorFlow simulation framework for scientific computing of fluid flows on tensor processing units

A computational fluid dynamics (CFD) simulation framework for fluid-flow prediction is developed on the Tensor Processing Unit (TPU) platform. The TPU architecture is featured with accelerated dense matrix multiplication, large high bandwidth memory, and a fast inter-chip interconnect, making it attractive for high-performance scientific computing. The CFD framework solves the variable-density Navier-Stokes equation using a low-Mach approximation, and the governing equations are discretized by a finite-difference method on a collocated structured mesh. It uses the graph-based TensorFlow as the programming paradigm. The accuracy and performance of this framework is studied both numerically and analytically, specifically focusing on effects of TPU-native single precision floating point arithmetic. The algorithm and implementation are validated with canonical 2D and 3D Taylor-Green vortex simulations. To demonstrate the capability for simulating turbulent flows, simulations are conducted for two configurations, namely decaying homogeneous isotropic turbulence and a turbulent planar jet. Both simulations show good statistical agreement with reference solutions. The performance analysis shows a linear weak scaling and a superlinear strong scaling up to a full TPU v3 pod with 2048 cores.

Millimeter-Wave Dielectric Slab-Based Chip-to-Chip Interconnect Network Allowing for Relaxed Assembly Tolerances

An on-chip, low-loss, and wideband transition to dielectric slab waveguide is proposed in this article, for millimeter-wave interchip communication network applications. The transition design features a three-terminal circuit with one on-chip planar microstrip line and two off-chip dielectric slab-waveguide ports. It presents an add-drop attribute, which can be employed to realize the traditional bus and backbone network topologies. Prototypes presented operate on a thin-film layer imitating the back-end-of-line layers of a chip. Measurements are performed for an end-to-end connection and a hexagonal ring interconnect network at 170 and 100 GHz, respectively. In addition, the proposed transition is shown to enable an equal signal power distribution scheme in a linear array of receivers. To provide much needed relaxation against mechanical tolerances and thermal expansion effects in multiport circuits based on the ceramic dielectric waveguide, a novel low-loss and mechanically flexible connection between two dielectric slab waveguides is presented. The design of this connection, operating from 80 to 100 GHz, is verified by measurements. Technical merits, packaging attributes, and limitations of the proposed single hierarchy interchip interconnect network are discussed.

On the routing and scalability of MZI-based optical Beneš interconnects

Silicon Photonic interconnects are a promising technology for scaling computing systems into the exa-scale domain. However, there exist significant challenges in terms of optical losses and complexity. In this work, we evaluate the applicability of a thermally/electrically tuned Beneš network based on Mach–Zehnder Interferometers for on-chip and inter-chip interconnects as regards its scalability. We examine how insertion loss, laser power and switching energy consumption scale with the number of endpoints. In addition, we propose a set of hardware-inspired routing strategies that leverage the inherent asymmetry present in the switching components. We evaluate a range of network sizes, from 16 up to 256 endpoints, using 8 realistic and synthetic workloads and found very promising results. Our routing strategies offer a reduction in path-dependent insertion loss of up to 35% in the best case, as well as a laser power reduction of 31% for 32 endpoints. In addition, bit-switching energy is reduced by between 8% and 15% using the most efficient routing strategy, depending on the communication workload. We also show that workload execution time can be reduced with the best strategies by 5%–25% in some workloads, while the worst-case increases are at most 3%. Using our routing strategies, we show that under the examined technology parameters, a 32-endpoint interconnect can be considered for the NoC domain in terms of insertion loss and laser power, even when using conservative parameters for the modulator.

Energy-Efficient Time-Based Adaptive Encoding for Off-Chip Communication

The energy for data transfer has an increasing effect on the total system energy as technology scales, often overtaking computation energy. To reduce the power of interchip interconnects, an adaptive encoding scheme called adaptive word reordering (AWR) is proposed, which effectively decreases the number of signal transitions, leading to a significant power reduction. A novel circuit is implemented, which exploits the time domain to represent complex bit transition computations as delays and, thus, limits the power overhead due to encoding. The effectiveness of AWR is validated in terms of decrease in both bit transitions and power consumption. AWR is shown to yield higher power savings compared with three state-of-the-art techniques reaching 23% and 61% during the transfer of multiplexed address-data and image files, respectively, at just 1-mm wire length.

Energy Efficient Chip-to-Chip Wireless Interconnection for Heterogeneous Architectures

Heterogeneous multichip architectures have gained significant interest in high-performance computing clusters to cater to a wide range of applications. In particular, heterogeneous systems with multiple multicore CPUs, GPUs, and memory have become common to meet application requirements. The shared resources like interconnection network in such systems pose significant challenges due to the diverse traffic requirements of CPUs and GPUs. Especially, the performance and energy consumption of inter-chip communication have remained a major bottleneck due to limitations imposed by off-chip wired links. To overcome these challenges, we propose a wireless interconnection network to provide energy-efficient, high-performance communication in heterogeneous multi-chip systems. Interference-free communication between GPUs and memory modules is achieved through directional wireless links, while omnidirectional wireless interfaces connect cores in the CPUs with other components in the system. Besides providing low-energy, high-bandwidth inter-chip communication, the wireless interconnection scales efficiently with system size to provide high performance across multiple chips. The proposed inter-chip wireless interconnection is evaluated on two system sizes with multiple CPU and multiple GPU chips, along with main memory modules. On a system with 4 CPU and 4 GPU chips, application runtime is sped up by 3.94×, packet energy is reduced by 94.4%, and packet latency is reduced by 58.34% as compared to baseline system with wired inter-chip interconnection.

On Ev-Degree and Ve-Degree Topological Properties of Tickysim Spiking Neural Network.

Topological indices are indispensable tools for analyzing networks to understand the underlying topology of these networks. Spiking neural network architecture (SpiNNaker or TSNN) is a million-core calculating engine which aims at simulating the behavior of aggregates of up to a billion neurons in real time. Tickysim is a timing-based simulator of the interchip interconnection network of the SpiNNaker architecture. Tickysim spiking neural network is considered to be highly symmetrical network classes. Classical degree-based topological properties of Tickysim spiking neural network have been recently determined. Ev-degree and ve-degree concepts are two novel degrees recently defined in graph theory. Ev-degree and ve-degree topological indices have been defined as parallel to their corresponding counterparts. In this study, we investigate the ev-degree and ve-degree topological properties of Tickysim spiking neural network. These calculations give the information about the underlying topology of Tickysim spiking neural network.

On the Degree-Based Topological Indices of the Tickysim SpiNNaker Model

Tickysim is a clock tick-based simulator for the inter-chip interconnection network of the SpiNNaker architecture. Network devices such as arbiters, routers, and packet generators store, read, and write forward data through fixed-length FIFO buffers. At each clock tick, every component executes a “read” phase followed by a “write” phase. The structures of any finite graph which represents numerical quantities are known as topological indices. In this paper, we compute degree-based topological indices of the Tickysim SpiNNaker Model ( T S M ) sheet.

Simulation study of thermomechanical fatigue of quilt packaging interchip interconnects

Quilt Packaging QP is a new direct interchip interconnect through metal nodules on chip edges We have performed simulations to study the robustness of QP against fatigue failure For quilts on ceramic carriers thermal stresses are driven primarily by the adhesive between chip and carrier and we have simulated systems with different adhesives as well as different chip material combinations Simulations for the test system estimated cycles to failure over a temperature range of to C The simulation results suggest favorable material properties for solder and adhesive to use for QP or QP like interconnects

DaDianNao: A Neural Network Supercomputer

Many companies are deploying services largely based on machine-learning algorithms for sophisticated processing of large amounts of data, either for consumers or industry. The state-of-the-art and most popular such machine-learning algorithms are Convolutional and Deep Neural Networks (CNNs and DNNs), which are known to be computationally and memory intensive. A number of neural network accelerators have been recently proposed which can offer high computational capacity/area ratio, but which remain hampered by memory accesses. However, unlike the memory wall faced by processors on general-purpose workloads, the CNNs and DNNs memory footprint, while large, is not beyond the capability of the on-chip storage of a multi-chip system. This property, combined with the CNN/DNN algorithmic characteristics, can lead to high internal bandwidth and low external communications, which can in turn enable high-degree parallelism at a reasonable area cost. In this article, we introduce a custom multi-chip machine-learning architecture along those lines, and evaluate performance by integrating electrical and optical inter-chip interconnects separately. We show that, on a subset of the largest known neural network layers, it is possible to achieve a speedup of $656.63 \times$ over a GPU, and reduce the energy by $184.05 \times$ on average for a 64-chip system. We implement the node down to the place and route at 28 nm, containing a combination of custom storage and computational units, with electrical inter-chip interconnects.

Wireless Interconnect in Multilayer Chip-Area-Networks for Future Multimaterial High-Speed Systems Design

Wireless chip area network which enables wireless communication among chips fosters development in wireless communication and it is envisioned that future hardware system and developmental functionality will require multimaterial. However, the traditional system architecture is limited by channel bandwidth-limited interfaces, throughput, delay, and power consumption and as a result limits the efficiency and system performance. Wireless interconnect has been proposed to overcome scalability and performance limitations of multihop wired architectures. Characterization and modeling of channel become more important for specification of choice of modulation or demodulation techniques, channel bandwidths, and other mitigation techniques for channel distortion and interference such as equalization. This paper presents an analytical channel model for characterization, modeling, and analysis of wireless chip-to-chip or interchip interconnects in wireless chip area network with a particular focus on large-scale analysis. The proposed model accounts for both static and dynamic channel losses/attenuation in high-speed systems. Simulation and evaluation of the model with experimental data conducted in a computer desktop casing depict that proposed model matched measurement data very closely. The transmission of EM waves via a medium introduces molecular absorption due to various molecules within the material substance. This model is a representative of channel loss profile in wireless chip-area-network communication and good for future electronic circuits and high-speed systems design.

Enabling inter- and intra-chip optical wireless interconnect by the aid of hybrid plasmonic leaky-wave optical antennas

In this paper, we propose a new method to provide optical link in Photonic Integrated Circuits (PICs). The proposed method uses two hybrid plasmonic leaky-wave optical antennas, operating at the standard optical telecommunication wavelength of 1.55μm, to provide inter-chip interconnect between two layers in a photonic chip and also intra-chip interconnect between two different photonic ICs. Linearly tapered couplers are designed to couple the optical signal from the silicon waveguide to the hybrid plasmonic antennas. The performance of the proposed optical link is verified using numerical full wave simulation. The proposed structure is planar, and can be fabricated using standard CMOS technology which makes it the superior candidate for realization of future multi-layered Photonic Integrated Circuits.

8 × 8 × 40 Gbps fully integrated silicon photonic network on chip

We demonstrate a fully integrated photonic network-on-chip circuit with wavelength division multiplexing transceivers on silicon. The total transmission capacity is up to 8×8×40 Gbps for intra- and inter-chip interconnections.

Improve Chip Pin Performance Using Optical Interconnects

With the fast development of processor chips, power-efficient, high-bandwidth, and low-latency interchip interconnects become more and more important. Studies show that the bandwidth of traditional parallel interconnects with low I/O clock frequencies will become bottlenecks in the near future. To solve this problem, two types of high-bandwidth interchip interconnects are developed. Low-swing differential electrical interconnects have widely been used in high-speed I/O designs. On the other hand, optical interconnects promise high bandwidth, low latency, and could improve the chip pin performance for manycore processors. They are becoming potential alternatives for electrical interconnects. This paper systematically models these two types of interconnects in terms of crosstalk noises, attenuation, and receiver sensitivities. Based on the proposed models, we developed optical and electrical interfaces and links (OEIL) and an analysis tool for OEIL. The OEIL can be used to analyze the energy consumption, bandwidth density, and latency of interconnects. Analytical models are verified by the results of published experiments. It shows that the optical interconnects have much higher bandwidth densities than the electrical interconnects. With this feature, the optical interconnects can significantly reduce I/O pin count compared with the electrical interconnects. For example, they can save at least 92% signal pins when connecting chips more than 25 cm (10 in) apart. The energy consumption of optical interconnects is comparable with that of electrical interconnects, and the latency of polymer waveguide-based optical interconnects is 18% less than that of electrical interconnect.

Optical Characteristics of a Multichannel Hybrid Integrated Light Source for Ultra-High-Bandwidth Optical Interconnections

The optical characteristics of a multi-channel hybrid integrated light source were described for an optical interconnection with a bandwidth of over 10 Tbit/s. The power uniformity of the relative intensity of a 1000-channel light source was shown, and the minimum standard deviation s of the optical power of the 200 output ports at each 25-channel laser diode (LD) array was estimated to be 0.49 dB. This hybrid integrated light source is expected to be easily adaptable to a photonics-electronics convergence system for ultra-high-bandwidth interchip interconnections.

A High-Linearity, 30 GS/s Track-and-Hold Amplifier and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process

A high-speed, track-and-hold amplifier and interleaved CMOS sample-and-hold circuit are implemented in an InP-on-CMOS fabrication process. Conventional 50- $\Omega $ interchip interconnects between III-V and CMOS circuits are eliminated with heterogeneous integration of III-V on CMOS, yielding higher performance circuits at lower power consumption. The track-and-hold amplifier is based on a double-switching feedback architecture using 250 nm InP HBTs and achieves an IIP3 of 19 dBm at a sampling rate of 30 GS/s. To the author's knowledge, this is the first published result of a high-speed track-and-hold amplifier in an InP BiCMOS process and the first implementation of a feedback linearized track-and-hold at a sampling rate above 2 GS/s. Additionally, a novel HBT buffer with feedback is demonstrated to offer high linearity and low power for driving time-interleaved CMOS sample-and-hold circuits. A 90 nm time-interleaved CMOS sample-and-hold circuit is demonstrated to achieve better than $-$ 53 dBc ${\rm HD}_3$ at a sampling rate of 5 GS/s while consuming roughly 24 mW per channel.

Thermal Cycling Study of Quilt Packaging

The continued progress of micro-electronics often requires functionality that is spread across multiple chips. This need has led to the development of a variety of alternative chip-packaging technologies that offer increased speed and bandwidth, with lower losses, in an increasing number of interchip interconnects. One recent alternative is quilt packaging® (QP), which has already shown promise from a performance perspective. The geometry of QP is essentially lateral: large numbers of ultrawide-bandwidth interchip interconnects (superconnects) are made directly by nodules fabricated along the edges of adjacent chips. Metallurgical bonding of the nodules creates a system in the form of a “quilt” of separately manufactured chips. This new interconnect geometry is subject to stresses that are different from more conventional schemes. For example, the thermal stress that causes fatigue and lead to failure in ball grid arrays is essentially shear stress, whereas the most critical stresses in QP are tensile and compressive. This paper describes studies of fatigue failure in QP, with attention to critical high-stress regions previously identified by finite-element modeling. Nodules were fabricated on silicon chips, and both single and quilted chips were thermally cycled up to 1000 times over a range of − 55 °C to 125 °C. Scanning electron microscopy (SEM) was used to detect mechanical failure. Focused-ion-beam cross-sectioning was used to expose the critical interior interfaces of QP structures for SEM examination. QP superconnects were found to be robust under all the test conditions evaluated.

Manufacturing technology of intra- and interchip interconnects for modern ULSIs: Review and concepts of development

Technological operations involved in manufacturing multilevel ULSI interconnections by the dual damascene (DD) method have been analyzed. Problem issues are considered, including (i) etching of porous intralevel insulation with ultralow values of dielectric constant, (ii) application of metal barrier and seed layers onto the porous surface of etched dielectric spacers, in which copper conductors have to be formed, (iii) low mechanical strength of porous dielectric spacers between copper conductors, (iv) insufficient stability of copper conductors with respect to failures as a result of electromigration, and (v) rapid growth in the resistivity of copper conductors with decreasing width, and limited possibility of compensating this factor by increasing conductor height (thickness). Possible approaches to solving these problems are proposed. According to one of these, horizontal copper conductors are formed first and then a porous dielectric is incorporated into the gaps between conductors by the method of chemical sol-gel deposition from solution by spin-on-dielectric (SOD) method on a centrifuge. The horizontal conductors can then be formed by the standard single-damascene process of copper deposition into temporal mask that is subsequently removed and replaced by the porous dielectric. According to another method, copper conductors are formed by local electrochemical deposition on the wafer surface that is preliminary covered by the barrier layer (BL), seed layer (SL), and a temporal mask, in which a pattern of conductors is prepared by etching down to the SL surface. In this case, the deposited copper conductors initially possess a textured crystalline structure, which facilitates the formation of elongated crystallites during subsequent thermal recrystallization. The surface of conductors can be also covered by local electrochemical process with an electroless barrier layer (e.g., of CoWP). Then, the BL and SL are removed and a porous ultralow-dielectric-constant insulator is incorporated into the gaps between copper conductors. The next stage of forming interconnections in multicrystal ULSIs consists of a three-dimensional (3D) vertical assembly of thinned chips by connecting them with copper conductors formed using through substrate via (TSV) technology. In order to improve heat removal from the assembly and increase its mechanical strength, the filling of vertical through channels in chips by copper is supplemented by copper plating of side edges and the formation of microbumps on crystal surfaces.

Bufferless Routing in Optical Gaussian Macrochip Interconnect

The ever increasing intra-chip and inter-chip traffic load in computing systems has been pushing traditional electronic interconnects to their limit in communication bandwidth, latency, and energy consumption. In order to achieve the high bandwidth and low latency required by intra-chip and inter-chip communications and mitigate the high interconnect power dissipation, optical interconnects have been considered as a promising candidate for intra-chip and inter-chip interconnections in next generation computing systems. In addition, packet switching is an efficient switching paradigm to fully utilize the communication bandwidth. However, due to lack of random access optical memory, it is challenging to implement all-optical packet switching in optical interconnects. In this paper, we exploit bufferless routing, a special type of packet-switching, to overcome the problem of lack of random access optical buffer. More specifically, we study bufferless routing in a novel optical multichip system, called Gaussian macrochip, where embedded chips are interconnected by an optical Gaussian network. By taking advantage of the underlying Hamiltonian cycles in the Gaussian network, we design a bufferless routing algorithm for the Gaussian macrochip, which routes packets along the shortest path in the absence of deflection, and guarantees that deflected packets reach their destinations within ${{N}}$ hops. Our extensive simulation results demonstrate that by adopting the proposed routing algorithm, Gaussian macrochip can support much higher inter-chip communication bandwidth, has much shorter average packet delay, and is more power efficient than the previously proposed architectures for optical multichip systems.

Exploration of Electrical and Novel Optical Chip-to-Chip Interconnects

Off-chip interconnect is often a bottleneck due to its limited number of pins and bandwidth. The authors present an optical orbital angular momentum (OAM)-based wireless interchip interconnect and compare it with traditional electrical and optical interconnect alternatives.

Athermal silicon optical interposers with quantum dot lasers operating from 25 to 125°C

Interposers for inter-chip interconnects should perform stably under high-temperature conditions and rapid temperature change due to the heat generated by mounted large-scale integration (LSI) chips. Athermal silicon optical interposers integrated with quantum dot lasers and other temperature-insensitive components on a single silicon substrate are demonstrated, and error-free data links at 12.5 Gbit/s operating from 25 to 125°C are achieved without any bias adjustment. Since maximum junction temperatures in most LSIs have been below 125°C now and will be in the future, the interposers are tolerant of heat generated by LSIs, and are suitable for inter-chip interconnects.