A High-Linearity, 30 GS/s Track-and-Hold Amplifier and Time Interleaved Sample-and-Hold in an InP-on-CMOS Process

Abstract

A high-speed, track-and-hold amplifier and interleaved CMOS sample-and-hold circuit are implemented in an InP-on-CMOS fabrication process. Conventional 50- $\Omega $ interchip interconnects between III-V and CMOS circuits are eliminated with heterogeneous integration of III-V on CMOS, yielding higher performance circuits at lower power consumption. The track-and-hold amplifier is based on a double-switching feedback architecture using 250 nm InP HBTs and achieves an IIP3 of 19 dBm at a sampling rate of 30 GS/s. To the author's knowledge, this is the first published result of a high-speed track-and-hold amplifier in an InP BiCMOS process and the first implementation of a feedback linearized track-and-hold at a sampling rate above 2 GS/s. Additionally, a novel HBT buffer with feedback is demonstrated to offer high linearity and low power for driving time-interleaved CMOS sample-and-hold circuits. A 90 nm time-interleaved CMOS sample-and-hold circuit is demonstrated to achieve better than $-$ 53 dBc ${\rm HD}_3$ at a sampling rate of 5 GS/s while consuming roughly 24 mW per channel.