Interstage Matching Research Articles

An active two-stage class-J power amplifier design for smart grid’s 5G wireless networks

<span>The wireless communication networks in the smart grid’s advanced metering infrastructure (AMI) applications need 5G technology to support large data transmission efficiently. As the 5G wireless communication network’s overall bandwidth (BW) and efficiency depend on its power amplifier (PA), in this work, a two-stage class-J power amplifier’s design methodology that operates at 3.5 GHz centre frequency by utilizing the CGH40010F model gallium nitride (GaN) transistor is presented. The proposed design methodology involves proper designing of input, output, and interstage matching networks to achieve class-J operation with improved power gain over desired BW using the advanced design system (ADS) electronic design automation (EDA) tool and estimating its integration feasibility through active element-based design approach using the Mentor Graphics EDA tool. The proposed PA provides 54% drain efficiency (D.E), 53% power added efficiency (PAE) with a small signal gain of 27 dB at 3.5 GHz and 41 dBm power output with 21 dB of improved power gain across a BW of around 400 MHz using 28 V power supply into 50 Ω load. By replacing the two-stage PA's passive elements with active elements, its layout size is estimated to be (15.5×29.2) μm2 . The results of the proposed PA exhibit its integration feasibility and suitability for the smart grid’s 5G wireless networks.</span>

A 23–29 GHz GaN Low-Noise Amplifier with Drain-to-Source Coupling Feedback

In this paper, a four-stage gallium nitride (GaN) low noise amplifier (LNA) using coupled-line (CL) feedback in a 0.15-μm GaN-on-SiC process is proposed. The electromagnetic coupling feedback between the drain and source of each transistor is employed to generate an additional signal path for neutralization, which enhances gain and improves stability performance. A series transmission line-capacitor-transmission line (TL-C-TL) network is introduced between stages of the LNA for wider band interstage matching. The measured results show that the designed LNA achieves a 3-dB bandwidth of 23.6 to 29.8 GHz, a peak gain of 23.7 dB at 25.8 GHz, and a minimum noise figure (NF) of 2.2 dB at 27.8 GHz. The output-referred 1-dB compression point (OP1dB) is 13 dBm. The total power consumption of the LNA is 200 mW.

A 2–36 GHz CMOS LNA with π-Network-Based wideband interstage matching technique for software-defined radio systems

With the advance in wireless communication, next-generation software-defined radio (SDR) systems require transceivers to operate in both sub-6GHz and millimeter-wave (mmWave) band and support multiple standards. However, bridging sub-6GHz frequencies with millimeter-wave bands exceeding 30 GHz remains a challenge for conventional wideband LNAs. To surmount this, a 2–36 GHz CMOS low-noise amplifier (LNA) designed for SDR systems is introduced in this paper. An innovative wideband input matching network capable of spanning both frequency domains is proposed. The methodology effectively mitigates the impact of vast parasitic capacitances, achieving wideband input matching against Electrostatic Discharge (ESD) and on-chip decoupling capacitor parasitic. In addition, a π-network-based wideband interstage matching technique is adopted to extend bandwidth of gain. A tri-stage prototype of the proposed LNA, designed using a 40-nm CMOS process, is designed to validate our design strategies. The post-simulation outcomes reveal a peak gain of 14 dB with a -3dB bandwidth ranging from 2 to 36 GHz, equating to a fractional bandwidth of 178 %. The Noise Figure (NF) is commendably uniform across the frequency spectrum, stabilizing at 5 dB. Furthermore, the third-order input intercept point (IIP3) is −4.2dBm to -3dBm across the bandwidth. The performance is achieved with a power of 19.4 mW and within a core area of 0.1 mm2.

An integrated LNA‐phase shifter in 65 nm CMOS for Ka‐band phased‐array receivers

SummaryIn this paper, a vector‐sum phase shifter (VSPS) integrated with a wideband high‐gain low‐noise amplifier (LNA) for Ka‐band phased‐array receivers is presented. The digitally controlled VSPS based on the RF phase shifting architecture consists of a modified I/Q signal generator with additional inductor resonance and a programmable variable gain amplifier (VGA) based on Four 3 × 4 transistor arrays. Besides the reduced parasitic effect of the I/Q signal generator, an Equidistant Contraction Technology (ECT) is used in the VGA, to maintain higher phase shift accuracy of the VSPS. A multistage LNA with series inductor peaking is adopted to fulfill the flat wideband gain, where LC resonance networks are used as interstage matching to compensate for gain roll‐off at a higher frequency. Based on simulations in 65 nm CMOS technology, the presented LNA‐Phase shifter has achieved an average NF of 3.24–3.66 dB, and an average gain of 13.1–23.6 dB. Moreover, an RMS phase error of 1.1–12.6°, an RMS gain error of 4.2–5.6 dB, and an RMS magnitude error of 2.1–2.8 dB are maintained across 27–40 GHz, with a 360° phase shift coverage in steps of approximately 2.8125°. The chip consumes 16.83 mW from a 1.2 V supply voltage, and the occupied area is 0.65 mm2.

A Ku-Band CMOS Balanced Driver Amplifier With Transformer-Based Notch Filter for SATCOM Phased Arrays

This brief presents a Ku-band balanced driver amplifier (BDA) for SATCOM phased arrays. To facilitate a flexible and low-loss coupler design, the non-correlation between the coupling coefficient and the output power of BDA is illustrated. The passive transformer-based notch filter is co-optimized with the inter-stage matching network. The sideband rejection is improved while maintaining high gain and linearity. The second harmonic trap technique is also applied to alleviate the amplitude-to-phase (AM-PM) distortion. Fabricated in 65-nm CMOS technology, the proposed BDA provides the maximal gain of 26 dB at 14 GHz with the highest sideband rejection of 26 dB. The input and output return losses are both better than -15 dB. It achieves a measured 1-dB compressed power (P1dB) of 19.5 dBm with the maximal power-added efficiency (PAEmax) of 27.8%. The small-signal gain and P1dB vary only 2 dB and 0.8 dBm from -55∘C to 85∘C, respectively.

A 32-GHz Eight-Way Power Amplifier MMIC in 150 nm GaN HEMT Technology

This paper presents a 32 GHz high-power amplifier (HPA) with a design strategy to achieve high-power output with reliable operation for Ka-band deep space satellite communication in 150 nm GaN HEMT technology. The presented Ka-band HPA employs a cascaded two-stage common source amplifier topology, and the output stage comprises an eight-way power combining network in the current mode. The interstage matching network is designed with the bandpass configuration utilizing capacitors and transmission lines to provide better stability at the low-frequency regime. The implemented Ka-band HPA achieved a power gain of 7.3 dB at the input level with the maximum PAE at 32 GHz, and the 3 dB gain bandwidth was 3.5 GHz (31.3~34.8 GHz). The saturated output power at the peak power-added efficiency (PAE) of 19.3% was 38.2 dBm, and the output 1 dB gain compression point (OP1 dB) was 27.4 dBm in the measurement. The designed HPA consumes an area of 19.35 mm2 including RF pads and DC pads.

A 0.38 V Fully Differential K-Band LNA with Transformer-Based Matching Networks

The implementation of a 0.38 V K-band low-power fully differential low-noise amplifier (LNA) in a 45 nm silicon-on-insulator (SOI) process is presented. The proposed architecture employs a two-stage approach with transformer-based interstage matching networks to minimize circuit area. The proposed LNA covers the frequency range from 20.3 to 24.1 GHz, it achieves a noise figure (NF) as low as 2.2 dB, and a gain of 12.9 dB, with a power consumption of 11.7 mW from a 0.38 V DC supply in a very compact area (0.15 mm2) excluding pads. Non-linearity simulations show the proposed circuit achieves a Po1dB of −7.3 dBm, and an OIP3 (Output Third Order Intercept) of 7 dBm. The transformers allow improved area use since they are simultaneously used as matching networks, RF chokes to bias the active devices, baluns at the input and output terminals to convert the single-ended signal into differential mode, and vice versa, and facilitates the interconnection with the upcoming stages. We used a state-of-the-art tool that generates the desired inductances to perform impedance matching for a given frequency and coupling factor value. A comparison with similar works proves the proposed LNA achieves a very low NF and the lowest power consumption reported in a differential circuit.

A two-way three-stage W-band power amplifier with series-parallel inductor-based T-type inter-stage matching network

A two-way three-stage W-band power amplifier (PA) in 65 nm CMOS SOI process (Ft/Fmax: 120 GHz/220 GHz) is presented in this paper. A differential cascode structure with a series-parallel inductor-based T-type inter-stage matching network is proposed to improve efficiency and power gain near three quarters of Ft. A high passive efficiency transformer-based two-way parallel power combining output matching network is implemented to increase the output power and achieve compact layout. The proposed W-band PA achieves a post-layout simulated 22.1-dB small-signal power gain (S21) and 7.2-GHz 3-dB bandwidth from 90.9 to 98.1 GHz. The post-layout simulated large-signal performances of the PA shows it achieves 17.11 dBm saturated output power (Psat), 13.68 dBm output 1-dB compression point (OP1dB) and 11.15% peak power-added efficiency (PAE) at 94.5 GHz.

Design of a broadband GaN 12 W power amplifier

AbstractA compact broadband 12 W power amplifier with broadband matching networks is presented. Transistors connected in parallel are used to synthesize the high power. Input, interstage, and output matching networks are also properly designed to meet the requirement of the broadband application. The broadband high power amplifier (HPA) was fabricated using a 0.15‐μm gallium nitride (GaN) HEMT technology, with a maximum saturated measured output power of 43 dBm from 6 to 18 GHz. The measured power added efficiency exceeds 20% in the whole interested band. The proposed HPA also has a compact size of 3.1 mm × 2.96 mm.

A 2–10-GHz Reconfigurable GaN Power Amplifier With Average Power-Added Efficiency of 30% and Output Power of 2 W

In this brief, a 2–10 GHz reconfigurable power amplifier (PA) with power-added efficiency (PAE) of 30% and output power of 2W is proposed using commercial <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.25~\mathbf {\mu }\text{m}$ </tex-math></inline-formula> GaN technology. It consists of two-stage amplifier transistors with reconfigurable input, inter-stage and output matching networks. By utilizing the reconfigurable matching networks, the proposed PA circuit divides the frequency band of 2–10 GHz into three continuous sub-frequency bands, and achieves high power added efficiency and gain in each sub-frequency band. As a result, the proposed PA can simultaneously maintain high efficiency and high gain and cover multioctave bandwidth. Moreover, in order to further improve the efficiency, harmonic suppression is used in low-band with open circuit impedance at third harmonic. With these techniques, the proposed PA covers frequency band of 2–10 GHz, delivers an average PAE of 38% at 2–5 GHz, 31% at 5–7 GHz, and 31.5% at 7–10 GHz. Good agreement between simulation and measurement is obtained.

Design of a Low Cost X-Band LNA with Sub-1-dB NF for SATCOM Applications

In this article, we demonstrate a low-cost 7.25-7.75 GHz two-stage low noise amplifier with sub-1-dB noise figure for satellite communication applications. The microstrip technology on Rogers RT5880 substrate with the dielectric constant of 2.2 and thickness of 0.508 mm were utilized to develop a low noise amplifier. The printed-circuit-board technology offers a variety of profits such as being low-cost, lighter-weight and re-configurability after the manufacturing process make this technology charming for satellite communication systems for both commercial and military applications. Since the monolithic microwave integrate circuit technology provide much smaller sized circuits and high electrical performance especially at the millimeter-wave frequencies, the printed microstrip technology can be a significant rival to integrated-circuit technology with its proven reliability, easier, cheaper and faster manufacturing process, compactible electrical performance in X-band applications. Moreover, the proposed amplifier was developed with utilizing California Eastern Laboratories’ CE3512K2 transistor on Rogers-RT5880 and surface mount devices were utilized in the matching networks to reduce the size. In addition, the source-generation and interstage matching topologies were implemented to simplify the matching complexity to enhance the noise and gain. The prototype was manufactured with utilizing LPKF prototyping machine. The developed LNA exhibits a measured gain of 23.5±0.5 dB with the noise figure of less than 0.9 dB and input/output return loss better than 11.5 dB in the operating frequency bandwidth. Furthermore, the developed amplifier has a measured carrier to interference of -59 dBc and P1dB of 13 dBm at the center frequency while consuming a total DC power of 50 mW.

A 60-GHz Variable-Gain Phase Shifter With an Active RL Poly-Phase Filter

A 60-GHz variable-gain phase shifter consisting of an active I/Q generator and Gilbert-cell-based summing amplifier fabricated in a 65-nm bulk CMOS process is presented here. The proposed I/Q signal generator is implemented by inserting an RL poly-phase filter into the interstage node of a cascode amplifier, which provides good interstage matching and results in a finite gain in the I/Q generator. It also provides good isolation characteristics between the I/Q generator and the subsequent vector-summing amplifier due to the common gate buffer stages. Therefore, it minimizes the rms gain and phase errors of the phase shifter by maintaining accurate I/Q signals regardless of the input impedance of the vector-summing amplifier, which varies with the gain and phase states. The vector-summing amplifier is operated by a current-steering digital to analog converter (DAC) to keep the total dc current constant regardless of the gain and phase states, which makes the output return loss constant. The DAC makes the vector-summing amplifier generate an arbitrary vector by determining the sizes of the I and Q vectors, and the double pole, double throw (DPDT) switch determines the quadrants. The rms gain and phase errors of the proposed variable-gain phase shifter show the values of 0.13 dB and 0.36°, respectively, at 60 GHz with 4-bit gain control in a 20-dB dynamic range and 5-bit phase control at 360°. In the 3-dB frequency range of 56.8–64.1 GHz, the rms gain and phase error outcomes are 0.26 dB and 1.44°, respectively. The chip area and overall power consumption are measured and found to be 0.55 mm2 and 14.52 mW, respectively.

A 35 dBm PSAT and 41% PAE GaAs Power Amplifier With Series Distributed-Balun

This brief presents a high-power Sub-6 GHz two-way differential power amplifier (PA) with a series distributed-balun output network in <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.5{\mu }\text{m}$ </tex-math></inline-formula> GaAs pHEMT process. The proposed series distributed-balun output network consists of two coupled-line-based distributed-baluns connected in series to achieve low-loss matching and power combining. The general three-port distributed-balun unit and its extended two-way series distributed-balun have been theoretically analyzed in detail. In addition, the multi-layer transformer structure is introduced to enhance the coupling factor of the inter-stage matching network. The measurement results of this three-stage PA demonstrate a peak gain of 32.6dB, with 3-dB bandwidth (BW−3dB) of 4.2-6 GHz. The saturated output power (Psat) is 34–35 dBm covers 4.8-6 GHz, and the peak power-added efficiency (PAE) is 41%. The measured root mean square error vector magnitude (EVMrms) with 160MHz of 64-QAM/256-QAM is 2.4%/1.93% with 28.7/26.5 dBm average output power (Pave) and −36.8/−38.7 dBc adjacent channel leakage ratio (ACLR) without digital pre-distortion (DPD).

A Frequency Quadrupler in 130-nm SiGe With Stack Multiport-Driven Matching Achieving 37.4% Instantaneous Bandwidth

In this letter, a wideband and high harmonic rejection frequency quadrupler, which consists of a two-stage push–push pair frequency doubler, is demonstrated in a 130-nm SiGe technology. A novel stack multiport-driven matching (SMDM) technology is employed in inter-stage matching to address the limited bandwidth, providing a more efficient method to match the dual-tank networks to 50 <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\Omega $ </tex-math></inline-formula> . The SMDM also provides dc pass-through with the common-base (CB) amplifier, thereby increasing the conversion gain (CG). Additionally, the undesired harmonics are suppressed by the dual-tank networks loaded on the collector of the two-stage doubler. The measured results show that the 3-dB bandwidth of the output power is about 6.8 GHz from 14.8 to 21.6 GHz, that is, 37.4%. The worst-case harmonic rejection ratios (HRRs) are 22.1 dBc at the second-order harmonic, 44.4 dBc at the fundamental harmonic, and 35.7 dBc at the third-order harmonic with input power 2 dBm over the entire operating bandwidth, respectively. The frequency quadrupler occupies an area of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$0.83\times0.5$ </tex-math></inline-formula> mm2.

An X-Band High-Accuracy GaAs Multifunction Chip With Amplitude and Phase Control

This paper presents a high-accuracy multifunction chip (MFC) with amplitude and phase control in X-band. The MFC is designed with a common leg structure and incorporates a 6-bit attenuator (ATT), a 6-bit phase shifter (PS), two gain compensation amplifiers (GCAs), three single pole double throw switches (SPDTs), and fourteen logic control circuits. The interstage matching networks (IMNs) are inserted to compensate for the insertion phase and attenuation changes from the design due to the mismatches occurring when cascading the separately designed PS and ATT blocks. The receive and transmit modes switching is achieved by using four SPDTs. In addition, the resistance feedback is used in GCAs to compensate for passive losses and provide gain to the MFC. The proposed MFC is fabricated in 0.15- <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\mu \text{m}$ </tex-math></inline-formula> GaAs pseudomorphic high-electron-mobility transistor (pHEMT) process. In the range of 8–11 GHz, the measured maximum root-mean-square (RMS) amplitude error of the MFC is less than 0.28 dB, and the maximum RMS phase error is less than 3.3°. Moreover, the MFC is achieved with a size of 4.3 mm <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\times2.85$ </tex-math></inline-formula> mm. Excellent performance and compact size make the MFC great potential in spaceborne phased array applications.

DC-10 GHz broadband linear power amplifier for 5G applications using 180 nm CMOS technology

This article suggests a broadband linear power amplifier (PA) for DC-10 GHz for Fifth-generation (5G) and multi-standard applications using 180 nm CMOS technology. The suggested radio frequency power amplifier is appropriate for wideband LTE, IoT, WSN, multi-standard, and 5G radio frequency transmitters. T-coil peaking and bridged-shunt-series peaking amplifiers are used for bandwidth extension and gain flatness. Also, the interstage matching inductors between common source and common gate transistors are applied to improve radio frequency achievement. The suggested PA consists of four stages as follows; input stage, two stages using the T-coil peaking technique, and the last stage utilizing bridged-shunt-series peaking topology. The input stage is a complementary current reuse (CCR) common gate with active shunt feedback (SFB) architecture. It is utilized to extend the matching of RF input impedance with agreeable linearity and power gain at little power consumption. The second stage works in class-C operation to enhance the efficiency and reduce DC power consumed whereas the class-AB mode is utilized in the third and fourth stages to improve the output power. The suggested PA obtains a peak constant power equal to 14.25 dBm, a maximum Power-Added-Efficiency (PAE) of 16 %, and a peak gain equal to 22 dB. The proposed power amplifier dissipates a DC power of 80 mW. The die size of the proposed power amplifier equals 1mm2, whereas the total chip size includes the pads is 1.62mm2.

A 32–40 GHz 7-bit Bi-Directional Phase Shifter With 0.36 dB/1.6° RMS Magnitude/Phase Errors for Phased Array Systems

This paper presents a digitally programmable bi-directional 7-bit passive phase shifter in a 65 nm CMOS technology. The core of this passive vector-synthesized phase shifter is a hybrid quadrature generator (HQG), an interstage matching network, and a passive vector modulator (PVM). This work proposes a high coupling-factor-based quadrature generator design methodology and demonstrates it with a compact vertical transformer. The interstage matching network between HQG and PVM is proposed to release the bandwidth bottleneck and achieve a 34% fractional frequency bandwidth. Two 6-bit X-type attenuators in the I and Q path form a high-resolution 12-bit controlling word. In 32–40 GHz, this 7-bit 360° phase shifter achieves a measured 2.8° step with 0.45-1.6° RMS phase error and 0.2-0.36 dB RMS magnitude error. With the broadband technique, its 3-dB bandwidth reaches 30.2-42.7 GHz with a 2.8° RMS phase error. Its in-band 1-dB compression point is 10.2 dBm. With the proposed compact HQG and PVM, this mm-wave passive phase shifter only occupies <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$220\times 630\,\,\mu \text{m}^{2}$ </tex-math></inline-formula> and has no power consumption.

A 18–44 GHz Low Noise Amplifier With Input Matching and Bandwidth Extension Techniques

This letter presents a low noise amplifier (LNA) with a 3-dB gain bandwidth (3-dB BW) of 18–44 GHz in 65-nm CMOS technology. By deriving an analytical equation of input impedance, a co-design methodology for the first two stages of LNA that can simultaneously achieve broadband input matching and low noise figure (NF) is implemented. Weakly coupled asymmetric transformers that introduce a section of reverse parallel winding in the primary coil are designed to realize broadband interstage matching, optimize the gain flatness and boost the transconductance. The proposed LNA achieves a measured peak gain of 19.5 dB with a fractional 3-dB gain bandwidth (FBW) of 83.8%, covering the whole <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$K$ </tex-math></inline-formula> -band and <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$Ka$ </tex-math></inline-formula> -band. The measured NF is 2.6–3.5 dB from 20 to 43 GHz. To the best of our knowledge, the proposed LNA achieves the highest 3-dB BW and FBW with competitive NF. The measured input 1-dB gain compression point ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$\text {IP}_{\mathrm {1\,dB}}$ </tex-math></inline-formula> ) ranges from −23 to −18.5 dBm over the entire 3-dB gain bandwidth.

Design and Analysis of a 26–34.5-GHz Power Amplifier With Balanced Mismatch Reduction and Interstage Matching

This letter presents a 26–34.5-GHz power amplifier (PA) fabricated in 65-nm bulk CMOS with a core area of 0.338 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . To reduce the mismatch in the conversion between single-ended and differential signals, the symmetry of the baluns is analyzed in detail. To achieve a broadband operation, a wideband source impedance matching network is introduced. The measured small signal gain is 25.1 dB, and the proposed PA achieves 21.6-dBm saturated output power ( <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {sat}}$ </tex-math></inline-formula> ) with 30.4% peak power-added efficiency (PAE) as well as OP <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> of 20.4 dBm with 29.4% PAE at 29 GHz. The 1-dB bandwidth of <inline-formula xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink"> <tex-math notation="LaTeX">$P_{\mathrm {sat}}$ </tex-math></inline-formula> is from 26 to 34.5 GHz.

Review of Efficiency CMOS Class AB Power Amplifier Topology in Gigahertz Frequencies

This paper reviewed the efficiency of CMOS class AB power amplifier topology especially in gigahertz frequencies. CMOS class AB power amplifier is a compromise between class A and class B in terms of linearity and efficiency between 50% to 78.5%. However, CMOS class AB power amplifier cannot have good linearity and efficiency simultaneously due to the breakdown in gate-oxide voltage and effects from hot carrier. The breakdown of oxide prevents optimum drain signal and the effect from hot carrier will reduce the quality of the overall PA design. Several works from year 1999 to 2019 with different topology such as multiple gated transistor, cascode, feedforward linearization, differential circuit, transformer combining method with common source harmonic termination and combination of a dual-switching transistor with a third harmonic tuning technique are discussed and the performances of the power amplifier are compared. The best three CMOS class AB power amplifier topologies were chosen in terms of high efficiency. The topologies are two stages with integrated input and interstage matching, Doherty amplifier combined with drain modulation based architectures and self-biased cascode topology that obtained power added efficiency of 45%, 43% and 42%, respectively. Key performance indicators for class AB power amplifier include frequency, power added efficiency, gain and output power are also discussed in this paper.