Interstage Matching Research Articles

A D-Band Cascode Amplifier With 24.3 dB Gain and 7.7 dBm Output Power in 0.13 $\mu$m SiGe BiCMOS Technology

This letter describes a D-band 3-stage cascode amplifier developed using the IHP 0.13 μm SiGe BiCMOS technology. The amplifier is implemented with low-loss transformer for inter-stage matching and single-to-differential transformation. The large-signal characteristics of the cascode HBT configuration are used to optimize the bias condition for highest output power and gain performance. A measured amplifier achieves a peak power gain of 24.3 dB, with a 3 dB bandwidth of 20 GHz centered at 130 GHz. The amplifier exhibits a saturated output power of 7.7 dBm and an output 1 dB gain compression point of 6 dBm with a power consumption of 84 mW. The measured noise figure is 6.8 dB at 130 GHz and stays under 8 dB over the 3 dB bandwidth. To the best of our knowledge, the proposed amplifier exhibits the highest gain and output power among the silicon-based D-band amplifiers reported so far.

A High Gain and High Efficiency Cmos Driver Amplifier for 3.5 Ghz WiMAX Applications

A two-stage 0.18μ m CMOS driver amplifier (DA) for WiMAX 3.3 to 3.8 GHz using common source (CS) inductive degeneration is presented in this paper. The first-stage is a modified cascode amplifier with inter-stage inductor matching while the later stage is a conventional CS amplifier. On-wafer measurement shows an average voltage gain of 26.3 dB with 3 dB bandwidth of 0.8 GHz, an output 1 dB compression (P 1 dB) of 12.2 dBm and a power added efficiency (PAE) of 45% at 3.5 GHz while consuming 25 mW from a 1.8 V supply. At 3.5 GHz, the input and output of the proposed amplifier are matched closely to 50 with input and output return losses of –22.9 dB and –24.3 dB respectively. At P 1 dB, it achieved an output third order intercept point (OIP3) of 19.8 dBm. Measurement results obtained in this work could be used as a reference design for immediate drive amplifier implementations in commercial mobile or portable WiMAX transmitter or signal generator.

A merged LNA and mixer with improved noise figure and gain for software defined radio applications

This letter presents a new architecture of merged low noise amplifier and mixer, which employs a noise cancellation scheme and uses an inductor as an inter-stage matching network between LNA and mixer to absorb parasitic capacitances. As the parasitic capacitances degrade the gain and noise figure of the entire circuit, using an inductor in the inter-stage can very effectively improve both noise figure and gain of the circuit. Based on this new method, a merged LNA-mixer has been designed in a 0.18-µm RF CMOS technology. Simulation results show 4-dB increase in power conversion gain and 1.7-dB improvement in noise figure in comparison with the case without inter-stage filter. This circuit draws only 5mA from a 1.8V supply and covers the frequency range of 1.3GHz to 4.1GHz. Its large bandwidth as well as low power consumption makes it suitable for rapidly growing software defined radio RF transceivers.

<i>A Brief Review</i>: Stage-Convertible Power Amplifier Using Differential Line Inductor

In this review article, a stage-convertible RF power amplifier designed with a 0.18-μm RF CMOS process is described. A method to implement a low-power matching network is an essential technology for the stage-convertible power amplifier. Various low-power matching networks with distributed active transformers as an output power combiner are compared in terms of the amounts of undesired coupling, the chip size, and the amount of power loss. The feasibility of a differential line inductor for the stage-convertible power amplifier is assessed and explained. Finally, we show that the differential line inductor is a realistic means of reducing the overall chip size, enhancing the quality factor of the matching network, and minimizing the undesired coupling between the inter-stage matching network and any output matching network. Additionally, the operating mechanism of the stage-convertible power amplifier using the differential line inductor for a low-power matching network is described in detail.

52–75 GHz wideband low-noise amplifier in 90 nm CMOS technology

A three-stage single-ended low-noise amplifier covering almost the entire V-band is presented. The design employs three cascade single-ended stages with pi-sections for wideband interstage matching and source degeneration at the first stage. The amplifier achieves a peak gain of 14 dB and minimum noise figure of 4.8 dB. A record 3 dB bandwidth of 37 is achieved with power consumption of 32 mW and core silicon area of 0.065 mm 2 in 90 nm CMOS technology.

Design of Wideband LNAs Using Parallel-to-Series Resonant Matching Network Between Common-Gate and Common-Source Stages

A method is proposed to design wideband low-noise amplifiers (LNAs) made of cascaded common-gate (CG) and common-source (CS) stages with a parallel-to-series resonant interstage matching network. The first CG stage has a dual-band response, and the second CS stage has higher gain between these two bands. By applying the proposed interstage matching technique, conjugate matching is achieved at high and low bands, while the midband loss is compensated by the second stage. The output network of the first stage and the input network of the second stage resonate at the same frequency. Two wideband LNAs are designed based on this method and implemented in 0.18- μm RF-mixed signal CMOS process. The first LNA operates at 3.1-10.3 GHz, having 9.6-12.71 dB of power gain and 2.5-3.9 dB of noise figure (NF) at the power consumption of 13.4 mW. The second LNA operates at 14.3-29.3 GHz, having 8.25 ± 1.65 dB of power gain and 4.3-5.8 dB of NF at the power consumption of 13.9 mW.

CMOS DSB Transmitter With Low TX Noise for UHF RFID Reader System-on-Chip

This paper presents a new design for a CMOS double-sideband (DSB) RF transmitter (TX) integrated circuit (IC) for UHF RF indentification (RFID) reader system-on-chip. Due to the strong demand for high linearity, low TX noise, and low cost, a CMOS passive up-conversion mixer with an adaptive bias circuit is proposed. High linearity of the passive mixer can be maintained over a wide range of dc levels from the dc-coupled IF signals using the proposed adaptive biasing circuit. A linear two-stage CMOS power amplifier (PA) follows the up-conversion mixer so that the overall third-order output intercept point (OIP3) of the two-stage PA is improved by the optimized design of the first stage in its biasing condition, the cell size, and due to inter-stage matching. The designed TX IC is fabricated using a 0.18-μm standard CMOS process and the implemented passive mixer exhibits a low double-sideband noise figure (DSB NF) of 4 dB and a high OIP3 of 13.3 dBm. The implemented PA exhibits a high-output 1-dB compression point (OP1dB) of 18 dBm, and a clear sweet spot in OIP3 of as high as 36.8 dBm at the two-tone average output power of 10 dBm. The implemented overall TX IC has a size of 960 × 670 × μm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> and the overall circuit performed with a gain of 17.8 dB, a high OP1dB of 17.6 dBm, an OIP3 of 28 dBm, and has a low DSB NF of 11.2 dB while consuming a biasing current of 58 mA from a 3.3-V supply. The proposed design also satisfies the spectral mask of the RFID standard for an output power of up to 18 dBm for the double-sideband amplitude shift-keying signals.

A 3.3 V 72.2 Mbit/s 802.11n WLAN transformer-based power amplifier in 65 nm CMOS

This paper describes the design of a power amplifier (PA) for 802.11n WLAN fabricated in 65 nm CMOS technology. The PA utilizes 3.3 V thick gate oxide (5.2 nm) transistors and a two-stage differential configuration with integrated transformers for input and interstage matching. A methodology used to extract the layout parasitics from electromagnetic (EM) simulations is described. For a 72.2 Mbit/s, 64-QAM, 802.11n OFDM signal at an average and peak output power of 11.6 and 19.6 dBm, respectively, the measured EVM is 3.8%. The PA meets the spectral mask up to an average output power of 17 dBm.

A fully integrated CMOS power amplifier with a half‐turn transformer for IEEE 802.11a WLAN applications

AbstractA fully integrated CMOS power amplifier for 5 GHz WLAN applications is implemented using 0.18 μm CMOS technology. An on‐chip transmission‐line transformer is used for output matching and voltage combining. An input balun, interstage matching components, an output transmission‐line transformer, and RF chokes are fully integrated in the amplifier, and thus no external components are required. The power amplifier occupies a total area of 1.7 mm × 1.2 mm. At a 3.3 V supply voltage, the amplifier exhibits a 22.6 dBm output 1 dB compression point, 23.8 dBm saturated output power, and 25 dB power gain. The power added efficiency (PAE) is 21% at maximum, 19% at P1dB. When a 54 Mbps/64 QAM OFDM signal is applied, the PA delivers an average power of 12 dBm at an EVM of −25 dB. © 2009 Wiley Periodicals, Inc. Microwave Opt Technol Lett 51: 2551–2553, 2009; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.24683

A 40-GHz Low-Noise Amplifier With a Positive-Feedback Network in 0.18-$\mu{\hbox{m}}$ CMOS

A novel circuit topology for a CMOS millimeter-wave low-noise amplifier (LNA) is presented in this paper. By adopting a positive-feedback network at the common-gate transistor of the input cascode stage, the small-signal gain can be effectively boosted, facilitating circuit operations at the higher frequency bands. In addition, <i xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">LC</i> ladders are utilized as the inter-stage matching for the cascaded amplifiers such that an enhanced bandwidth can be achieved. Using a standard 0.18-mum CMOS process, the proposed LNA is implemented for demonstration. At the center frequency of 40 GHz, the fabricated circuit exhibits a gain of 15 dB and a noise figure of 7.5 dB, while the return losses are better than 10 dB within the 3-dB bandwidth of 4 GHz. Operated at a 1.8-V supply, the LNA consumes a dc power of 36 mW.

An RF power amplifier with inter-metal-shuffled capacitor for inter-stage matching in a digital CMOS process

One challenge of the implementation of fully-integrated RF power amplifiers into a deep submicro digital CMOS process is that no capacitor is available, especially no high density capacitor. To address this problem, a two-stage class-AB power amplifier with inter-stage matching realized by an inter-metal coupling capacitor is designed in a 180-nm digital CMOS process. This paper compares three structures of inter-metal coupling capacitors with metal-insulator-metal (MIM) capacitor regarding their capacitor density. Detailed simulations are carried out for the leakage, the voltage dependency, the temperature dependency, and the quality factor between an inter-metal shuffled (IMS) capacitor and an MIM capacitor. Finally, an IMS capacitor is chosen to perform the inter-stage matching. The techniques are validated via the design and implement of a two-stage class-AB RF power amplifier for an UHF RFID application. The PA occupies 370 × 200 μm2 without pads in the 180-nm digital CMOS process and outputs 21.1 dBm with 40% drain efficiency and 28.1 dB power gain at 915 MHz from a single 3.3 V power supply.

A $K$-Band CMOS Distributed Doubler With Current-Reuse Technique

A K-band distributed frequency doubler is developed in 0.18 mum CMOS technology. This doubler combines the distributed topology for broadband characteristics and current-reuse technique to improve the conversion gain. The high-pass drain line and high-pass inter-stage matching network are used to obtain a good fundamental rejection. A measured conversion gain of better than -12.3 -dB is obtained, and the fundamental rejection is better than 30 dB for the output frequency between 18 and 26 GHz. The dc power consumption is 10.5 mW with a chip size of 0.55 times 0.5 mm2.

DESIGN OF 3 TO 5 GHZ CMOS LOW NOISE AMPLIFIER FOR ULTRA-WIDEBAND (UWB) SYSTEM

A single-stage ultra-wideband (UWB) CMOS low noise amplifler (LNA) employing interstage matching inductor on conven- tional cascode inductive source degeneration structure is presented in this paper. The proposed LNA is implemented in 0.18m CMOS technology for a 3 to 5GHz ultra-wideband system. By careful op- timization, an interstage inductor can increase the overall broadband gain while maintaining a low level of noise flgure of an amplifler. The fabricated prototype has a measured power gain of +12.7dB, input return loss of 18dB, output return loss of 3dB, reverse isolation of 35dB, noise flgure of 4.5dB and input IP3 of i1dBm at 4GHz, while consuming 17mW of DC dissipation at a 1.8V supply voltage.

Direct conversion RF front-end with a low-power consumption technique for 2.4 GHz ISM band

The implementation and performance measurements of RF front-end are presented. The low-power RF front-end designed in TSMC 0.18 µm process for 2.4 GHz ISM band direct conversion is presented. The proposed RF front-end is comprised of the folded mixer, fully differential low-noise amplifier (LNA) and interstage matching network. Gilbert-cell mixers using the folded technique and current reused LNA are designed for low power consumption. The folded mixers are implemented by using PMOS devices in the switching stage of mixers with a resonating inductor for low flicker noise. The proposed RF front-end consumes 7.2 mW from the 1.2 V supply and a conversion gain of 23 dB is achieved. The third-order intercept point (IIP3) is −10.5 dBm, and the proposed RF front-end has good linearity. By using PMOS devices and the folded technique, low flicker noise of 10 dB at 10 kHz is achieved, and thus the proposed RF front-end can be used in the direct conversion receiver for narrow bandwidth.

Development of Integrated Broad-Band CMOS Low-Noise Amplifiers

This paper presents a systematic design methodology for broad-band CMOS low-noise amplifiers (LNAs). The feedback technique is proposed to attain a better design tradeoff between gain and noise. The network synthesis is adopted for the implementation of broad-band matching networks. The sloped interstage matching is used for gain compensation. A fully integrated ultra-wide-band 0.18-mum CMOS LNA is developed following the design methodology. The measured noise figure is lower than 3.8 dB from 3 to 7.5 GHz, resulting in the excellent average noise figure of 3.48 dB. Operated on a 1.8-V supply, the LNA delivers 19.1-dB power gain and dissipates 32 mW of power. The gain-bandwidth product of the UWB LNA reaches 358 GHz, the record number for the 0.18-m CMOS broad-band amplifiers. The total chip size of the CMOS UWB LNA is 1.37 times 1.19 mm2.

A Fully Integrated 5-GHz CMOS Power Amplifier for IEEE 802.11a WLAN Applications

A fully integrated 5-㎓ CMOS power amplifier for IEEE 802.11a WLAN applications is implemented using 0.18-㎛ CMOS technology. An on-chip transmission-line transformer is used for output matching network and voltage combining. Input balun, inter-stage matching components, output transmission line transformer and RF chokes are fully integrated in the designed amplifier so that no external components are required. The power amplifier occupies a total area of 1.7㎜ × 1.2㎜. At a 3.3-V supply voltage, the amplifier exhibits a 22.6-㏈m output 1-㏈ compression point, 23.8-㏈m saturated output power, 25-㏈ power gain. The measured power added efficiency (PAE) is 20.1% at max. peak, 18.8% at P1㏈. When 54 Mbps/64 QAM OFDM signal is applied, the PA delivers 12㏈m of average power at the EVM of -25㏈.

4-GHz Inter-Stage-Matched SiGe HBT LNA with Gain Enhancement and No Noise Figure Degradation

An effective way to boost power gain without noise figure degradation in a cascode low noise amplifier (LNA) is demonstrated at 4 GHz using 0.35 μm SiGe HBT technology. This approach maintains the same current consumption because a low-pass π-type LC matching network is inserted in the inter-stage of a conventional cascode LNA. 5 dB gain enhancement with no noise figure degradation at 4 GHz is observed in the SiGe HBT LNA with inter-stage matching.

A 6.5-kV ESD-protected 3-5-GHz ultra-wideband BiCMOS low-noise amplifier using interstage gain roll-off compensation

Design and validation of an electrostatic discharge (ESD)-protected ultra-wideband low-noise amplifier (LNA) is presented in this paper. It features an interstage matching network for gain roll-off compensation to achieve a flat gain over its passband. Evaluated with a chip-on-board approach, the amplifier demonstrates a gain of 11.8 /spl plusmn/ 0.3 dB, minimum noise figure of 2.1 dB, and a group delay variation of /spl plusmn/30 ps from 3 to 5 GHz, even though it uses a less advanced 0.35-/spl mu/m BiCMOS technology. The LNA is protected against human body model ESD stress up to 6.5 kV. The measured input third-order intercept point at 4.5 GHz is -5.5 dBm. The core LNA draws 3 mA from a 3-V supply.

5.2-GHz GaInP/GaAs HBT cascode LNA with 5.5 dB gain enhancement using inter-stage LC matching

A gain boosting method without noise-figure degradation by optimizing interstage matching in a cascode low-noise amplifier (LNA) with emitter-degeneration inductor is demonstrated at 5.2 GHz using 2-μm GaInP/GaAs HBT technology. A low-pass LC matching network is inserted in the interstage of a conventional cascode LNA with emitter-degeneration-inductor to enhance the gain with the same current consumption. The 2-μm GaInP/GaAs HBT LNA without interstage matching has 14-dB power gain and 2.37-dB noise figure at 5.2 GHz while the 2-μm GaInP/GaAs HBT LNA with interstage matching has 19.5-dB power gain and 2.22-dB noise figure at 5.2 GHz. The current consumption is 2.3 mA and voltage supply is 3.6 V. © 2006 Wiley Periodicals, Inc. Microwave Opt Technol Lett 48: 1499–1501, 2006; Published online in Wiley InterScience (www.interscience.wiley.com). DOI 10.1002/mop.21741

Fully-integrated GaAs HBT power amplifier MMIC with high linear output power for 3 GHz-band broadband wireless applications

A high linear output power two-stage GaAs heterojunction bipolar transistor (HBT) power amplifier MMIC is reported. The input, interstage and output matching circuits are designed for wideband and low-voltage operations, and are fully integrated into an MMIC chip. The power amplifier measured with 54 Mbits 64-QAM OFDM signals at a collector supply voltage of 3.3 V showed linear output power of higher than 23.2 dBm at an error vector magnitude of 3.0% in a frequency range 3.3–3.6 GHz.