Interstage Matching Network Research Articles

Low NF and High P1dB Wideband Quasi-Circulator With Unequal Power Split and Reconfigurable Inter-Stage Matching

In this article, a wideband quasi-circulator (QC) with the low noise figure (NF) and high 1-dB compression point ( P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> ) is proposed. The slotline-based 180° hybrid is introduced to achieve the wideband high transmitter-receiver (TX-RX) isolation. Meanwhile, the bidirectional in-phase stage and the nonreciprocal out-of-phase stage are utilized to obtain specific power-split ratios for the low insertion loss and high antenna-transmitter (ANT-TX) isolation. By using the unequal power split, the proposed QC is without the fundamental 3-dB loss seen in reciprocal ANT interfaces. Besides, to further enhance the TX-RX isolation within a wideband, a reconfigurable inter-stage matching network based on a varactor-tuned capacitor is implemented. To verify the mechanisms mentioned above, a reconfigurable wideband QC operating at 1.75-2.9 GHz is implemented and fabricated. The total power consumption is 224 mW. The measurement exhibits in-band TX-RX isolation of 27-58 dB. The TX-ANT and ANT-RX insertion losses are 4.3-5.0 dB and 1.0-1.9 dB, respectively. The QC also achieves the minimum in-band ANT-RX NF of 3.4 dB. Meanwhile, the measured TX-ANT and ANT-RX IIP3s are 39.4 and 32.5 dBm, respectively. The TX input P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> is greater than 28.78 dBm, while the RX input P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> is 23 dBm. The TX-induced ANT-RX P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">1 dB</sub> is measured to be 28 dBm.

A Ku-Band CMOS Power Amplifier With Series-Shunt LC Notch Filter for Satellite Communications

This article presents a Ku-band power amplifier with a series-shunt LC notch filter in 65-nm CMOS. The notch filter is integrated into the inter-stage matching network to attenuate the receiver-band noise, thereby reducing transmitter-to-receiver interference. A comprehensive analysis of the series and the shunt notch filters, as well as the position to apply the notch filter is discussed. Besides, a systematic method of optimizing passive devices in the notch filter is proposed to further improve network Q and minimize the influence on the power amplifier. Fabricated in 65-nm CMOS technology, the power amplifier prototype delivers a measured gain of 21.9 dB with 3-dB bandwidth from 13.7 GHz to 16.7 GHz at the nominal state. At 14.2 GHz, it can offer a saturated output power of 14.5 dBm with peak power added efficiency of 24.1%. The notch frequency is adjustable from 10.3 to 11.9 GHz to offer the best attenuation at the receiver band. From 10 to 12 GHz, a maximal attenuation of 30 dB is achieved. The design occupies a core area of 0.35×0.85 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> .

Novel Battery-Less Sustainable Energy Harvester Scheme for On-board Electronic Units

With the rapid development in smart vehicles, the on-board unit is established for communication between the vehicle and toll collection booth for toll collection. However, providing a continuous power supply to such units has been a challenge. While features like compactness, low cost and simplicity are to be maintained, the accuracy and performance of the device are to be maintained intact. This paper proposes a battery-less energy harvester scheme as a solution to this power issue. Maximum energy transmission Several researches are conducted on obtaining maximum energy transmission through performance optimization in this domain. This paper provides maximum performance while minimizing the energy harvester transponder dimensions. The energy transmitted to the transponder is maximized considering the optimal source impedance. This provides power to the battery-less structure. The radio frequency to DC rectifier is provided with an optimal source impedance with the help of a small patch antenna. Utilization of a lossy matching network can be avoided through this technique. Inter-stage matching network is used for comparison of the function. The energy efficiency using the proposed scheme is increased by a factor of 10% when compared to the existing schemes.

Fully integrated CMOS tunable power amplifier using reconfigurable input/interstage/output matching networks

This paper presents a two-stage tunable power amplifier (PA) fully-integrated in 130 nm CMOS process. This multi-band PA consists of reconfigurable input, interstage, and output matching networks in order to tune the center frequency in use. The proposed tunable power amplifier enables three different bands with center frequency of 900 MHz, 1450 MHz, and 1900 MHz. By switching these bands, the designed power amplifier covers frequency range of 700 MHz–2200 MHz known as Long-Term Evolution mobile network. As a result, the proposed tunable power amplifier obtains small-signal gain (S21) of 27.8 dB/29.4 dB/28.6 dB, saturated output power (Psat) of 22.4 dBm/23.0 dBm/23.2 dBm, and power added efficiency of 21.0%/23.7%/25.0% at three targeted frequency bands, respectively. The proposed fully-integrated triple-band power amplifier chip layout occupies an area of 2.25 mm2 including bond pads.

Design of 35-dB 0.03-to-2.7 GHz Two-Stage Broadband Power Amplifier With 37.2 dBm Psat Using Modular Technology

This paper presents a modular technology for two-stage broadband power amplifier (PA) design. The proposed method focuses on separately realizing two stage’s flat gain characteristics, thus providing the entire circuit’s required flatness over broad bandwidth. The power stage employs stacked structure to provide enough power and confine the output impedance around $50~\Omega $ , while the driver stage’s periphery is selected to achieve impedance transformation demanded by modularization. The elaborate requirements for input and inter-stage matching networks (MNs) are repeatable which can be synthesized by real frequency technique (RFT), shortening the design time of broadband MNs. The modular approach can also be transferred to the implementation of other broadband PAs. This novel technology was verified using $0.25~\mu \text{m}$ GaAs PHEMT process. The fabricated two-stage broadband PA obtains a small-signal gain higher than 35.0 dB and saturated output power of 37.2± 1.6 dBm from 30 MHz to 2.7 GHz, with a peak power added efficiency (PAE) of 46.2% at 500 MHz. To our knowledge, this is the highest gain and output power in GaAs broadband amplifier below 2.7 GHz.

A 120–150 GHz Power Amplifier in 28-nm CMOS Achieving 21.9-dB Gain and 11.8-dBm Psat for Sub-THz Imaging System

This paper presents a high-gain D-band power amplifier (PA) fabricated with 28-nm CMOS technology for a sub-terahertz frequency modulated continuous wave imaging system. It adopts two-channel power combining using artificial transmission lines to absorb the parasitic capacitance of the ground-signal-ground pad. The layout of the transistors and neutralization capacitors are optimized to improve the maximum stable gain, stability, and robustness. Asymmetrically magnetically coupled resonators are used in inter-stage and input matching networks to extend the operating bandwidth. The PA achieves a peak power gain of 21.9 dB and maximum output power of 11.8 dBm with 10.7% of power-added efficiency. Also, this PA can achieve higher than 10 dBm output power over the frequency range of 120–150 GHz.

Design of a Compact and Highly Efficient Energy Harvester System Suitable for Battery-Less Low Cost On-Board Unit Applications

This study addresses the general problem regarding the power supply in specific on-board unit (OBUs) solutions. In detail, this paper refers to a subset of the so-called electronic toll collection (ETC) applications such as assets control and vehicle identification, where simplicity, low costs, and maximum compactness represent the most important features. In this context, the next generation of OBUs, developed specifically with reference to such applications, will involve energy harvester-based battery-less techniques. Previous studies have mainly concentrated on performance optimization by achieving maximum energy transmission to the OBUs. This study discusses a technique suitable for both maximizing performance and minimizing the dimensions of transponder energy harvesters suitable for assets control and vehicle identification operating at 5.8 GHz. The technique assumes that an optimal source impedance exists that maximizes the energy transfer to the transponder, thus enabling its power supply in a battery-less configuration. We discuss a solution based on a compact patch antenna designed to exhibit this optimal source impedance to the RF-to-DC rectifier. This approach avoids the use of a lossy matching network. For the sake of comparison, the same function is compared with an equivalent development, which includes the interstage matching network between the antenna and the RF-to-DC rectifier. We introduce experimental results demonstrating that the ultracompact energy harvester optimized at −5 dBm of impinging power is capable of increasing both the charge current and energy efficiency from 340 to 450 μA and from 37% to 47%, respectively.

Design of a Ka-Band Cascode Power Amplifier Linearized With Cold-FET Interstage Matching Network

A Ka-band CMOS cascode power amplifier (PA) linearized with a cold-FET-based interstage matching network is presented, which is designed in a 65-nm CMOS process. Since it is difficult to make a cascode PA matched to the optimum output and input impedances at high frequencies, a matching network has to be introduced at the node between the common-source (CS) and common-gate (CG) stages. The cold-FET-based matching network improves the linearity and the input and output impedance matchings, which is analyzed and optimized with its simple model. It makes the PA have gain expansion and phase lag with the power, which allows the PA to have less amplitude-to-amplitude (AM-AM) and amplitude-to-phase (AM-PM) distortions. In addition, it improves the return losses of the PA by making the impedances for power matching and conjugate matching located closely. The implemented PA achieves the peak power-added efficiency (PAE) of 38.2% and the saturated output power (P <sub xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">sat</sub> ) of 17.1 dBm at 31 GHz while occupying the chip area of 0.16 mm <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">2</sup> . It is also shown that the OP1 dB is improved by 1.7 dB, and the AM-PM distortion is reduced to only 1.1° due to the linearization technique. It is tested with 64-quadrature amplitude modulation (QAM) signals, which has a 400-MHz channel bandwidth (BW) and a 9.7-dB peak-to-average power ratio (PAPR). It achieves average output powers of 9.6/7.7 dBm with error vector magnitudes (EVMs) of -25/-30 dB for 64-QAM OFDM signals, efficiencies of 17.7%/12%, and the adjacent channel leakage ratio (ACLR) of -28.2/-32.8 dBc, respectively.

A 52–58 GHz Power Amplifier With 18.6-dBm Saturated Output Power for Space Applications

This brief presents a 52–58 GHz power amplifier (PA) with constant output power across the entire band. A new topology based on the impedance transformation of transmission lines was adopted as the inter-stage matching network. Compared with the conventional 2-section LC matching topology, our approach reduced the matching loss by 1.5 dB at 54 GHz. Such topology made the design capable of operating at a frequency close to 80% of the unit-current-gain cut-off frequency ( $f_{T}$ ) specified by the device technology. Additionally, stacked-FET was adopted as the power stage for the output power enhancement in a broadband sense. Implemented in the commercially available 0.15- $\boldsymbol{\mu }\text{m}$ GaAs pseudomorphic high-electron-mobility transistor (pHEMT) process, the 2-stage PA demonstrated a small-signal gain of 14.7 dB, a saturated output power ( $P_{sat}$ ) of 18.6 dBm, and a maximum power-added-efficiency (PAE) of 18.2% at 54 GHz.

A Reconfigurable Class-AB/F Power Amplifier for 0.1–4.2 GHz Multistandard Applications

In this paper, a reconfigurable multi-mode Class-AB/F power amplifier (PA) is proposed for 0.1–4.2 GHz multistandard applications. The PA operates in linear mode (class-AB) for variable-envelope modulated signals and switching mode (class-F) for constant-envelope modulated signals. The proposed linear mode PA design is suitable for multi-band LTE, IOT, WSN and multi-standard RF transmitter, while switching mode PA design can be used in multi-band IOT-LPWA and BLE (Bluetooth Low Energy) RF transmitter. The proposed PA has a reconfigurable off-chip inter-stage and output matching networks over the specified frequency band, while the input stage is Complementary Current-Reuse common-gate with active shunt feedback configuration to achieve Ultra-Wideband (UWB) input matching. The proposed multi-mode PA is designed using a 130 nm CMOS process. Class-AB PA has a saturated output power of 23.5 dBm ± 1 dB over 0.1–4.2 GHz, a power-added efficiency (PAE) of 41%, a third-order intercept point (OIP3) of 17 dBm, and adjacent channel power ratio (ACPR) of − 29.3 dBc for LTE 15 MHz channel bandwidth. The maximum PAE of 62.1% under the class-F operation is achieved at output power of 24.5 dBm. The PA occupies 0.64 mm2 of chip area, while the estimated off-chip area is 13.3 mm2. The proposed PA consumes 164 mW, and 16 mW in class-AB and class-F, respectively.

A 38-GHz Millimeter-Wave Double-Stacked HBT Class-F−1 High-Gain Power Amplifier in 130-nm SiGe-BiCMOS

Investigations into integrated millimeter-wave (mmW) Class-F−1 power amplifier (PA) in stacked configuration have not been reported previously. This article presents a novel two-stage double-stacked heterojunction bipolar transistor (HBT) Class-F−1 PA in the 130-nm SiGe-BiCMOS technology. The proposed amplifier operates at the mmW center frequency of 38 GHz. The driving stage of the amplifier is loaded with a Class-F harmonic network and the double-stacked power stage incorporates Class-F−1 loading. An interstage matching network is designed to deliver maximum power transfer from the driving stage to the power stage. The proposed new HBT amplifier yields a saturated output power of 21.2 dBm along with an overall gain of 22.1 dB and a peak power-added efficiency (PAE) of 30.1%. A figure-of-merit (FoM) of 69.68 was achieved for this amplifier which is the highest so far when compared with various recently reported integrated mmW Class-F−1/F PAs.

Millimeter Wave SOI-CMOS Power Amplifier With Enhanced AM-PM Characteristic

This paper proposes a novel inter-stage load-pull characterization method to enhance the linearity of millimeter wave integrated power amplifiers (PAs) by minimizing their amplitude-to-phase (AM-PM) distortion without worsening their AM-AM or efficiency performances. The proposed method identifies the optimal solution for the inter-stage matching network which enables the synthesis of a driver stage AM-PM characteristic that is complementary to that of the power stage; consequently, reducing the overall AM-PM distortion of the PA. The proposed technique is applied to design a proof-of-concept 28–31 GHz PA demonstrator using 45 nm silicon-on-insulator CMOS technology. The measurement results obtained under continuous wave excitation at 29 GHz demonstrate an excellent AM-PM characteristic, with phase distortions as low as 0.2° at the 1-dB compression power level of 13.9 dBm and less than 1° at an output power level of up to 16 dBm (very close to the saturation power of 16.6 dBm). This enhanced AM-PM linearity improves the linearizability of the PA. This was confirmed by testing the PA with a 64 quadrature amplitude modulated test signal with an instantaneous bandwidth of 800 MHz. Without applying any digital pre-distortion (DPD) technique, the PA delivers a power added efficiency (PAE) of 8.7% at an average output power ( $P_{avg}$ ) of 9.4 dBm while maintaining an error vector magnitude (EVM) of −25 dB. However, after applying a very simple memoryless DPD function with only four coefficients, the PA can operate at a higher $P_{avg}$ of 11.1 dBm with a much better PAE of 12.2% while still maintaining an acceptable EVM of −25.2 dB. Thanks to the proposed technique, the PAE of the proposed PA can be improved by 40% with a very simple application of a low cost and low complexity DPD technique.

A 60 GHz balun low-noise amplifier in 28-nm CMOS for millimeter-wave communication

In this paper, a 60 GHz complementary metal-oxide-semiconductor (CMOS) balun low-noise amplifier (LNA) was implemented for millimeter-wave communication. To improve the gain and noise performance, slow-wave coplanar waveguides (S-CPW) with high quality factor were designed as input, output, and inter-stage matching networks. At the input port, a balun transformer provides additional passive gain while performing the singled-ended to differential conversion. Implemented in a 28-nm CMOS process, simulated results show that the proposed LNA exhibits a simulated linear gain of 16 dB and a noise figure of 5.6 dB at 60 GHz, with a 3-dB gain bandwidth of 5 GHz (58 GHz–63 GHz). The input return loss is better than −25 dB at the central frequency. The simulated input third-order intercept point (IIP3) is −5 dBm. The circuit draws 35 mA from 1 V supply voltage.

Tunable Quasi-Circulator Based on a Compact Fully-Reconfigurable 180° Hybrid for Full-Duplex Transceivers

In this paper, a tunable quasi-circulator (QC) is proposed, which consists of a compact fully-reconfigurable 180° hybrid and two amplifier stages in the transmitter (TX)- and receiver (RX)-paths, respectively. Such hybrid is implemented by six varactor-tuned phase shifters, which can not only achieve the frequency tuning operation but also suppress the signal leaking from the TX to the RX in the proposed QC. To further enhance the TX-RX isolation, a variable-impedance balance resistor based on the PIN diode is introduced and tapped on the hybrid. Meanwhile, at the TX- and RX-paths of the QC, two amplifier stages with inter-stage matching networks are connected to the hybrid, respectively, which can achieve the nonreciprocity operation of the proposed QC with high performance. To verify the mechanism of the structures mentioned above, a tunable QC operating at 2.88–3.56 GHz is implemented and fabricated. The measurement has merits of the in-band TX-RX isolation greater than 34 dB, RX gain higher than 4.3 dB, and noise figure lower than 5.5 dB. Besides, the minimum gain of the TX path is 6.8 dB, and an output 1-dB compression point of 21.7 dBm with a power efficiency of 20% at 3.2 GHz is achieved, respectively.

Pole-Controlled Wideband 120 GHz CMOS Power Amplifier for Wireless Chip-to-Chip Communication in 40-nm CMOS Process

This brief proposes a wideband CMOS power amplifier (PA) with flat gain using a pole-controlled transformer in the sub-THz band for wireless chip-to-chip communication. An analysis of the transformer-based interstage matching network is presented, which indicates a zero in-band ripple condition. For verification, a pole-controlled PA (with an area of 0.33 mm $^{{2}}$ including PADs) is fabricated using a 40-nm CMOS process and measured. The proposed PA achieves a measured 3-dB bandwidth of 38.5 GHz from 96.5 GHz-to-135 GHz, small-signal gain of 15.8 dB, and saturated output power of 14.6 dBm with a peak power-added efficiency (PAE $_{\mathrm{MAX}}$ ) of 9.44%. The proposed PA shows state-of-the-art performance with respect to the bandwidth and other figures of merit.

A 10.56-GHz Broadband Transceiver With Integrated T/R Switching via Matching Network Reuse and 0.3–2.1-GHz Baseband in 28-nm CMOS Technology

This paper presents a 10.56-GHz transceiver with ultracompact transformer-based transmit/receive (T/R) switching via matching network reuse. The reused transformer can operate as T/R switch and impedance matching networks for a power amplifier (PA) and a low-noise amplifier (LNA) simultaneously. The T/R switch, PA, and LNA are fully codesigned, and the interstage matching networks of the PA and LNA are comatched with the T/R switch to improve the performance of the front end (FE). A three-coil transformer is introduced in the PA to improve the linearity and bandwidth of the FE in the transmit (TX) mode. A mode selection unit (MSU) is also utilized in LNA to improve the TX/RX isolation and the linearity of the FE in the TX mode. Utilizing the fully codesign technique in the FE, the bandwidth of the FE is extended to over 4.2 GHz in both the TX and RX modes. A novel “gm-cell-based” broadband programmable gain amplifier (PGA) and a third-order transconductance-capacitor (gm-c) low-pass filter (LPF) are used in analog baseband to provide over 24-dB gain and 1.8-GHz bandwidth adjustment range with ultralow dc power consumption. To prove the concept, the new architecture is implemented in 28-nm CMOS technology. Measurement results prove that the insertion loss of the proposed T/R switch introduced in both the TX and RX modes is ~0.5 dB, and benefiting from this, the RX obtained a 4.2-dB noise figure, and TX obtained 9.9- and 14.1-dBm OP1dB and Psat. The measured single sideband bandwidth of the transceiver is wider than 2.1 GHz in both the TX and RX modes.

A 230–260-GHz Wideband and High-Gain Amplifier in 65-nm CMOS Based on Dual-Peak $G_{{\mathrm{max}}}$ -Core

This paper proposes a wideband and high-gain amplifier design technique based on a dual-peak maximum achievable gain ( $G_{\mathrm{ max}}$ ) core. The proposed technique achieves a power gain close to $G_{\mathrm{ max}}$ at two frequencies simultaneously, thereby enabling the implementation of a wideband and high-gain amplifier. The input, output, and interstage matching networks are designed in a gain compensating manner, considering the gain variation of the dual-peak $G_{\mathrm{ max}}$ -core. The four-stage amplifier based on an identical dual-peak $G_{\mathrm{ max}}$ -core at each stage is implemented in a 65-nm CMOS process. The measured results show a 3-dB bandwidth of 30 GHz (227.5–257.2 GHz), a gain of 12.4 ± 1.5 dB, and a peak power added efficiency (PAE) of 1.6% with dc power dissipation of 23.8 mW, which corresponds to the widest 3-dB bandwidth and gain per stage comparable to those of other reported CMOS amplifiers operating at frequencies above 200 GHz.

A Fully Integrated −32-dB EVM Broadband 802.11abgn/ac PA With an External PA Driver in WLP 40-nm CMOS

Even though CMOS-based power amplifiers (PAs) provide reductions in size and cost for wireless local area network (WLAN) applications, their performances must be improved to match those of HBT-based PAs. In this paper, a design methodology for WLAN CMOS PAs is proposed to obtain broadband performances with a compact area using the wafer-level package technology. To achieve a highly linear output power with high efficiency across a 1-GHz bandwidth in a 5G-band PA, a reconfigurable interstage matching network and a broadband compact output transformer are proposed. For applications requiring a high linear transmission power, an integrated CMOS PA in a full transmitter chain must support the operation with external HBT-based PAs. A structure involving a main internal PA with an external PA driver is proposed to support the external PA mode with low-current consumption. The proposed structure does not require additional components or an output port and does not have the performance degradation of the main internal PA. The implemented 2.4G-band/5G-band CMOS PA using 40-nm CMOS technology has an average output power in the ranges of 19.1–19.2/18.6–18.8 dBm in the respective ranges of 2.4–2.5/4.9–5.9 GHz and concurrently complies with the −32-dB error vector magnitude (EVM) requirement. The power-added efficiencies (PAEs) for the 2.4G-band/5G-band CMOS PA with a −32-dB EVM is 12.9%/12.2% at 2.45/5.5 GHz. To the best of the authors’ knowledge, the presented PA exhibits the state-of-the-art minimum variation with high PAE and an output power in the range of 4.9–5.9 GHz compared to the fully integrated WiFi CMOS PAs reported thus far.

An X‐band single‐pull class A/B power amplifier in 0.18 μm CMOS

AbstractWe report a compact single‐pull X‐band power amplifier (PA) operating at the class AB utilizing on‐chip transformers in 0.18‐μm 1P6M CMOS technology. Designed X‐band PA includes the interstage matching network and the output power combiner by utilizing on‐chip transformers to achieve small area occupation with improved power added efficiency (PAE). A series RC network is employed between gate and drain of the MOS to provide stable operation with improved bandwidth. The designed PA measures the saturated output power of 18 dBm while the achieved power gain is 19.2 dB at 8 GHz. The output 1‐dB gain compression point (OP1dB) is 14.9 dBm, and the peak PAE is measured to be 22.6% under the supply of 1.8 V. The core chip size is 0.43 mm2 excluding the pads.

A 6–18-GHz Switchless Reconfigurable Dual-Band Dual-Mode PA MMIC Using Coupled-Line-Based Diplexer

In this paper, a switchless dual-band, dual-mode power amplifier (PA) has been developed for multioctave operation. For the switchless dual-band operation, we proposed a new coupled-line-based diplexer structure. The proposed diplexer operates as a balun at high-band frequencies and the coupled line at low-band frequencies. To better understand the proposed diplexer structure, a detailed analysis is performed based on a coupled-line theory. The interstage and output-stage matching networks of the PA are designed by using the proposed diplexer. To maximize the power-added efficiency (PAE) of the designed PA, turn off the unused band PAs and decide the optimum off-state bias condition of transistors. The designed dual-band, dual-mode PA is fabricated with commercial 0.25- $\mu \text{m}$ GaN HEMT process. The fabricated PA shows over 15-dB small-signal gain at 5–11 GHz in the low-band mode and 9–18 GHz in the high-band mode. The measured average output power and PAE are 35 dBm, 23% in the low-band mode and 37 dBm, 26% in the high-band mode.