Integral Nonlinearity Research Articles

A 12-bit, 2.5-bit/Phase Column-Parallel Cyclic ADC

A 12-bit, 1.67-MS/s, two-stage cyclic ADC, using a 1.5-bit algorithm in a 2.5-bit framework is proposed in this brief. The number of accurate comparators is reduced to half as compared with the conventional 2.5-bit stage, which reduces the power consumption. Furthermore, the pipelined operation of the two stages reduces the total number of clock-cycles, which improves the conversion rate. The proposed ADC is designed and fabricated in a standard 180-nm CMOS technology. The obtained differential nonlinearity and integral nonlinearity are +0.5/−0.5 LSB and +0.8/−0.9 LSB, respectively. The ADC consumes 435- $\mu \text{W}$ of power and occupies an area of 0.045 mm2. The postlayout simulations of ADC designed in a column-pitch of 5.6 $\mu \text{m}$ show that it is suitable for column-parallel readout in CMOS image sensors.

All-Digital Time-to-Digital Converter Design Methodology Based on Structured Data Paths

Time-to-Digital Converters (TDC) are popular circuits in many applications, where high resolution time measurements are required, for example, in Positron Emission Tomography (PET). Besides its resolution, the TDC's linearity is also an important performance indicator, therefore calibration circuits usually play an important role on TDCs architectures. This paper presents an all-digital TDC implemented using Structured Datapath to reduce the need for calibration circuitry and cells custom design, without compromising the TDC's linearity. The proposed design is fully implementable using a Hardware Description Language (HDL) and enables a complete design flow automation, reducing both development time and system's complexity. The TDC is based on a Delay Locked Loop (DLL) paired with a coarse counter to increase measurement range. The proposed architecture and the design approach have proven to be efficient in developing a high resolution TDC with high linearity. The proposed TDC was implemented in TSMC 0.18 CMOS technology process achieving a resolution of 180ps, with Differential Non-Linearity (DNL) and Integral Non-Linearity (INL) under 0.6 LSB.

基于五氧化二钽集成非线性光波导的高重复频率宽带平坦相干光频率梳的产生

基于五氧化二钽集成非线性光波导的高重复频率宽带平坦相干光频率梳的产生

Time Resolution Improvement Using Dual Delay Lines for Field-Programmable-Gate-Array-Based Time-to-Digital Converters with Real-Time Calibration

This paper presents a time-to-digital converter (TDC) based on a field programmable gate array (FPGA) with a tapped delay line (TDL) architecture. This converter employs dual delay lines (DDLs) to enable real-time calibrations, and the proposed DDL-TDC measures the statistical distribution of delays to permit the calibration of nonuniform delay cells in FPGA-based TDC designs. DDLs are also used to set up alternate calibrations, thus enabling environmental effects to be immediately accounted for. Experimental results revealed that relative to a conventional TDL-TDC, the proposed DDL-TDC reduced the maximum differential nonlinearity by 26% and the integral nonlinearity by 30%. A root-mean-squared value of 32 ps was measured by inputting the constant delay source into the proposed DDL-TDC. The proposed scheme also maintained excellent linearity across a range of temperatures.

A novel split capacitor array switching scheme with proportional coefficient for SAR ADC

A novel switching scheme with proportional coefficient for successive approximation register analog-to-digital converter is presented in this work. The proposed switching scheme realize proportional coefficient by means of charge-sharing, which can achieve a high energy efficiency. Due to the split capacitor array structure is adopted here, the total capacitance can be reduced by 96.9% over the conventional structure. Moreover, the bridge capacitor is the unit capacitor, which is very convenient for layout design and capacitance matching. Furthermore, the proposed switching scheme reduces the energy by 99.9% compared with the conventional architecture through using the MSB-split switching structure and the single-side method. The proposed switching scheme also has a good performance in reset energy consumption and linearity. Based on the MATLAB simulation results, the maximum differential nonlinearity and maximum integral nonlinearity results of the proposed switching scheme are 0.626 LSB and 0.727 LSB, respectively.

Hilbert Based Testing of ADC Differential Non-linearity Using Wavelet Transform Algorithms

In testing Mixed Signal Devices such as Analog to Digital and Digital to Analog Converters, some dynamic parameters, such as Differential Non-Linearity and Integral Non-linearity, are very critical to evaluating devises performance. However, such analysis has been notorious for complexity and massive compiling process. Therefore, this research will focus on testing dynamic parameters such as Differential Non-Linearity by simulating numerous numbers of bits Analog to Digital Converters and test the output signals base on new testing algorithms of Wavelet transform based on Hilbert process. Such a new testing algorithm should enhance the testing process by using less compiling data samples and prompt testing results. In addition, new testing results will be compared with the conventional testing process of Histogram algorithms for accuracy and enactment.

A Sub-mW Fractional-<inline-formula> <tex-math notation="LaTeX">${N}$ </tex-math> </inline-formula> ADPLL With FOM of −246 dB for IoT Applications

This paper presents a sub-mW fractional- ${N}$ all-digital phase-locked loop (ADPLL) with scalable power consumption, which achieves an figure of merit (FOM) of −246 dB. The proposed 10-b ultralow-power isolated constant-slope digital-to-time converter (DTC) achieves a 580-fs resolution and a measured integral nonlinearity (INL) of 870 fs with 0.14-mW power consumption at 52 MS/s. A narrow-range time amplifier (TA)-time-to-digital converter (TDC) with gain calibration minimizes both the in-band phase noise degradation and the loop-bandwidth variation. In addition, a coarse-DPLL is introduced with dead-zone function, which reduces the phase lock time to 4.2 $\mu \text{s}$ at a 13-MHz frequency error. The coarse-DPLL monitors large frequency and phase jump in the background while consuming almost zero power. In an ultralow power mode, the proposed fractional- ${N}$ ADPLL consumes a 0.65-mW power with a 26-MHz reference. A rms jitter of 1.00 ps and −50-dBc in-band fractional spur are achieved with a −242-dB FOM. In high-performance mode, a reference doubler is utilized, the jitter and spurs can be improved to 535 fs and −56 dBc, respectively, while consuming 0.98 mW. The proposed ADPLL with scalable power and jitter performance can be utilized for Internet-of-Things (IoT) applications, such as Bluetooth low energy (BLE) and Wi-Fi networks.

An Ultra-Low-Power 16-Bit Second-Order Incremental ADC With SAR-Based Integrator for IoT Sensor Applications

This brief presents a 16-bit amplifier-free second-order incremental analog-to-digital converter (IADC2) for sensor applications. The proposed IADC2 employs a power efficient successive approximation register (SAR)-based integrator for the charge transfer operation, which consumes dynamic power only, instead of using power-consuming operational transconductance amplifiers that consume a high static current. The proposed amplifier thus achieves ultra-low-power consumption in low-frequency operation. In addition, the charge redistribution period of a capacitor digital-to-analog converter (CDAC) in the SAR-based integrator is split in a time-interleaving way, such that the CDAC can be shared by the first and second integrators. A test chip, including the proposed IADC2, was fabricated using 0.18- ${\mu }\text{m}$ standard CMOS process technology. The measurement results show that the proposed IADC2 achieves a differential nonlinearity of −0.51/+0.74 LSB and an integral nonlinearity of −3.12/+0.24$ LSB. In addition, the measured maximum signal-to-noise ratio, and an effective number of bits are 93.4 dB and 15.22-bit for the dc signal, respectively. The measured power consumption is 0.24 ${\mu }\text{W}$ at a sampling frequency of 10 kHz. Therefore, the proposed IADC2 is suitable for various sensor applications requiring ultra-low-power consumption.

Highly‐digital voltage scalable 4‐bit flash ADC

This study describes the highly-digital 4-bit 200 MS flash analogue to digital converter (ADC) whose major part can be digitally synthesised thus achieving low power, reducing the time-to-market and is scalable with technology. The comparators used in the ADC consist of complementary metal-oxide-semiconductor (CMOS)-based inverter and NAND-NOR as standard cells. The complete flash ADC is designed in 180 nm CMOS technology with 1.8 V supply with the power consumption of 4.51 mW. The signal-to-noise and distortion ratio, signal-to-noise ratio and spurious-free dynamic range are equal to 23.3, 25.2 and 30.1 dB. It provides an effective number of bits equal to 3.5. The differential non-linearity (DNL) of this ADC is ± 0.25 LSB and integral non-linearity (INL) is + 0.6 LSB.

A CMOS SPAD Imager with Collision Detection and 128 Dynamically Reallocating TDCs for Single-Photon Counting and 3D Time-of-Flight Imaging.

Per-pixel time-to-digital converter (TDC) architectures have been exploited by single-photon avalanche diode (SPAD) sensors to achieve high photon throughput, but at the expense of fill factor, pixel pitch and readout efficiency. In contrast, TDC sharing architecture usually features high fill factor at small pixel pitch and energy efficient event-driven readout. While the photon throughput is not necessarily lower than that of per-pixel TDC architectures, since the throughput is not only decided by the TDC number but also the readout bandwidth. In this paper, a SPAD sensor with 32 × 32 pixels fabricated with a 180 nm CMOS image sensor technology is presented, where dynamically reallocating TDCs were implemented to achieve the same photon throughput as that of per-pixel TDCs. Each 4 TDCs are shared by 32 pixels via a collision detection bus, which enables a fill factor of 28% with a pixel pitch of 28.5 μm. The TDCs were characterized, obtaining the peak-to-peak differential and integral non-linearity of −0.07/+0.08 LSB and −0.38/+0.75 LSB, respectively. The sensor was demonstrated in a scanning light-detection-and-ranging (LiDAR) system equipped with an ultra-low power laser, achieving depth imaging up to 10 m at 6 frames/s with a resolution of 64 × 64 with 50 lux background light.

A Low-Power High-Linear Time-to-Digital Converter for Measuring R-R Intervals in ECG Signal Optimized by Neural Network and TLBO Algorithm

In this paper, a two-stage time interpolation time-to-digital converter (TDC) is proposed to achieve adequate resolution and wide dynamic range for measuring R-R intervals in QRS detection. The architecture is based on a coarse counter and a couple of two-stage interpolator circuit in order to improve the conversion linearity. The proposed TDC is modeled with the neural network, while the teacher–learner-based optimization algorithm (TLBO) is used to optimize the integral nonlinearity (INL) of the proposed TDC. The proposed optimization method shows a characteristic close to the ideal output of the TDC behavior over a wide input range. Using the achieved results of the TLBO algorithm simulation results using CADENCE VIRTUOSO and standard 180[Formula: see text]nm CMOS technology shows 1.2[Formula: see text]s dynamic range, 100[Formula: see text]ns resolution, 0.19[Formula: see text]mW power consumption and area of 0.16[Formula: see text]mm2. The proposed circuit can find application in biomedical engineering systems and other fields where long and accurate time interval measurement is needed.

A 4-Channel 12-Bit High-Voltage Radiation-Hardened Digital-to-Analog Converter for Low Orbit Satellite Applications

This paper presents a circuit design and an implementation of a four-channel 12-bit digital-to-analog converter (DAC) with high-voltage operation and radiation-tolerant attribute using a specific CSMC H8312 0.5- $\mu \text{m}$ Bi-CMOS technology to achieve the functionality across a wide-temperature range from −55 °C to 125 °C. In this paper, an R-2R resistor network is adopted in the DAC to provide necessary resistors matching which improves the DAC precision and linearity with both the global common centroid and local common centroid layout. Therefore, no additional, complicated digital calibration or laser-trimming are needed in this design. The experimental and measurement results show that the maximum frequency of the single-chip four-channel 12-bit R-2R ladder high-voltage radiation-tolerant DAC is 100 kHz, and the designed DAC achieves the maximum value of differential non-linearity of 0.18 LSB, and the maximum value of integral non-linearity of −0.53 LSB at 125 °C, which is close to the optimal DAC performance. The performance of the proposed DAC keeps constant over the whole temperature range from −55 °C to 125 °C. Furthermore, an enhanced radiation-hardened design has been demonstrated by utilizing a radiation chamber experimental setup. The fabricated radiation-tolerant DAC chipset occupies a die area of 7 mm $\times7$ mm in total including pads (core active area of 4 mm $\times5$ mm excluding pads) and consumes less than 525 mW, output voltage ranges from −10 to +10 V.

A Calibration-Free/DEM-Free 8-bit 2.4-GS/s Single-Core Digital-to-Analog Converter With a Distributed Biasing Scheme

This paper describes a calibration-free/dynamic-element-matching-free 8-bit 2.4-GS/s single-core current-steering digital-to-analog converter (CS-DAC) featuring an integral nonlinearity of ±0.097 LSB (equivalent to ~11-bit accuracy), a differential nonlinearity of 0.15/−0.05 LSB, a spurious-free dynamic range of >47.8 dB across the Nyquist bandwidth of 1.13 GHz, and a power dissipation of 26.4 mW from 1.2-/2-V supplies. These attributes are achieved by our proposed distributed biasing scheme, which largely decouples two critical tradeoffs in the CS-DAC—the tradeoff between the output impedance of the current sources and their current mismatches and that between the current mismatches and the timing errors. To simplify the CS-DAC measurements and hence reduced costs associated with testing during manufacturing, we propose a custom built-in $8\times 2.4$ -Gb/s digital pattern generator (DPG) featuring low I/O pin count, no high-speed data I/O circuits, and low hardware complexity/size. The proposed 8-bit 2.4-GS/s CS-DAC with the built-in DPG is realized using a commercial 65-nm low-power CMOS process.

Mutually Coupled Time-to-Digital Converters (TDCs) for Direct Time-of-Flight (dTOF) Image Sensors ‡

Direct time-of-flight (dTOF) image sensors require accurate and robust timing references for precise depth calculation. On-chip timing references are well-known and understood, but for imaging systems where several thousands of pixels require seamless references, area and power consumption limit the use of more traditional synthesizers, such as phase/delay-locked loops (PLLs/DLLs). Other methods, such as relative timing measurement (start/stop), require constant foreground calibration, which is not feasible for outdoor applications, where conditions of temperature, background illumination, etc. can change drastically and frequently. In this paper, a scalable reference generation and synchronization is provided, using minimum resources of area and power, while being robust to mismatches. The suitability of this approach is demonstrated through the design of an time-to-digital converter (TDC) array, distributed over 1.69 mm2, fabricated using TSMC 65 nm technology (1.2 V core voltage and 4 metal layers—3 thin + 1 thick). Each TDC is based on a ring oscillator (RO) coupled to a ripple counter, occupying a very small area of 550 m2, while consuming 500 W of power, and has 2 s range, 125 ps least significant bit (LSB), and 14-bit resolution. Phase and frequency locking among the ROs is achieved, while providing 18 dB phase noise improvement over an equivalent individual oscillator. The integrated root mean square (RMS) jitter is less than 9 ps, the instantaneous frequency variation is less than 0.11%, differential nonlinearity (DNL) is less than 2 LSB, and integral nonlinearity (INL) is less than 3 LSB.

Run‐time calibration scheme for the implementation of a robust field‐programmable gate array–based time‐to‐digital converter

SummaryIn this study, we propose a robust field‐programmable gate array (FPGA)–based time‐to‐digital converter (TDC) with run‐time calibration. A code density test was used for differential nonlinearity (DNL) calibration to deal with nonuniformity in delay cells. The proposed calibration scheme is implemented as a four‐step finite state machine (FSM) for run‐time calibration. We implemented the TDC with the proposed run‐time calibration circuit on the Xilinx 65‐nm FPGA platform. This improved the DNL and integral nonlinearity (INL) values over those obtained using a TDC without run‐time calibration circuit. The DNL and INL values at a time resolution of 46.875 picoseconds were [−0.68, 1.04] and [−4.27, 2.27] least significant bits, respectively. More than 30% DNL and INL improvements are achieved for the TDC with calibration circuit. The results obtained at temperatures of 27°C to approximately 70°C indicated that the proposed run‐time calibration circuit enhanced the capability of the FPGA‐based TDC against temperature effects. The FPGA‐based TDC with the proposed run‐time calibration FSM provides robust high‐resolution performance suited for a range of scientific applications.

A 0.44-fJ/Conversion-Step 11-Bit 600-kS/s SAR ADC With Semi-Resting DAC

This paper presents an 11-bit ultralow voltage energy efficient successive approximation register (SAR) analog-to-digital converter (ADC). With the proposed semi-resting (SR) digital-to-analog convertor (DAC) switching scheme, this paper consumes only 6%–13.5% switching energy, compared to the state-of-the-art works. In addition, the SR switching scheme effectively reduces the differential nonlinearity and integral nonlinearity to be 1/2, compared to the conventional approach under the same matching conditions. With the proposed SR DAC switching scheme, this paper can handle the same input swing using a half supply and consume smaller power consumption. A cascade-input comparator is developed to consume only 49% of the power and 66% of the decision time with a threefold front-stage gain boost. The test chip occupies a core area of 0.035 mm2 in 90-nm CMOS technology. The prototype consumes 187 nW at 600 kS/s with a single 0.3-V supply voltage. The achieved effective number of bits and spurious-free dynamic range at Nyquist input are 9.46 bits and 73 dB, respectively. The resultant Walden’s figure of merit (FoM) and Schreier’s FoM are 0.44 fJ/conversion-step and 180.8 dB, respectively.

Multichannel, Low Nonlinearity Time-to-Digital Converters Based on 20 and 28 nm FPGAs

This paper presents low nonlinearity, compact, and multichannel time-to-digital converters (TDC) in Xilinx 28 nm Virtex 7 and 20 nm UltraScale field-programmable gate arrays (FPGAs). The proposed TDCs integrate several innovative methods that we have developed: 1) the subtapped delay line averaging topology; 2) tap timing tests; 3) a direct compensation architecture; and 4) a mixed calibration method. The code density tests show that the proposed TDCs have much better linearity performances than previously reported ones. Our approach is cost-effective in terms of the consumption of logic resources. To demonstrate this, we implemented 96 channel TDCs in both FPGAs, using less than 25% of the logic resources. The achieved least significant bit (LSB) is 10.5 ps for Virtex 7 and 5.0 ps for UltraScale FPGAs. After the compensation and calibration, the differential nonlinearity (DNL) is within [–0.05, 0.08] LSB with σDNL = 0.01 LSB, and the integral nonlinearity (INL) is within [–0.09, 0.11] LSB with σINL = 0.04 LSB for the Virtex 7 FPGA. The DNL is within [–0.12, 0.11] LSB with σDNL = 0.03 LSB, and the INL is within [–0.15, 0.48] LSB with σINL = 0.20 LSB for the UltraScale FPGA.

A Low-Power 12-Bit Extended Counting ADC Without Calibration for CMOS Image Sensors

This brief proposes a low-power 12-bit column-parallel extended counting analog-to-digital converter (EC ADC) without calibration for CMOS image sensors. The proposed 12-bit EC ADC uses the ${\Delta \Sigma }$ ADC and single-slope ADC (SS ADC) to convert the input voltage to the upper 4 bit and lower 8 bit, respectively. It reduces power consumption by sharing a comparator between the ${\Delta \Sigma }$ ADC and the SS ADC, and is robust to the inaccurate ramp signal. The 16-LSB linearity error of the ramp signal causes only 1 LSB linearity error of the proposed EC ADC. In addition, the proposed EC ADC improves the ADC linearity without calibration by adjusting the slope of the ramp signal in the lower 8-bit conversion phase according to the capacitance mismatch between the sampling and feedback capacitors. A test chip with 200 readout channels, each including the proposed EC ADC, was fabricated using an 0.18- ${\mu }\text{m}$ CMOS process. The measurement results show that the proposed EC ADC achieves a differential nonlinearity of +0.4/−0.3 LSB and an integral nonlinearity of +3.5/0 LSB without calibration. In addition, the measured signal-to-noise distortion ratio and effective number of bits are 65.4 dB and 10.5-bit, respectively. The measured power consumption per ADC is $22~{\mu }\text{W}$ and the best figure of merit in power efficiency is achieved to be 82 fJ/step.

USER-SMILE: Ultrafast Stimulus Error Removal and Segmented Model Identification of Linearity Errors for ADC Built-in Self-Test

Linearity testing of analog-to-digital converters (ADCs) is very challenging and expensive due to the stringent linearity requirement on the stimulus and the extremely long test time. This paper introduces a novel method for ADC static linearity testing, allowing the stimulus linearity requirement to be significantly relaxed and the test time to be significantly reduced compared to the state-of-art histogram method. Two nonlinear but functionally related input signals are used as the ADC’s excitation and a stimulus error removal technique is used to recover test accuracy. With a segmented non-parametric integral nonlinearity model, this method requires much fewer parameters to accurately represent the nonlinearity. The proposed algorithm has been extensively verified and correlated in simulations. This method not only enables low-cost production testing but can also be used for low-cost on-chip built-in self-test. This method is limited to ADCs with segmented architecture such as SAR ADCs, pipeline ADCs, and cyclic ADCs.

Energy-efficient switching scheme based on floating technique for SAR ADC

A high energy-efficiency capacitor switching scheme for successive approximation register (SAR) analog-to-digital converters is proposed in the paper. During the design procedure, the charge characteristic of the floating capacitor and the technique of splitting capacitor ensure zero energy consumption of switching operation. With the reset energy of capacitor arrays taken into account, the proposed switching scheme can achieve 100% less switching energy over the conventional switching scheme. Furthermore, this work also achieves about 50% area reduction with only two reference voltages. The behavioral simulation of the proposed SAR was performed, the maximum differential nonlinearity and maximum integral nonlinearity are 0.451 and 0.452 LSB respectively.