Integrated Driver Circuit Research Articles

Optical Transmitter Based on a 1.3-μm VCSEL and a SiGe Driver Circuit for Short-Reach Applications and Beyond

Long-wavelength vertical-cavity surface-emitting lasers (LW-VCSELs) with emission wavelength in the 1.3-μm region for intensity modulation (IM)/direct detection optical transmissions enable longer fiber reach compared to C-band VCSELs, thanks to the extremely low chromatic dispersion impact at that wavelength. A lot of effort has been recently dedicated to novel cavity designs in order to enhance LW-VCSELs' modulation bandwidth to allow higher data rates. Another approach to further improve VCSEL-based IM speed consists of making use of dedicated driver circuits implementing feedforward equalization (FFE). In this paper, we present a transmitter assembly incorporating a four-channel 0.13-μm SiGe driver circuit wire-bonded to a novel dual 1.3-μm VCSEL array. The short-cavity indium phosphide buried tunnel junction VCSEL design minimizes both the photon lifetime and the device parasitic currents. The integrated driver circuit requires 2.5-V supply voltage only due to the implementation of a pseudobalanced regulator; it includes a two-tap asymmetric FFE, where magnitude, sign, relative delay, and pulse width distortion of the taps can be modified. Through the proposed transmitter, standard single-mode fiber reach of 20 and 4.5 km, respectively, for 28- and 40-Gb/s data rate has been demonstrated with state-of-the-art power consumption. Transmitter performance has been analyzed through pseudorandom bit sequences of both 2 7 -1 and 2 31 -1 length, and the additional benefit due to the use of the driver circuit has been discussed in detail. A final comparison with state-of-the-art VCSEL drivers is also includedt.

An external compensation method for AMOLED using the concept of ramp‐stop

AbstractIn this paper, we propose an external feedback method to compensate the device variation for active‐matrix organic light‐emitting diode. The pixel data current is controlled by ramping the gate voltage and converted to the sensed voltage Vsense in real time. When Vsense is equal to a preset voltage Vdata, the switching block outputs the low potential to stop the ramping. Therefore, the gate voltage is locked at the value corresponding to the target data current. This circuit is implemented with three thin‐film transistors in the active area and some functional blocks in driver integrated circuit (IC), namely, sentinel block, current‐voltage converting block, and switching block. Unlike the other usual methods of external compensation requiring double number of connections between driver IC and glass, by using the common ramping signal and a simple circuit made on glass, the proposed method can be implemented with only one pin per column.

Allegro MicroSystems Europe Announces New High-Current Integrated DC Motor Driver Integrated Circuit

Allegro MicroSystems Europe Announces New High-Current Integrated DC Motor Driver Integrated Circuit

P‐52: A Fibonacci‐Like Charge Pump and its Current Drive Capacity Enhancement for Display Driver ICs

In this work, a mixed‐Fibonacci charge pump scheme with gate drive enhancement is proposed to provide as high as 30 V output voltage for display driver integrated circuits (ICs). By generating a high supply voltage (<6.6 V) with a first voltage doubler charge pump, the subsequent Fibonacci charge pump engages more middle‐voltage (MV) power transistors and more MV control signals. This improves the current drive capacity by approximately 50%‐120%, and the power efficiency is optimized by approximately 10%. Alternatively, it saves about 50% of chip size compared with the traditional scheme. Based on a 0.11 μm 1.5 V/6 V/32 V process, the design is fabricated and the performance improvement is validated. The novel one can achieve a peak current drive capacity of 1.74 mA and its peak power efficiency is 74%.

General-Purpose Clocked Gate Driver IC With Programmable 63-Level Drivability to Optimize Overshoot and Energy Loss in Switching by a Simulated Annealing Algorithm

A general-purpose clocked gate driver integrated circuit (IC) to generate an arbitrary gate waveform is proposed to provide a universal platform for fine-grained gate waveform optimization handling various power transistors. The fabricated IC with a 0.18 μm Bipolar-CMOS-DMOS process has 63 P-type MOS (PMOS) and 63 N-type MOS (NMOS) driver transistors on a chip whose activation patterns are controlled by 6-bit digital signals and 40 ns time step control. In the 500 V switching measurements with a manual gate waveform optimization, the proposed gate driver reduces the IC overshoot by 25% and 41%, and the energy loss by 38% and 55% for Si-insulated-gate bipolar transistor and SiC-MOSFET, respectively, which demonstrate the feasibility of driving various power devices with the same driver. An automatic optimization by simulated annealing algorithm is introduced to fully utilize the benefit of the gate driver, and the further reduction of IC overshoot by 26% and the energy loss by 18% are achieved over the manual optimization.

A small‐area and low‐power data driver IC using two‐stage DAC with a capacitor array for active matrix flat‐panel displays

AbstractA small‐area and low‐power data driver integrated circuit (IC) using a two‐stage digital‐to‐analog converter (DAC) with a capacitor array is proposed for active matrix flat‐panel displays. The proposed data driver IC employs a capacitor array in the two‐stage DAC so as to reduce the DAC area and eliminate the need for a resistor string, which has high‐power consumption. To verify the proposed two‐stage DAC, a 20‐channel data driver IC with the proposed 10‐bit two‐stage DAC was fabricated using a 0.18‐μm complementary metal–oxide–semiconductor process with 1.8 and 6 V complementary metal–oxide–semiconductor devices. The proposed 10‐bit two‐stage DAC occupies only 43.8% of the area of a conventional 10‐bit two‐stage DAC. The measurement results show that the differential nonlinearity and integral nonlinearity are +0.58/−0.52 least significant bit and +0.62/−0.59 least significant bit, respectively. The measured interchannel deviation of the voltage outputs is 8.8 mV, and the measured power consumption of the 20‐channel data driver IC is reduced to 7.1 mW, which is less than half of the power consumed by the conventional one.

10-Gb/s Distributed Amplifier-Based VCSEL Driver IC With ESD Protection in 130-nm CMOS

This paper presents a low-power 10-Gb/s vertical cavity surface emitting laser (VCSEL) driver integrated circuit (IC) with electrostatic discharge (ESD) protection in the 130-nm CMOS technology. A distributed amplifier (DA)-based modulator is proposed to boost the driver bandwidth. It employs artificial transmission lines to cancel the device parasitic capacitances of the driver. A distributed ESD protection technique is applied to equalize the group delay of the DA to optimize the jitter performance. To minimize the silicon area, the optimal number of DA taps in the proposed modulator has been derived. To compensate for the capacitive load and the channel losses at the output of the driver, a frequency-domain preemphasis scheme is proposed. The proposed DA modulator occupies an area of 0.69 mm2, and the entire driver IC has a die size of $2~\textrm {mm} \times 2$ mm, including the pads. Both electrical and optical tests have been carried out to characterize the performance of the proposed VCSEL driver IC. Measurements at a data rate of 10-Gb/s demonstrate a typical power consumption of 85 mW under a single 2.5 V supply voltage (49 mW, if separate 1.2 and 2.5 V supplies are used) and an rms jitter of 0.63 and 1.12 ps for the electrical test and optical test, respectively.

Design and Analysis of 37.5% Energy-Recycling Flyback-Type Class-D Low-Side Gate Driver IC with 5-to-15-V Level Conversion

This paper presents an energy-recycling class-D low-side gate driver integrated circuit (IC), which can also perform 5-to-15-V level upconversion using a bidirectional flyback converter topology. The gate driver itself is a mini switching regulator that operates at 5–15 MHz to generate 1-μs transition time gate-switching waveforms. In order to maintain uniform charging/discharging currents during transitions, the embedded flyback converter operates in a pulse-frequency modulation mode while charging and in a pulse width modulation mode while discharging the gate node. The required pulses with digitally programmable frequencies and duty cycles are efficiently generated by a custom-designed IC fabricated in a 0.25-μm HV CMOS technology. Also, the presented analysis guides a way to achieve the desired transition time with the maximum efficiency. The prototype IC demonstrates 37.5% energy recycling while driving a 15-V insulated-gate bipolar transistor power switch with 105-nC gate charge at 20 kHz.

Four-Channel WDM Transmitter With Heterogeneously Integrated III-V/Si Photonics and Low Power 32 nm CMOS Drivers

We experimentally demonstrate a novel four-channel wavelength division multiplexing transmitter operating at 1.3 μm wavelength employing heterogeneously integrated III-V/Si photonic circuit co-packaged with low-power 32-nm SOI CMOS driver integrated circuits (ICs). Error-free operation (BER <; 10 <sup xmlns:mml="http://www.w3.org/1998/Math/MathML" xmlns:xlink="http://www.w3.org/1999/xlink">-12</sup> ) has been achieved across all four channels for back-to-back, 2 and 10 km single-mode fiber transmission at 25 Gb/s per each channel, targeting intra-and inter-data-center interconnect applications. Power consumption as low as 19.2 mW for four CMOS driver ICs has been recorded, which yields 0.19 pJ/bit energy efficiency.

Transmitter Made up of a Silicon Photonic IC and its Flip-Chipped CMOS IC Driver Targeting Implementation in FDMA-PON

We report on the design, fabrication, and characterization of a reflective transmitter targeting implementation in passive optical networks (PON) with frequency division multiplexed access (FDMA). It is made up of a Silicon photonic integrated circuit (Si-PIC) comprising a reflective Mach Zehnder modulator and its flip-chipped CMOS electronic integrated circuit driver, the two ICs being interconnected by means of high density and low parasitic copper micro pillars. Several transmissions, in an FDMA PON context, are successfully demonstrated using 500 MBaud QPSK and 16-QAM modulated subcarriers, achieving bit error rate below 2.10−3. For QPSK-modulated subcarriers (respectively, 16-QAM), the available access frequency bandwidth is measured to be 1–7 GHz (respectively, 2–4 GHz) with an available loss budget of 9 dB (respectively, 5 dB). Improvements of the Si-PIC are further identified to achieve compliancy with 31 dB ODN loss.

Application of cascode level shifter for EMI reduction in LCD driver IC

Purpose – This paper aims to design the circuit for electromagnetic interface (EMI) reduction in liquid crystal display (LCD). Design/methodology/approach – The cascode level shifter and segmented driver circuit are applied in LCD column driver integrated circuit (IC) for EMI reduction. Cascode current mirror is used in the proposed level shifter for DC voltage biasing and reduction of the driving current which passes through the level shifter. The on-off switching currents and transient times are measured and compared between the conventional and proposed level shifters. Additionally, a segmented data latch is obtained by the timing spread solution in data latch, and applied to split the large peak switching current into a number of smaller peak current. The timing spread-operation does not actually reduce the total power of the noise, instead, it spreads the noise power evenly over the frequency bandwidth. The optimal number of latch is dependent on the operating frequency and EMI allowance. The column driver IC and clock controller are integrated in 0.18 μm CMOS technology with 1-poly and 4-metal process. Findings – The post-layout simulation shows that the proposed column driver circuit for LCD driver IC significantly reduces the peak switching current, and it results in the reduction of EMI noise level by more than 15 dB. It is obtained with 20 segmented operations in data latch at 40 MHz frequency. Originality/value – The advantage of the cascode current source is that it can provide a well-controlled bias current with an accurate current transfer ratio. To reduce the EMI noise in LCD driver circuit, the cascode current source is properly located for the DC bias block in the level shifter. The application is rarely done by others, and a significant EMI noise reduction is found. The well-controlled current source provides a high performance switching in the level shifter.

Novel Dual-Coupling Pixel Circuit to Achieve High Transmittance of Blue-Phase Liquid Crystal

A new pixel circuit for in-plane switching blue-phase liquid crystal displays (IPS BPLCDs) is developed. The dual-coupling method enables the proposed circuit to generate twice the maximum output voltage of source driver integrated circuits (ICs) for the BPLC with a simple structure, so the achievable transmittance is about four times that of the BPLC that is simply driven using practical source driver ICs. A 10.1-in prototype IPS BPLC panel (720 × 360) and simulation results demonstrate the feasibility of the proposed circuit for practical BPLCD applications, and the tone rendering distortion index is as low as 0.11.

Implementation of Chip-Level Optical Interconnect With Laser and Photodetector Using SOI-Based 3-D Guided-Wave Path

A chip-level optical interconnect module combined with a vertical-cavity surface-emitting laser (VCSEL) chip, a photodetector (PD) chip, a driver integrated circuit (IC), and an amplifier IC on a silicon-on-insulator (SOI) substrate with 3-D guided-wave paths is experimentally demonstrated. Such an optical interconnect is developed for the signal connection in multicore processors or memory-to-processor interfaces. The 3-D guided-wave path, consisting of silicon-based 45° microreflectors and trapezoidal waveguides, is used to connect the optical signal between transmitter and receiver. In this paper, the VCSEL and PIN PD chips are flip-chip integrated on a SOI substrate to achieve complete chip-level optical interconnects. Due to the unique 3-D guided-wave path design, a higher laser-to-PD optical coupling efficiency of -2.19 dB and a larger alignment tolerance of ±10μm for the VCSEL/PD assembly are achieved. The measured laser-to-PD optical transmission efficiency can reach -2.19 dB, and the maximum optical power and threshold current of VCSEL is 3.27 mW and 1 mA, respectively. To verify the data transmission, the commercial driver IC and amplifier IC are assembled upon the silicon chip, and the error-free data transmission of 10 Gbps can be achieved when the VCSEL is operated at the driving current of 9 mA.

Integrated Protection Circuits for an NMOS Silicon Carbide Gate Driver Integrated Circuit

Recent work has been done to build a Silicon Carbide (SiC) gate driver IC for use with a 1,200V SiC power MOSFET. Protection circuits form an important part of the complete gate driver/power device system. Under-voltage lockout (UVLO) protection disables the gate driver when power supplies are insufficient to turn the power device fully on. Desaturation detection provides protection to the power device by recognizing over-current conditions and disabling the gate driver for a set duration. The protection circuits described in this paper are integrated with a novel SiC gate-driver architecture utilizing discrete 20 V and 40 V power supplies. Two separate UVLO circuits monitor these power supplies while being powered by the 20 V supply. The desaturation detection circuit ensures that the power device is in its safe operating area. The desaturation detection circuit is designed to work with a 20A SiC MOSFET in less than 500ns, while avoiding false triggering on leading-edge spikes. Bench test results of the two UVLOs and desaturation detection circuits were captured and are compared to simulated results.

A Novel Integrated Circuit Driver for LED Lighting

A novel integrated circuit for driving LED lighting has been proposed, designed and fabricated. Besides the typical parts of LED driver, an integral part was added at the output terminal of error amplifier in the driver. In this way, a novel average current mode can be set up to take the place ordinary peak current control mode. In addition, a BUCK low-level topology was adopted, too. It can be used to drive up to eight 1 W HB LED lights with 350 mA constant current. In this way, the LED driver displays high performance, in which output current with less 1% error and total efficiency as high as 96%. The feasibility of the design has been verified by actual measurement on the fabricated chip.

Design of adaptive dead-time control circuit for resonant half-bridge driver

To decrease the switching loss and the dead-time effect of resonant half-bridge inverter, a novel adaptive dead-time control circuit of resonant half-bridge driver Integrated Circuit (IC) is presented. Without increasing the pin number of IC, this circuit takes a novel strategy to adaptively regulate dead time to a temperate range between high and low thresholds. The high and low thresholds are adaptive to the fall time of output signal in a half-bridge clock cycle. The IC of the designed circuit is suitable for high-voltage applications. The dead-time regulation range of this circuit achieves 0–3.5 µs. The range of temperate dead-time state is 300 ns. The failure signal of this circuit can protect the IC and peripheral power devices by regulating operation in three clock cycles. Both simulation and measurement of the proposed circuit in a half-bridge driver IC with an operating frequency at 50 kHz are presented based on the 0.5 µm 700 V BCD process. The results of simulation and measurement show that the presented circuits’ performance is perfect.

Analytical model for energy recovery circuit of plasma display panel data driver integrated circuit

An analytical model is proposed to analyse the energy recovery circuit (ERC) efficiency of plasma display panel (PDP) data driver integrated circuit (IC). The experimental measurements agree with the analysis results very well. The analysis results show that the ERC efficiency of PDP data driver IC is influenced by three factors: the value of charge time TERC, the channel resistor Ron and the capacitance of CL. The range of TERC is restricted in actual PDP system. CL is determined by physical parameters of PDP panel, and its value is nearly changeless. Therefore the ERC efficiency of PDP data driver IC can be improved significantly by using superior DPLD (double-channel p-type lateral extended drain metal oxidesemi conductor) transistor that has smaller Ron.

Design and Investigation of an Isolated Gate Driver Using CMOS Integrated Circuit and HF Transformer for Interleaved DC/DC Converter

This paper deals with the design and the implementation of an isolated gate driver system using a CMOS integrated circuit for interleaved dc/dc converters. It is based on a novel gate driver topology for power switches like MOSFETs and insulated-gate bipolar transistors. Composed of two legs of a CMOS inverter, a high-frequency pulse transformer, and two Zener diodes connected in antiseries configuration with the gate of the power switch, this driver topology provides an optimal bipolar gate driver waveform with greater positive and negative gate biases to fasten the switch on and off. It represents a simple ultracompact isolated gate driver simple to integrate in CMOS technology. Power consumption, system size, and robustness of the gate driver are therefore optimized. This integrated driver circuit can be used for any multitransistor applications. We detail the operation principle of the proposed driver topology in this paper. We implemented the gate driver to control a three-phase interleaved boost converter; the results show the effectiveness of the proposed driver system.

A 200 °C Universal Gate Driver Integrated Circuit for Extreme Environment Applications

High-temperature power converters (dc-dc, dc-ac, etc.) have enormous potential in extreme environment applications, including automotive, aerospace, geothermal, nuclear, and well logging. For successful realization of such high-temperature power conversion modules, the associated control electronics also need to perform at high temperature. This paper presents a silicon-on-insulator (SOI) based high-temperature gate driver integrated circuit (IC) incorporating an on-chip low-power temperature sensor and demonstrating an improved peak output current drive over our previously reported work. This driver IC has been primarily designed for automotive applications, where the underhood temperature can reach 200 °C. This new gate driver prototype has been designed and implemented in a 0.8 μm, 2-poly, and 3-metal bipolar CMOS-DMOS (Double-Diffused Metal-Oxide Semiconductor) on SOI process and has been successfully tested for up to 200 °C ambient temperature driving a SiC MOSFET and a SiC normally-ON JFET. The salient feature of the proposed universal gate driver is its ability to drive power switches over a wide range of gate turn-ON voltages such as MOSFET (0 to 20 V), normally-OFF JFET (-7 to 3 V), and normally-ON JFET (-20 to 0 V). The measured peak output current capability of the driver is around 5 A and is thus capable of driving several power switches connected in parallel. An ultralow-power on-chip temperature supervisory circuit has also been integrated into the die to safeguard the driver circuit against excessive die temperature (≥220 °C). This approach utilizes increased diode leakage current at higher temperature to monitor the die temperature. The power consumption of the proposed temperature sensor circuit is below 10 μW for operating temperature up to 200 °C.

Highly power-efficient and reliable light-emitting diode backlight driver IC for the uniform current driving of medium-sized liquid crystal displays

In this paper, a light-emitting diode (LED) backlight driver integrated circuit (IC) for medium-sized liquid crystal displays (LCDs) is proposed. In the proposed IC, a linear current regulator with matched internal resistors and an adaptive phase-shifted pulse-width modulation (PWM) dimming controller are also proposed to improve LED current uniformity and reliability. The double feedback loop control boost converter is used to achieve high power efficiency, fast transient characteristic, and high dimming frequency and resolution. The proposed IC was fabricated using the 0.35 μ m bipolar–CMOS–DMOS (BCD) process. The LED current uniformity and LED fault immunity of the proposed IC were verified through experiments. The measured power efficiency was 90%; the measured LED current uniformity, 97%; and the measured rising and falling times of the LED current, 86 and 7 ns, respectively. Due to the fast rising and falling characteristics, the proposed IC operates up to 39 kHz PWM dimming frequency, with an 8-bit dimming resolution. It was verified that the phase difference between the PWM dimming signals is changed adaptively when LED fault occurs. The experiment results showed that the proposed IC meets the requirements for the LED backlight driver IC for medium-sized LCDs.