Integrated Circuit Applications Research Articles

Lateral depletion-mode 4H-SiC n-channel junction field-effect transistors operational at 400 °C* *Project supported by the Key Research and Development Program of Shaanxi Province, China (Grant No. 2020ZDLGY03-07), the National Science Foundation of China (Grant Nos. 61774117 and 61774119), the Science Challenge Project (Grant No. TZ2018003), the National Key R&D Program of China (Grant No. 2017YFB0102302), the Shaanxi Science & Technology

This paper presents the development of lateral depletion-mode n-channel 4H-SiC junction field-effect transistors (LJFETs) using double-mesa process toward high-temperature integrated circuit (IC) applications. At room temperature, the fabricated LJFETs show a drain-to-source saturation current of 23.03 μA/μm, which corresponds to a current density of 7678 A/cm2. The gate-to-source parasitic resistance of 17.56 kΩ ⋅ μm is reduced to contribute only 13.49% of the on-resistance of 130.15 kΩ ⋅ μm, which helps to improve the transconductance up to 8.61 μS/μm. High temperature characteristics of LJFETs were performed from room temperature to 400 °C. At temperatures up to 400 °C in air, it is observed that the fabricated LJFETs still show normally-on operating characteristics. The drain-to-source saturation current, transconductance and intrinsic gain at 400 °C are 7.47 μA/μm, 2.35 μS/μm and 41.35, respectively. These results show significant improvement over state-of-the-art and make them attractive for high-temperature IC applications.

Predictive physics based simulation of nano scale gate-all-around field effect transistor under the influence of high-k gate dielectrics

In this paper the electrical characteristics of a nano scale silicon gate-all-around field effect transistor (GAA-FET) with different dielectrics in the gate electrode are predicted. For this, we first calibrate physics based TCAD simulator against experimental results reported by IBM. Then the device electrical figures of merit comprised of ION/IOFF, transconductance (gm) and subthreshold slope (SS) are extracted. The obtained results show that utilizing various high-k gate dielectrics has a noticeable impact on the device performance. Different high-k gate dielectrics comprised of Al2O3, Si3N4 and HfO2 are explored in our study. Moreover, when high-k gate dielectric is used instead of conventional SiO2 insulator, the electrical characteristics will be improved in terms of ION/IOFF ratio, transconductance to drive current ratio (gm/IDS) and SS. Based on our simulations and obtained results, scaling GAA-FETs by utilizing high-k dielectrics offers superior electronic devices and promising candidates for “more Moore” domain and integrated circuit applications.

200°C/5 MHz GaN‐based gate driver circuits with 1 nF/4.7 Ω RC load for high‐temperature high‐frequency all‐GaN IC applications

A GaN-based gate driver circuits have been successfully designed and fabricated using a commercially available 6-inch GaN-on-Si platform. The driver circuits consist of three-stage direct-coupled FET logic (DCFL) inverters featuring monolithically integrated depletion-mode (D-mode) and enhancement-mode (E-mode) high electron mobility transistors (HEMTs). At room temperature (RT), at a supply voltage of 4 V the single-stage DCFL fabricated on the same die exhibits a large gate swing (3.84 V) and large noise margins (logic-low noise margin (NML) of 1.55 V and logic-high noise margin (NMH) of 2.18 V), both of which are desirable for all-GaN IC applications. Meanwhile, the gate driver circuits were characterised up to 200°C on a PCB with a capacitance load of 1 nF in series with 4.7 Ω resistance to resemble the load condition. At 200°C, the gate driver circuits function well even at 5 MHz operation frequency. The turn on/off propagation delay and rise/fall time of the gate driver circuits are 5/40 and 22/18 ns, respectively. As far as the authors’ knowledge, this is the highest reported operation frequency for GaN-based gate driver circuits under such high temperature, making it very promising for high-temperature high-frequency all-GaN integrated circuit (IC) applications.

Tuning of Threshold Voltage in Silicon Nano-Tube FET Using Halo doping and its Impact on Analog/RF Performances

In this paper, a novel method is proposed for the first time to achieve multiple threshold voltage (VT) for Silicon Nanotube FET. Using TCAD simulator, it is shown that threshold voltage can be varied by tuning the halo doping and tube diameter of Silicon Nanotube FET. The typical method to attain multiple threshold voltages is to select the pertinent gate work-function for individual devices. But this is not practically feasible due to the difficult process complexity. In this work, the tuning of halo doping and nanotube diameter can be elected to provide three possible values of VT at 14-nm technology node. Furthermore, short-channel effect like Drain Induced Barrier Lowering (DIBL) is also found to be reduced with HALO doped region at source side. It is also observed that the threshold voltage decreases while increasing the tube diameter. Moreover, HALO doping at drain side is found showing a significant improvement in analog/RF performances of the device which eventually makes the device more suitable for radio-frequency integrated circuit applications.

A novel source material engineered double gate tunnel field effect transistor for radio frequency integrated circuit applications

Tunnel field effect transistors (TFETs) have proved their potential for many possible electronic circuit applications. However, with the variety of TFET structures being worked upon it has been an unresolved challenge to optimize them for the applications to which they are best suited. In this paper we present a detailed comparative analysis of the linearity distortion and the radiofrequency (RF) performance parameters of a proposed heterojunction Mg2Si source double gate TFET (HMSDG-TFET) and a conventional homojunction Si source DG-TFET (SSDG-TFET). A source material engineering scheme is utilized to implement a staggered type 2 heterojunction at the source–channel junction by replacing the source material with Mg2Si (a low band gap material) to enhance the ON current (2.5 × 10–4 A µm−1), reduce the threshold voltage (0.26 V) and achieve a steeper subthreshold swing (10.05 mV decade−1). For linearity and distortion analysis, the figure of merit (FOM)-like higher-order transconductances, second- and third-order voltage intercepts, third-order intercept point, third-order intermodulation distortion, zero crossover point, 1 dB compression point, second-order harmonic distortion, third order harmonic distortion and total harmonic distortion have been examined. To portray the possible application of devices under consideration for RF integrated circuit applications, both structures are investigated for RF FOMs such as power gains, cutoff frequency (fT), maximum oscillation frequency (F max) and admittance parameters. Investigations carried out using a Silvaco ATLAS device simulator tool revealed that with fT approximately three orders higher (0.49 THz) and F max approximately two orders higher (0.9 THz) than that of a SSDG-TFET, the HMSDG-TFET is an appropriate candidate for use in high-frequency, high-linearity, low-distortion and low-power analog/RF applications.

Recent progress in germanium-core optical fibers for mid-infrared optics

The search for low-loss and robust optical fibers in the infrared spectrum has always been an important research topic for many investigators. Over the years, fibers of various materials groups have been proposed to obtain ‘the ultimate infrared fiber’. Recently, a new competitive alternative has emerged: the semiconductor-core glass-cladded optical fibers. The excellent bulk materials properties and integrated circuit applications reveals the potential of semiconductors as fiber materials. One of the important photonic materials that has been proposed as a fiber-core material is germanium. In this paper, the development of Ge-based fibers and their optical properties in the mid-infrared spectrum are discussed. The performance of Ge-based fibers has been compared with other semiconductor-core fibers. Recent developments in the area of semiconductor fibers and the future prospects of semiconductors as infrared fiber materials are also discussed.

Ion beam synthesis and photoluminescence study of supersaturated fully-relaxed Ge-Sn alloys

Direct-bandgap germanium-tin (Ge-Sn) alloys are highly sought-after materials for applications in silicon photonic integrated circuits. Other than crystal quality, two main factors determine the transition from the indirect to direct bandgap: the high Sn concentration and the strain relaxation in the materials. Using ion implantation and pulsed laser melting, we demonstrate a fully-relaxed Ge-Sn alloy with a Sn concentration of 6at.%. This concentration is at least 10 times higher than the equilibrium solubility of Sn in Ge. Cross-sectional transmission electron microscopy shows unconventional threading-like defects in the film as the mechanism for the strain relaxation. Due to the high degree of strain relaxation and the good crystal quality, photoluminescence could be obtained from the samples to examine the indirect-direct bandgap transition in the alloys.

Using the Hexagonal Layout Style for MOSFETs to Boost the Device Matching in Ionizing Radiation Environments

This paper describes an experimental comparative study of the matching between conventional (rectangular gate shape) and Diamond (hexagonal gate geometry) n-channel Metal-Oxide-Semiconductor (MOS) Field Effect Transistors (MOSFETs), which were manufactured in an 130 nm Silicon-Germanium Bulk Complementary MOS (CMOS) technology and exposed to different X-rays Total Ionizing Doses (TIDs). The results indicate that the Diamond layout style with alpha () angle equal to 90˚ for MOSFETs is capable of boosting the device matching by at least 17% regarding the electrical pa-rameters studied (Threshold Voltage and Subthreshold Slope) as compared with the conventional MOSFET counterparts, considering that they present the same gate area, channel width, bias conditions and for the same TID. This is due to the Longitudinal Corner Effect (LCE). Parallel MOSFETs with Different Channel Length Effect (PAMDLE) and Deactivation of Parasitic MOSFETs in the Bird’s Beak Regions Effect (DEPAMBBRE) present in the structure of Diamond MOSFETs. Therefore, the Diamond layout style can be consid-ered an alternative hardness-by-design (HBD) layout strategy to boost the electrical performance and TID tolerance of MOSFETs enabling analog or radio-frequency CMOS inte-grated circuits (ICs) applications.

A nano-FET structure comprised of inherent paralleled TFET and MOSFET with improved performance

Abstract In this paper we unveil of a new structure in which a Metal Oxide Semiconductor Field Effect Transistor (MOSFET) is paralleled with a Tunneling Field Effect Transistor (TFET) to increase on-state current. In order to enhance tunneling current injection rate in the device, workfunction engineering in gate and substrate electrodes and doping engineering in channel (source pocket) are utilized. For further on-state current enhancement of device, thermionic injection mechanism is used by incorporating a MOSFET in the structure. In addition, hetero gate dielectric is used to reduce parasitic capacitances. Our analysis show PTM-FET transistor has several excellences in comparison to DW HGD SP TFET in terms of transconductance, Ion/Ioff current ratio, short channel effects like DIBL, Early voltage, maximum transducer power gain, unilateral power gain, gain bandwidth product, unity gain frequency and parasitic capacitances. The mentioned advantages for PTM-FET transistor can be a window of utilizing this device in both low power and high performance integrated circuit applications.

Transconductance Amplification in Dirac‐Source Field‐Effect Transistors Enabled by Graphene/Nanotube Hereojunctions

AbstractSteep‐slope devices are predicted to provide excellent quality for analog integrated circuit applications due to their high transconductance efficiency (gm/Ids) breaking the metal‐oxide‐semiconductor field‐effect transistor limit (38.5 V−1). The potential advantage of a Dirac‐source FET (DSFET) as an analog transistor is explored based on a graphene/carbon nanotube (CNT) heterojunction. A high gm/Ids beyond 38.5 V−1 over four decades of current is experimentally demonstrated in an individual CNT‐based DSFET, reaching a peak value of 66 V−1, which is a new record for all reported transistors. Importantly, this high gm/Ids extends beyond the subthreshold region and leads to transconductance amplification in the overthreshold region. The best peak transconductance at a low bias of −0.1 V exceeds 20 µS per tube, which has approximately threefold improvement over that of a normal CNT FET with a shorter gate length. Outperforming other advanced devices, the extended high transconductance efficiency greatly promotes DSFET competitiveness in the high‐precision analog field.

Mechanical behaviors of MoS nanowires under tension from molecular dynamics simulations

As a new class of one-dimensional (1D) transition-metal monochalcogenides (TMMs) nanowires (NWs), the recently synthesized MoS NWs exhibit potential applications in two-dimensional integrated circuit. However, their mechanical behaviors remain almost unexplored. In this paper, the mechanical behaviors of MoS NWs under tensile loading are studied by classical molecular dynamics simulations together with first-principles calculations. A novel phase transformation is observed in the MoS NWs when the strain applied to them is larger than a critical value, which results in tension-induced hardening in their tensile modulus. Due to the existence of phase transformation, a complicated mechanical response is observed in MoS NWs during the entire loading process, which successively experiences the linear, plateau, stress hardening and fracture stages. The influence of various factors including the strain rate and temperature on the mechanical properties of MoS NWs such as phase transformation, Young’s modulus, fracture strength and fracture strain are also examined. The mechanical properties of MoS NWs obtained in this paper will be beneficial to their future applications in the semiconducting field. It is also expected that the results of the tension-induced phase transformation and its influence on the material properties observed in the present MoS NWs can be further extended to other 1D TMMs such as MoTe and SnSe NWs, since these 1D TMMs are found to possess the similar structure.

Photonic Crystal Circular Nanobeam Cavity Laser with Type-II GaSb/GaAs Quantum Rings as Gain Material

The optical emission from type-II semiconductor nanostructures is influenced by the long carrier lifetime and can exhibit remarkable thermal stability. In this study, utilizing a high quality photonic crystal circular nanobeam cavity with a high quality factor and a sub-micrometer mode volume, we demonstrated an ultra-compact semiconductor laser with type-II gallium antimonide/gallium arsenide quantum rings (GaSb/GaAs QRs) as the gain medium. The lasing mode localized around the defect region of the nanobeam had a small modal volume and significant coupling with the photons emitted by QRs. It leads the remarkable shortening of carrier lifetime observed from the time-resolved photoluminescence (TRPL) and a high Purcell factor. Furthermore, a high characteristic temperature of 114 K was observed from the device. The lasing performances indicated the type-II QRs laser is suitable for applications of photonic integrated circuit and bio-detection applications.

Assessment of On-Chip Current Sensor for Detection of Thermal-Neutron-Induced Transients

This article assesses, for the first time, a body/bulk built-in current sensor (BBICS) in a CMOS 65-nm test chip under thermal neutron, high-energy neutron, and laser radiation. Experimental results suggest that the on-chip current sensor is effective to detect transient faults in different case-study subcircuits of the chip exposed to the accelerated radiation effects, opening prospects for embedding this type of sensor in reliable, secure, and low-power integrated circuit applications.

Radio frequency thermal plasma-processed Ni-W nanostructures for printable microcircuit electrodes

Nonconventional alloy systems have been actively investigated to find an appropriate electrode candidate for highly integrated microcircuit applications. Here, a Ni-W nanoscale-alloy system is introduced to modulate the unwanted early densification of Ni nanoparticles by adopting a considerable amount of W in the single-step process of radio frequency thermal plasma synthesis. Multiple phases other than Ni phase, i.e., α-W and β-W, were found to coexist when the content of W was presumably beyond its solid solubility limit in Ni. Noticeable retardation of the densification of Ni was observed depending on the content of W in the resultant film electrodes fired at different temperatures up to 1200 °C. As expected, electrical resistivity of the film electrodes depended on the progress of densification. A large variation of electrical resistivity with different W contents was observed at the low temperature of 900 °C while the variation became very small at high temperatures of >1100 °C for all the films. The successful late densification indicates that the Ni-W alloy system is suitable as a microcircuit electrode with a reasonably low electrical resistivity of ~10−5 Ω cm.

Modeling of on-off Current and Cutoff Frequency in Organic Thin Film Transistors

Organic thin-film transistors (OTFTs) are providing incitement in various integrated circuit applications because of advantages like low cost and being flexible.In this paper we present an analytical modeling of on-off current and cutoff frequency in organic thin film transistors. The proposed model accurately describes both the parameters uniquely and is based on the standard equations of transistor . The model parameters are listed out and simulation of the final model is performed in MATLAB . Furthermore, it has been concluded that the high cutoff frequency of OTFTs can be achieved with short channel length and high gate voltage ,further high on-off current ratio can be attained by lowering semiconducting layers’ thickness and increasing the mobility.

Gate capacitance effect on P-type tunnel thin-film transistor with TiN/HfZrO2 gate stack

In this work, the polycrystalline-silicon (poly-Si) tunnel field-effect thin-film transistors (TFETs) with TiN/HfZrO2 gate stack materials are demonstrated to exhibit low threshold voltage ~ –1.218 V, subthreshold swing (SS) ~ 0.311 V/decade and channel length insensitive transfer characteristics. Conventional carrier transport mechanism of poly-Si thin-film transistors (TFTs) is the thermionic emission with scattering effect, which is deduced as the drift-diffusion transport model with additional trap state induced energy barrier height, resulting in the stronger channel length dependence effect. For the poly-Si TFETs, the carrier transport mechanism is the interband tunneling, including band-to-band tunneling and trap-assisted tunneling, which is less affected by the channel length. The different carrier transport mechanisms of poly-Si TFETs and TFTs would lead to different gate dielectric thickness effect. When the thickness of gate dielectric HfZrO2 is reduced from 18 to 10 nm to increase the gate capacitance density, the SS and on-state current of poly-Si TFETs exhibit much higher improvement than them of poly-Si TFTs. It indicates that the high gate capacitance density is a key parameter for the development of poly-Si TFETs to replace the conventional poly-Si TFTs in three-dimensional integrated circuit applications.

Radiation immunity study on space environment application of new integrated circuits

Radiation immunity study on space environment application of new integrated circuits

Characteristic Simulation of Hybrid Multilayer Junctionless Field Effect Transistors with Negative Capacitance Effect

In this study, we reported a hybrid multi-PNPN channel junctionless field effect transistor (JLFET) with negative capacitance (NC) effect by simulation. By incorporating a ferroelectric HfAlO capacitor with NC effect, an extremely low subthreshold swing of 34 mV/decade, a very high on/off current ratio and a very low driven voltage were achieved in the NC-enhanced hybrid multi-PNPN channel JLFET. This novel device not only improves the on-state current reduction while channel scaling down, but also shows great potential for the next-generation low-power three-dimensional stacked integrated circuit applications.

Programmable Hybrid Circuit Based on Reconfigurable SPP and Spatial Waveguide Modes

AbstractA programmable hybrid circuit is proposed, which is composed of two reconfigurable spoof surface plasmon polariton (SPP) waveguides loaded with varactor diodes and a substrate integrated waveguide (SIW). By manipulating their dispersion behaviors, the band‐pass effect is achieved in the hybrid circuit, in which the upper and lower cutoff frequencies are determined by the SPP waveguide and SIW, respectively. When two SPP waveguides are configured to have the same cutoff frequency that is higher than the SIW's cutoff, the proposed circuit can realize a power division; when one SPP waveguide is reconfigured to reject the waves from SIW, this circuit will be a band‐pass filter. As a typical application, a logic “OR” gate with 2‐bit coding is designed by programming the bias voltages applied to the varactor diodes loaded on the unit structures of the SPP waveguides. All functions are demonstrated by measurement results that agree with numerical simulations very well. The work provides more potential applications in multifunctional integrated circuits and digital communication systems.

Enhancing the Seebeck effect in Ge/Si through the combination of interfacial design features

Due to their inherent physical properties, thin-film Si/SiGe heterostructures have specific thermal management applications in advanced integrated circuits and this in turn is essential not only to prevent a high local temperature and overheat inside the circuit, but also generate electricity through the Seebeck effect. Here, we were able to enhance the Seebeck effect in the germanium composite quantum dots (CQDs) embedded in silicon by increasing the number of thin silicon layers inside the dot (multi-fold CQD material). The Seebeck effect in the CQD structures and multi-layer boron atomic layer-doped SiGe epitaxial films was studied experimentally at temperatures in the range from 50 to 300 K and detailed calculations for the Seebeck coefficient employing different scattering mechanisms were made. Our results show that the Seebeck coefficient is enhanced up to ≈40% in a 3-fold CQD material with respect to 2-fold Ge/Si CQDs. This enhancement was precisely modeled by taking into account the scattering of phonons by inner boundaries and the carrier filtering by the CQD inclusions. Our model is also able to reproduce the observed temperature dependence of the Seebeck coefficient in the B atomic layer-doped SiGe fairly well. We expect that the phonon scattering techniques developed here could significantly improve the thermoelectric performance of Ge/Si materials through further optimization of the layer stacks inside the quantum dot and of the dopant concentrations.