Abstract

Due to their inherent physical properties, thin-film Si/SiGe heterostructures have specific thermal management applications in advanced integrated circuits and this in turn is essential not only to prevent a high local temperature and overheat inside the circuit, but also generate electricity through the Seebeck effect. Here, we were able to enhance the Seebeck effect in the germanium composite quantum dots (CQDs) embedded in silicon by increasing the number of thin silicon layers inside the dot (multi-fold CQD material). The Seebeck effect in the CQD structures and multi-layer boron atomic layer-doped SiGe epitaxial films was studied experimentally at temperatures in the range from 50 to 300 K and detailed calculations for the Seebeck coefficient employing different scattering mechanisms were made. Our results show that the Seebeck coefficient is enhanced up to ≈40% in a 3-fold CQD material with respect to 2-fold Ge/Si CQDs. This enhancement was precisely modeled by taking into account the scattering of phonons by inner boundaries and the carrier filtering by the CQD inclusions. Our model is also able to reproduce the observed temperature dependence of the Seebeck coefficient in the B atomic layer-doped SiGe fairly well. We expect that the phonon scattering techniques developed here could significantly improve the thermoelectric performance of Ge/Si materials through further optimization of the layer stacks inside the quantum dot and of the dopant concentrations.

Highlights

  • Due to dense packaging in high power electronics, the heat generation in chips can reach ~50 W/cm[2], which produces uneven temperature distributions with 5 °C to 30 °C overheated hot spots and decreases the reliability of silicon-based electronic components[1,2,3]

  • Our experiments revealed that this composite quantum dots (CQDs) material can offer significantly enhanced Seebeck effect

  • It is seen that the concentration of Ge atoms in the CQDs layers is about 55%, showing that intermixing of Si and Ge occurs during the growth process, which is a common process in crystallization of Si/Ge multilayers[43,44]

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Summary

Introduction

Due to dense packaging in high power electronics, the heat generation in chips can reach ~50 W/cm[2], which produces uneven temperature distributions with 5 °C to 30 °C overheated hot spots and decreases the reliability of silicon-based electronic components[1,2,3].

Results
Conclusion
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