Integrated Circuit Substrates Research Articles

Thin Copper Plate Defect Detection Based on Lamb Wave Generated by Pulsed Laser in Combination with Laser Heterodyne Interference Technique.

Thin copper plate is widely used in architecture, transportation, heavy equipment, and integrated circuit substrates due to its unique properties. However, it is challenging to identify surface defects in copper strips arising from various manufacturing stages without direct contact. A laser ultrasonic inspection system was developed based on the Lamb wave (LW) produced by a laser pulse. An all-fiber laser heterodyne interferometer is applied for measuring the ultrasonic signal in combination with an automatic scanning system, which makes the system flexible and compact. A 3-D model simulation of an H62 brass specimen was carried out to determine the LW spatial-temporal wavefield by using the COMSOL Multiphysics software. The characteristics of the ultrasonic wavefield were extracted through continuous wavelet transform analysis. This demonstrates that the A0 mode could be used in defect detection due to its slow speed and vibrational direction. Furthermore, an ultrasonic wave at the center frequency of 370 kHz with maximum energy is suitable for defect detection. In the experiment, the size and location of the defect are determined by the time difference of the transmitted wave and reflected wave, respectively. The relative error of the defect position is 0.14% by averaging six different receiving spots. The width of the defect is linear to the time difference of the transmitted wave. The goodness of fit can reach 0.989, and it is in good agreement with the simulated one. The experimental error is less than 0.395 mm for a 5 mm width of defect. Therefore, this validates that the technique can be potentially utilized in the remote defect detection of thin copper plates.

High Speed Copper Plating Process for IC Substrate

The integrated circuit (IC) substrate occupies an interesting place in electronic devices. They serve as the bridge between the integrated circuits and the PCB. In this connecting point, they must meet the requirements of both worlds. They must provide the high density of connections to match the IC chip, while at the same time be a stable and robust platform for the chip to reside on. The IC substrate feature sizes and uniformity requirements are moving closer to what is required in the semi-conductor industry, except these substrates must be made at a scale, speed, and cost expected in the PCB industry. In this paper, we present an acid copper electrolyte for plating 2 in 1 redistribution layers (RDL), with small vias and fine lines down to 10µm wide. The electrolytic process successfully plates these features, while maintaining a uniform surface across the panel. The 510 mm x 515 mm panel had less than 5% variation in Cu thickness. The electrolyte was evaluated in a vertical continuous plating (VCP) style tool and a tool that plates panels at high speed. The standard VCP tool operated around 1.0 – 3.0 ASD, whereas the high-speed plater operated around 4.5 – 6.5 ASD. The obvious benefit of the high-speed tool was to reduce the plating time, but it also provided new degrees of control that are not available in VCPs. In either tool, the electrolyte performed well and produced uniform deposits that met the physical requirements that IC substrate applications demand.

Addressing Advanced IC Substrate Deformation and Pattern Distortion Using an Extremely Large Exposure Field Fine Fine-Resolution Lithography System

The More than Moore era is upon us, as manufacturers increasingly turn to back-end advances to meet the next-generation device performance gains of today and tomorrow. In the advanced packaging space, heterogeneous integration combines multiple chips with different functionalities and from different silicon nodes inside one package, ranging in size from 75mm x 75mm to 175mm x 175mm. But as with any new technology, heterogeneous integration comes with its own set of unique challenges. For starters, package sizes are expected to grow significantly due to the number of components making up each integrated package. The problem: these significantly larger packages would typically require multiple exposure shots to complete the lithography steps for the package. Furthermore, the process of adding multiple redistribution layers (RDL) may cause stress to both the surface and inside of the substrate. Formation changes experienced by the panel, as a result of thermal, high-pressure and other fan-out processes, shift the design location from its nominal coordinates; this causes inaccurate overlay and low-overlay yield in the lithography process. And then there is the matter of tightening resolution requirements. RDL layers in advanced integrated circuit substrates (AICS) will require a resolution of 3µm and will eventually move toward a resolution of 1µm. To address these challenges, and better enable the heterogenous integration process, an extremely large exposure field, fine-resolution lithography solution was proposed to enable packages over 250mm x 250mm without the need for image stitching, while exceeding the overlay and critical dimension uniformity requirements for these packages. In this paper, a 515mm x 510mm Ajinomoto build-up film (ABF)+copper clad laminate (CCL) substrate is selected as the test vehicle. We will analyze the pattern distortion of an ABF+CCL substrate to understand the distribution of translation, rotation, scale, magnification, trap, orthogonality and other errors in the substrate, and then use an extremely large exposure field, fine-resolution lithography system to address the pattern distortion of the substrate. This demonstration will provide an analysis of panel distortion and detail how the extremely large exposure field, fine-resolution lithography solution addresses panel distortion to achieve an aggressive overlay number.

CMOS substrate RC netlist reduction towards design cycle speed up

Integrated circuit substrate crosstalk is an effect with significant impact on design cycle and silicon success. Its accurate simulation comprises a significant design cycle acceleration means. A seamless way to incorporate the substrate crosstalk effect into the simulation is through a netlist describing the electrical behaviour of the substrate. Since such a netlist contains connections between all substrate contacts, it is extremely large for simulators to handle. Therefore it should be reduced, preserving the related accuracy and enabling simulation. In this work a methodology exploiting geometrical and electrical properties of the structure is applied, leading to a practical netlist. This netlist enables rapid simulation providing crucial information versus impact of the substrate crosstalk on system on chip performance.

Spatial and Channel-Wise Co-Attention-Based Twin Network System for Inspecting Integrated Circuit Substrate

Spatial and Channel-Wise Co-Attention-Based Twin Network System for Inspecting Integrated Circuit Substrate

Robust Inspection of Integrated Circuit Substrates Based on Twin Network With Image Transform and Suppression Modules

Robust Inspection of Integrated Circuit Substrates Based on Twin Network With Image Transform and Suppression Modules

Characterization of cordierite based h‐BN doped ceramics as an electronic substrate/circuit board material

AbstractIn this study, h‐BN was added to the cordierite composition obtained from zeolite, which was prepared by the determined stoichiometry to facilitate machinability and increase thermal conductivity. Sintering behavior, hardness, machinability, and thermal/electrical properties of the samples obtained by sintering the compounds at different times were investigated. Thanks to these features, it is aimed to use cordierite as an alternative material to integrated circuit substrates and electronic packaging materials. The produced samples were analyzed by X‐ray diffraction analysis, examined by scanning electron microscopy, and field emission scanning electron microscopy. Afterward, thermal properties such as thermal diffusivity, thermal conductivity, and electrical properties such as electrical conductivity and dielectric permittivity were measured. The hardness and machinability of samples were investigated. Cordierite, spinel, glassy phase, and h‐BN phase were detected, and it was observed that the blocky cordierite grains turned into equiaxed grains with the increase of the h‐BN. According to the results obtained from the thermal conductivity test, it was seen that the h‐BN additive increased the thermal conductivity value in general. In addition, it was determined that with the increase of h‐BN, the hardness decreased, and the machinability properties of the samples improved.

Crystallization kinetic and dielectric properties of CaO–MgO–Al2O3–SiO2 glass/Al2O3 composites

Abstract The sintering behavior and the dielectric properties of CaO–MgO–Al2O3–SiO2 (CMAS) glass and CMAS glass/Al2O3 ceramic composites were studied by the combination of differential scanning calorimetry, X-ray diffraction and scanning electron microscopy as well as dielectric properties measurement. The results demonstrate that the CMAS glass with composition 25CaO-15MgO-12Al2O3-48SiO2 (wt.%) can significantly improve the sintering performance of Al2O3 ceramics, and does not lead to an obvious decrease in the dielectric properties. Low dielectric constant and low dielectric loss were obtained when sintering the CMAS/Al2O3 composites at 1273 K, which demonstrate that it satisfies the requirement of the integrated circuit substrate materials when working at high frequency.

Investigation of the mechanical characteristics of the Cu/low-k BEOL under wire bonding process loading

ABSTRACT Wire bonding is a key integrated circuit (IC) interconnect technology, and it adheres metal wires to the IC pad and substrate by applying significant compression and energic loading. On the other hand, the Cu/low-k technology of the advanced IC industry is driven by the market demands of small size, and low resistance-capacitance delay applications. Because material properties of Cu/low-k back end of line (BEOL) exhibit significant differences from the conventional Al-based system, 3 new reliability failure modes are introduced after the wire bonding process, including the Al pad lift, Cu pad lift and the nanoscaled Cu diffusion barrier crack. To study the mechanical characteristics of the Cu/low-k BEOL under the wire bonding process loading, this research establishes a set of transient numerical models with mesh control and computation acceleration techniques. The mechanical characteristics of the wire bonding process and the differences between the conventional and Cu/low-k BEOLs are analyzed via the detailed analysis of the historical stress plots over the wire bonding process time. Moreover, the risks of wire bonding induced the failure modes against different Cu/low-k designs are studied by the proper mechanical indices, and optimized design trends are suggested.

A Novel Feature Extraction Algorithm and System for Flexible Integrated Circuit Packaging Substrate.

Aiming at the line defect detection of a flexible integrated circuit substrate (FICS) without reference template, there are some problems such as line discontinuity or inaccurate line defect location in the detection results. In order to address these problems, a line feature detection algorithm for extracting an FICS image is proposed. Firstly, FICS image acquisition is carried out by using the appearance defect intelligent detection system independently developed in our lab. Secondly, in the algorithm design of the software system, the binary image of the line image to be segmented is obtained after the color FICS image is classified by K-means, median filtering, morphological filling and closed operation. Finally, for an FICS binary image, an image segmentation model with convexity-preserving indirect regular level set is proposed, which is applied to extract the line features of an FICS image. Experiment results show that, compared with the CV model, LBF model, LCV model, LGIF model, Order-LBF model and RSF model, the proposed model can extract line features with high accuracy, and the line boundary is smooth, which lays an important foundation for high-precision measurement of line width and line distance and high-precision location of defects.

A novel solder joint diagnosis algorithm using differential geometry approach in high-density flexible integrated circuit substrates

To provide a system with high-density solder joint 3D information acquisition and improve the comprehensive performance of automatic optical inspection systems, a novel diagnosis system for solder joints of high-density flexible integrated circuit substrates is proposed in this paper. The differential geometry principle is introduced to analyze the appearance identity of solder joints, and the diagnosis is handled as a pattern-recognition problem with the Frenet frame-matching approach. First, a high-precision 3D information-acquisition system constituted of two CCD digital cameras, each with a microscope and a three-color LED illumination, is developed. Second, a discrete estimation scheme based on the differential geometry theory is proposed to achieve curvature measurement, and then the shape of the solder joints is characterized by the crest line representation method. Finally, the classification strategy is to establish different models of solder joint types and make a decision based on a set of the predefined diagnosis rules. By inspecting various types of solder joints and comparing with other typical algorithms, the performance of the proposed system is evaluated. The experiment results indicate that the proposed algorithm has advantages of fast inspection speed, low misjudgment rate, which is reduced to 2.2%, and detailed classification.

A Novel Authentication Methodology to Detect Counterfeit PCB Using PCB Trace-Based Ring Oscillator

The existence of counterfeit products, e.g., integrated circuits (ICs) and printed circuit boards (PCBs), in the modern semiconductor supply chain has seriously jeopardized the security and reliability of electronic systems, and has also caused the loss of suppliers’ profit and reputation. Most of existing research papers prevent or detect counterfeit IC and PCB substrate separately, without testing the PCB as a whole, and often require the assistance of external equipment. In this article, a novel ring oscillator-based PCB authentication (ROPA) methodology to detect counterfeit PCB through supply chain is proposed, which utilizes PCB trace-based ring oscillators (PTRO) assisted by on-chip ring oscillators, and a novel PCB signature extraction methodology. By switching the PCB to different load modes, the signature can reflect the process variations in PCB traces and overall impedance. The ROPA can provide both IC and PCB authentication independently of external equipments, and allows remote authentication for the user. The ROPA structure has shown advantageous area (0.301% on average) and power (0.355% on average) overhead when implemented on a number of benchmarks. Then the ROPA is implemented on a set of authentic and counterfeit FPGA development boards to verify the effectiveness on counterfeit detection. The results show that the proposed method provides 96.7% confidence in detecting tampered PCBs and 100% confidence in detecting overproduced, recycled, and cloned PCBs.

An improved measure of quality loss for notching processes

AbstractNowadays, electronic products are progressively becoming thinner, lighter, and more convenient for people to use. Printed circuit boards, and especially integrated circuit (IC) substrates, are among the essential component of these products. The IC substrate not only protects circuits, fixes lines, and conducts heat, but is also the critical component that provides signal connectivity between the chip, the printed circuit boards, and other crucial parts during the packaging process. The process capability index Cpm is commonly used to assess the product quality loss for decision making in modern semiconductor packaging manufacturing. For high‐definition products, packaging processes often have very strict quality requirements and thus the quality inspection procedure is time‐consuming and complicated. Therefore, because of the limitation of manpower and capacity of the inspection instruments, the collected sample for quality assessment may be with small to moderate sample sizes. In this paper, we introduce an unbiased estimator for Cpm and provide a step‐by‐step parametric bootstrap procedure for obtaining a composite lower confidence bound on Cpm. To compare with the approaches discussed in the literature, numerical simulations are conducted under various process parameter settings. The results show that for small to moderate sample sizes, the proposed method applying the unbiased estimator has more accurate coverage rates than the existing methods. At the end of this paper, an application of quality loss assessment in notching processes is demonstrated.

A fast oxidation region detection algorithm based on differential geometry approach for high-density flexible integrated circuit packaging substrates

Vision inspection has been widely used in the field of defect measurement as a noncontact, nondestructive measurement technique. Conventional visual defect detection methods rely heavily on standard templates and image features, but the standard templates are either difficult to obtain or do not exist in many application fields, especially in flexible integrated circuit (IC) substrate defect detection at a microscopic level. To solve the above problems, a rapid online oxidation defect detection algorithm for micron-level flexible IC substrate oxidation defects, based on the differential geometric approach, is proposed in this paper. First, the sample fitting model is established by using minimal generalized variance as well as the surface fitting model. Second, the defect area of the substrate is determined by analyzing the similarity and membership, which is coded among the pixels by considering the spatial topological structure of the image. Finally, experiments are performed to show that the algorithm proposed in this paper not only has high precision, but also meets industrial real-time requirements for the rapid production of a flexible substrate. Since the method does not depend on the standard template of the original image, it can achieve vision detection effects at high speed and with high precision.

Detection of oxidation region of flexible integrated circuit substrate based on topology mapping

Vision inspection has been extensively used in the field of defect measurement field as a non-contact and nondestructive measurement technique. The conventional methods of visual defect detection rely heavily on the standard templates and features of image, but the standard templates are difficult to obtain or even don’t exist in many application fields especially for the field of flexible Integrated Circuit (IC) substrate defect detection based on micro vision. To solve the above problems, an algorithm of oxidation defects detection based on topology mapping. First, the filter template of weighted average neighborhood closed curve based on topology mapping is used to remove the image noise. Second, an image segmentation method is proposed by using the idea of maximum variance between classes to find out the threshold, then the spatially filtered is used to remove the normal surface texture and the structure of the substrate which is introduced by metallographic microscope enlargement. Finally, experiments are performed to show that the filter template of weighted average neighborhood closed curve is better than the existing filters and effectively removes image noise, then the segmentation method in this paper works better.

Understanding AlN Obtaining Through Computational Thermodynamics Combined with Experimental Investigation

Basic material concept, technology and some results of studies on aluminum matrix composite with dispersive aluminum nitride reinforcement was shown. Studied composites were manufactured by „in situ” technique. Aluminum nitride (AlN) has attracted large interest recently, because of its high thermal conductivity, good dielectric properties, high flexural strength, thermal expansion coefficient matches that of Si and its non-toxic nature, as a suitable material for hybrid integrated circuit substrates. AlMg alloys are the best matrix for AlN obtaining. Al2O3–AlMg, AlN–Al2O3, and AlN–AlMg binary diagrams were thermodynamically modelled. The obtained Gibbs free energies of components, solution parameters and stoichiometric phases were used to build a thermodynamic database of AlN– Al2O3–AlMg system. Obtaining of AlN with Liquid-phase of AlMg as matrix has been studied and compared with the thermodynamic results. The secondary phase microstructure has a significant effect on the final thermal conductivity of the obtained AlN. Thermodynamic modelling of AlN–Al2O3–AlMg system provided an important basis for understanding the obtaining behavior and interpreting the experimental results.

Enhanced blue emission of ZnO films deposited on AlN substrates

Taking into account the individual excellent optical properties of ZnO and AlN, the combination of ZnO with AlN may give the enhanced performances. Based on similar lattice constants between ZnO and AlN, considering that AlN is a promising high power integrated circuit substrate material, ZnO films are deposited on AlN substrates using magnetron sputtering. We find that AlN substrate shows an excellent transparency with an average transmittance of about 80%. As ZnO films are deposited on AlN substrate, average transmittance still maintain above 80% except for the UV absorption edge shifted to the longer wavelength. In addition, AlN substrate shows two emission peaks at 420 and 468nm ascribed to Al vacancies with different charge states. As ZnO films are deposited on AlN substrates in pure Ar gas, the intensity of both peaks attain the maximum. After introducing O2 gas, they conversely decreases and attains the minimum. PL emissions increase again as the sample is annealed in vacuum. Excellent blue emissions are obtained due to the synergistic effect between ZnO and AlN. This work may help the development of the practical optoelectronic devices based on ZnO and AlN materials.

Glass 3D Solenoid Inductors IPD Substrate Manufacturing Assembly and Characterization

Abstract This paper aims to discuss the integration of 3D solenoid inductors fabricated by using a glass core substrate with through glass via (TGV) technology. Glass materials were chosen for the substrate core based on the natural properties of low insertion loss, adjustable CTE, low surface roughness and high insulation for RF application. The TGV formation and semi-additive conformal copper electroplating were the key processes of the glass core substrate manufacturing. The key benefits of these evaluations are a competitive cost structure for a 508mm × 508mm glass panel IC (integrated circuit) substrate HVM (high volume manufacture) line. The characterization results of TGV formation, the process flow of 3D solenoid inductor glass core substrate and real silicon device chips assembled on the top of glass core substrate were also investigated and discussed.

Methodology for Coupling and Interference Prediction in Integrated-Circuit Substrates

This paper presents a methodology to evaluate different integrated-circuit substrate technology options in terms of interference coupling. It is based on the electromagnetic characterization of the different substrate configurations as radial multilayered dielectric lossy open waveguides and the selection of the propagation modes that effectively contribute to substrate coupling. In addition, attenuation patterns are obtained for different technologies, doping profiles, frequencies, and interference mechanisms in order to provide a tool for early interference prediction, electromagnetic compatibility performance evaluation and floorplan strategy definition.

Micro drilling quality of the Cu/BT laminate for IC substrate

Purpose In an integrated circuit (IC) substrate, more fillers, including talcum powder and aluminium hydroxide, are added, which leads to much higher rigidity and hardness compared with a traditional printed circuit board. However, the micro drilling of IC substrates is harder. This paper aims to test the drilling process of IC substrates to improve the drilling process and the micro hole quality. Design/methodology/approach Substrate drilling by a micro drill with 0.11-mm diameter was used under several drilling conditions. The influence of drilling conditions on the drilling process was observed. Drilling forces, drill wear and micro hole quality were also studied. Findings The deformation circle around holes, hole location accuracy, bugle hole and burrs were the major defects of micro holes that were observed during the drilling of the substrate. Reducing the drilling force and drill wear was the effective way to improve hole quality. Originality/value The technology and manufacturing of IC substrates has been little investigated. Research data on drilling IC substrates is lacking. The micro hole quality directly affects the reliability of IC substrates. Thus, improving the drilling technology of IC substrates is very important.